17f2b7720SXuan Hupackage xiangshan.backend.decode 27f2b7720SXuan Hu 37f2b7720SXuan Huimport chipsalliance.rocketchip.config.Parameters 47f2b7720SXuan Huimport chisel3._ 57f2b7720SXuan Huimport chisel3.util._ 67f2b7720SXuan Huimport freechips.rocketchip.util.uintToBitPat 73a2e64c4SZhangZifeiimport freechips.rocketchip.rocket.Instructions._ 87f2b7720SXuan Huimport utils._ 97f2b7720SXuan Huimport xiangshan.ExceptionNO.illegalInstr 107f2b7720SXuan Huimport xiangshan._ 113a2e64c4SZhangZifeiimport yunsuan.{VipuType, VfpuType} 127f2b7720SXuan Hu 137f2b7720SXuan Huabstract class VecType { 147f2b7720SXuan Hu def X = BitPat("b?") 157f2b7720SXuan Hu def N = BitPat("b0") 167f2b7720SXuan Hu def Y = BitPat("b1") 177f2b7720SXuan Hu def generate() : List[BitPat] 187f2b7720SXuan Hu def asOldDecodeOutput(): List[BitPat] = { 197f2b7720SXuan Hu val src1::src2::src3::fu::fuOp::xWen::fWen::vWen::mWen::xsTrap::noSpec::blockBack::flushPipe::selImm::Nil = generate() 207f2b7720SXuan Hu List (src1, src2, src3, fu, fuOp, xWen, fWen, xsTrap, noSpec, blockBack, flushPipe, selImm) 217f2b7720SXuan Hu } 227f2b7720SXuan Hu} 237f2b7720SXuan Hu 24*58c35d23Shuxuan0307case class OPIVV(op0: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean) extends VecType { 257f2b7720SXuan Hu def generate() : List[BitPat] = { 26*58c35d23Shuxuan0307 List (SrcType.vp, SrcType.vp, op0, fu, fuOp, N, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, SelImm.X) 277f2b7720SXuan Hu } 287f2b7720SXuan Hu} 297f2b7720SXuan Hu 30*58c35d23Shuxuan0307case class OPIVX(op0: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean) extends VecType { 31*58c35d23Shuxuan0307 def generate() : List[BitPat] = { 32*58c35d23Shuxuan0307 List (SrcType.xp, SrcType.vp, op0, fu, fuOp, N, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, SelImm.X) 33*58c35d23Shuxuan0307 } 347f2b7720SXuan Hu} 357f2b7720SXuan Hu 36*58c35d23Shuxuan0307case class OPIVI(op0: BitPat, fu: BitPat, fuOp: BitPat, vWen: Boolean, mWen: Boolean, vxsatWen: Boolean, selImm: BitPat) extends VecType { 37*58c35d23Shuxuan0307 def generate() : List[BitPat] = { 38*58c35d23Shuxuan0307 List (SrcType.imm, SrcType.vp, op0, fu, fuOp, N, N, vWen.B, mWen.B, vxsatWen.B, N, N, N, selImm) 39*58c35d23Shuxuan0307 } 407f2b7720SXuan Hu} 417f2b7720SXuan Hu 42c6661c33SHaojin Tangcase class OPMVV(vdRen: Boolean, fu: BitPat, fuOp: BitPat, xWen: Boolean, vWen: Boolean, mWen: Boolean, others: Any) extends VecType { 43c6661c33SHaojin Tang private def src3: BitPat = if (vdRen) SrcType.vp else SrcType.X 447f2b7720SXuan Hu def generate() : List[BitPat] = { 45c6661c33SHaojin Tang List (SrcType.vp, SrcType.vp, src3, fu, fuOp, xWen.B, N, vWen.B, mWen.B, N, N, N, N, SelImm.X) 467f2b7720SXuan Hu } 477f2b7720SXuan Hu} 487f2b7720SXuan Hu 49c6661c33SHaojin Tangcase class OPMVX(vdRen: Boolean, fu: BitPat, fuOp: BitPat, xWen: Boolean, vWen: Boolean, mWen: Boolean, others: Any) extends VecType { 50c6661c33SHaojin Tang private def src3: BitPat = if (vdRen) SrcType.vp else SrcType.X 51c6661c33SHaojin Tang def generate() : List[BitPat] = { 52c6661c33SHaojin Tang List (SrcType.xp, SrcType.vp, src3, fu, fuOp, xWen.B, N, vWen.B, mWen.B, N, N, N, N, SelImm.X) 53c6661c33SHaojin Tang } 547f2b7720SXuan Hu} 557f2b7720SXuan Hu 56b448988dSczwcase class OPFVV(src1:BitPat, src3:BitPat, fu: BitPat, fuOp: BitPat, fWen: Boolean, vWen: Boolean, mWen: Boolean) extends VecType { 57b448988dSczw def generate() : List[BitPat] = { 58b448988dSczw List (src1, SrcType.vp, src3, fu, fuOp, N, fWen.B, vWen.B, mWen.B, N, N, N, N, SelImm.X) 59b448988dSczw } 607f2b7720SXuan Hu} 617f2b7720SXuan Hu 62b448988dSczwcase class OPFVF(src1:BitPat, src3:BitPat, fu: BitPat, fuOp: BitPat, fWen: Boolean, vWen: Boolean, mWen: Boolean) extends VecType { 637f2b7720SXuan Hu def generate() : List[BitPat] = { 64b448988dSczw List (src1, SrcType.vp, src3, fu, fuOp, N, fWen.B, vWen.B, mWen.B, N, N, N, N, SelImm.X) 657f2b7720SXuan Hu } 667f2b7720SXuan Hu} 677f2b7720SXuan Hu 687f2b7720SXuan Hucase class VSET() extends VecType { 697f2b7720SXuan Hu def generate() : List[BitPat] = { null } 707f2b7720SXuan Hu} 717f2b7720SXuan Hu 727f2b7720SXuan Hucase class VLS() extends VecType { 737f2b7720SXuan Hu def generate() : List[BitPat] = { null } 747f2b7720SXuan Hu} 757f2b7720SXuan Hu 767f2b7720SXuan Huobject VecDecoder extends DecodeConstants { 777f2b7720SXuan Hu private def F = false 787f2b7720SXuan Hu private def T = true 797f2b7720SXuan Hu 807f2b7720SXuan Hu val opivvTable: Array[(BitPat, List[BitPat])] = Array( 81*58c35d23Shuxuan0307 VADD_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 82*58c35d23Shuxuan0307 VSUB_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 837f2b7720SXuan Hu 84*58c35d23Shuxuan0307 VMINU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 85*58c35d23Shuxuan0307 VMIN_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 86*58c35d23Shuxuan0307 VMAXU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 87*58c35d23Shuxuan0307 VMAX_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 88*58c35d23Shuxuan0307 89*58c35d23Shuxuan0307 VAND_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 90*58c35d23Shuxuan0307 VOR_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 91*58c35d23Shuxuan0307 VXOR_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 92*58c35d23Shuxuan0307 93*58c35d23Shuxuan0307 VRGATHER_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 94*58c35d23Shuxuan0307 VRGATHEREI16_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 95*58c35d23Shuxuan0307 96*58c35d23Shuxuan0307 VADC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F).generate(), 97*58c35d23Shuxuan0307 VMADC_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 98*58c35d23Shuxuan0307 VMADC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F).generate(), 99*58c35d23Shuxuan0307 100*58c35d23Shuxuan0307 VSBC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F).generate(), 101*58c35d23Shuxuan0307 VMSBC_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 102*58c35d23Shuxuan0307 VMSBC_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F).generate(), 103*58c35d23Shuxuan0307 104*58c35d23Shuxuan0307 VMERGE_VVM -> OPIVV(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F).generate(), 105*58c35d23Shuxuan0307 106*58c35d23Shuxuan0307 VMSEQ_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 107*58c35d23Shuxuan0307 VMSNE_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 108*58c35d23Shuxuan0307 VMSLTU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 109*58c35d23Shuxuan0307 VMSLT_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 110*58c35d23Shuxuan0307 VMSLEU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 111*58c35d23Shuxuan0307 VMSLE_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 112*58c35d23Shuxuan0307 113*58c35d23Shuxuan0307 VSLL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 114*58c35d23Shuxuan0307 VSRL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 115*58c35d23Shuxuan0307 VSRA_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 116*58c35d23Shuxuan0307 VNSRL_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 117*58c35d23Shuxuan0307 VNSRA_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 118*58c35d23Shuxuan0307 119*58c35d23Shuxuan0307 VSADDU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 120*58c35d23Shuxuan0307 VSADD_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 121*58c35d23Shuxuan0307 VSSUBU_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 122*58c35d23Shuxuan0307 VSSUB_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 123*58c35d23Shuxuan0307 124*58c35d23Shuxuan0307 VSMUL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 125*58c35d23Shuxuan0307 126*58c35d23Shuxuan0307 VSSRL_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 127*58c35d23Shuxuan0307 VSSRA_VV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 128*58c35d23Shuxuan0307 129*58c35d23Shuxuan0307 VNCLIPU_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 130*58c35d23Shuxuan0307 VNCLIP_WV -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 131*58c35d23Shuxuan0307 132*58c35d23Shuxuan0307 VWREDSUMU_VS -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 133*58c35d23Shuxuan0307 VWREDSUM_VS -> OPIVV(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 1347f2b7720SXuan Hu ) 1357f2b7720SXuan Hu 136*58c35d23Shuxuan0307 val opivxTable: Array[(BitPat, List[BitPat])] = Array( 137*58c35d23Shuxuan0307 VADD_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 138*58c35d23Shuxuan0307 VSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 139*58c35d23Shuxuan0307 VRSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 140*58c35d23Shuxuan0307 141*58c35d23Shuxuan0307 VMINU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 142*58c35d23Shuxuan0307 VMIN_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 143*58c35d23Shuxuan0307 VMAXU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 144*58c35d23Shuxuan0307 VMAX_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 145*58c35d23Shuxuan0307 146*58c35d23Shuxuan0307 VAND_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 147*58c35d23Shuxuan0307 VOR_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 148*58c35d23Shuxuan0307 VXOR_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 149*58c35d23Shuxuan0307 150*58c35d23Shuxuan0307 VRGATHER_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 151*58c35d23Shuxuan0307 152*58c35d23Shuxuan0307 VSLIDEUP_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 153*58c35d23Shuxuan0307 VSLIDEDOWN_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 154*58c35d23Shuxuan0307 155*58c35d23Shuxuan0307 VADC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F).generate(), 156*58c35d23Shuxuan0307 VMADC_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 157*58c35d23Shuxuan0307 VSBC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F).generate(), 158*58c35d23Shuxuan0307 VMSBC_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 159*58c35d23Shuxuan0307 VMSBC_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, F, T, F).generate(), 160*58c35d23Shuxuan0307 161*58c35d23Shuxuan0307 VMERGE_VXM -> OPIVX(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F).generate(), 162*58c35d23Shuxuan0307 163*58c35d23Shuxuan0307 VMSEQ_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 164*58c35d23Shuxuan0307 VMSNE_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 165*58c35d23Shuxuan0307 VMSLTU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 166*58c35d23Shuxuan0307 VMSLT_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 167*58c35d23Shuxuan0307 VMSLEU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 168*58c35d23Shuxuan0307 VMSLE_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 169*58c35d23Shuxuan0307 VMSGTU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 170*58c35d23Shuxuan0307 VMSGT_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F).generate(), 171*58c35d23Shuxuan0307 172*58c35d23Shuxuan0307 VSLL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 173*58c35d23Shuxuan0307 VSRL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 174*58c35d23Shuxuan0307 VSRA_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 175*58c35d23Shuxuan0307 VNSRL_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 176*58c35d23Shuxuan0307 VNSRA_WX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 177*58c35d23Shuxuan0307 178*58c35d23Shuxuan0307 VSADDU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 179*58c35d23Shuxuan0307 VSADD_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 180*58c35d23Shuxuan0307 VSSUBU_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 181*58c35d23Shuxuan0307 VSSUB_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 182*58c35d23Shuxuan0307 183*58c35d23Shuxuan0307 184*58c35d23Shuxuan0307 VSMUL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 185*58c35d23Shuxuan0307 186*58c35d23Shuxuan0307 VSSRL_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 187*58c35d23Shuxuan0307 VSSRA_VX -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F).generate(), 188*58c35d23Shuxuan0307 189*58c35d23Shuxuan0307 VNCLIPU_WV -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 190*58c35d23Shuxuan0307 VNCLIP_WV -> OPIVX(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T).generate(), 191*58c35d23Shuxuan0307 ) 192*58c35d23Shuxuan0307 193*58c35d23Shuxuan0307 val opiviTable: Array[(BitPat, List[BitPat])] = Array( 194*58c35d23Shuxuan0307 VADD_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(), 195*58c35d23Shuxuan0307 VRSUB_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(), 196*58c35d23Shuxuan0307 197*58c35d23Shuxuan0307 VAND_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(), 198*58c35d23Shuxuan0307 VOR_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(), 199*58c35d23Shuxuan0307 VXOR_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(), 200*58c35d23Shuxuan0307 201*58c35d23Shuxuan0307 VRGATHER_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(), 202*58c35d23Shuxuan0307 203*58c35d23Shuxuan0307 VSLIDEUP_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(), 204*58c35d23Shuxuan0307 VSLIDEDOWN_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(), 205*58c35d23Shuxuan0307 206*58c35d23Shuxuan0307 VADC_VIM -> OPIVI(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(), 207*58c35d23Shuxuan0307 VMADC_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(), 208*58c35d23Shuxuan0307 209*58c35d23Shuxuan0307 VMERGE_VIM -> OPIVI(SrcType.vp, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(), 210*58c35d23Shuxuan0307 211*58c35d23Shuxuan0307 VMSEQ_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS).generate(), 212*58c35d23Shuxuan0307 VMSNE_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS).generate(), 213*58c35d23Shuxuan0307 VMSLEU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS).generate(), 214*58c35d23Shuxuan0307 VMSLE_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS).generate(), 215*58c35d23Shuxuan0307 VMSGTU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS).generate(), 216*58c35d23Shuxuan0307 VMSGT_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, F, T, F, SelImm.IMM_OPIVIS).generate(), 217*58c35d23Shuxuan0307 218*58c35d23Shuxuan0307 VSLL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(), 219*58c35d23Shuxuan0307 VSRL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(), 220*58c35d23Shuxuan0307 VSRA_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(), 221*58c35d23Shuxuan0307 VNSRL_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(), 222*58c35d23Shuxuan0307 VNSRA_WI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(), 223*58c35d23Shuxuan0307 224*58c35d23Shuxuan0307 VSADDU_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIS).generate(), 225*58c35d23Shuxuan0307 VSADD_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIS).generate(), 226*58c35d23Shuxuan0307 227*58c35d23Shuxuan0307 VSSRL_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(), 228*58c35d23Shuxuan0307 VSSRA_VI -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIU).generate(), 229*58c35d23Shuxuan0307 230*58c35d23Shuxuan0307 VNCLIPU_WV -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIU).generate(), 231*58c35d23Shuxuan0307 VNCLIP_WV -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, T, SelImm.IMM_OPIVIU).generate(), 232*58c35d23Shuxuan0307 233*58c35d23Shuxuan0307 VMV1R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(), 234*58c35d23Shuxuan0307 VMV2R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(), 235*58c35d23Shuxuan0307 VMV4R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(), 236*58c35d23Shuxuan0307 VMV8R_V -> OPIVI(SrcType.X, FuType.vipu, VipuType.dummy, T, F, F, SelImm.IMM_OPIVIS).generate(), 237*58c35d23Shuxuan0307 ) 2387f2b7720SXuan Hu 239c6661c33SHaojin Tang val opmvv: Array[(BitPat, OPMVV)] = Array( 240c6661c33SHaojin Tang VAADD_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 241c6661c33SHaojin Tang VAADDU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 242c6661c33SHaojin Tang VASUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 243c6661c33SHaojin Tang VASUBU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 244c6661c33SHaojin Tang VCOMPRESS_VM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 245c6661c33SHaojin Tang VCPOP_M -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F, T), 246c6661c33SHaojin Tang VDIV_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 247c6661c33SHaojin Tang VDIVU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 248c6661c33SHaojin Tang VFIRST_M -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F, T), 249c6661c33SHaojin Tang VID_V -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 250c6661c33SHaojin Tang VIOTA_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 251c6661c33SHaojin Tang VMACC_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F, T), 252c6661c33SHaojin Tang VMADD_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F, T), 253c6661c33SHaojin Tang VMAND_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 254c6661c33SHaojin Tang VMANDN_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 255c6661c33SHaojin Tang VMNAND_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 256c6661c33SHaojin Tang VMNOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 257c6661c33SHaojin Tang VMOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 258c6661c33SHaojin Tang VMORN_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 259c6661c33SHaojin Tang VMXNOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 260c6661c33SHaojin Tang VMXOR_MM -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 261c6661c33SHaojin Tang VMSBF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 262c6661c33SHaojin Tang VMSIF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 263c6661c33SHaojin Tang VMSOF_M -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 264c6661c33SHaojin Tang VMUL_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 265c6661c33SHaojin Tang VMULH_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 266c6661c33SHaojin Tang VMULHSU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 267c6661c33SHaojin Tang VMULHU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 268c6661c33SHaojin Tang VMV_X_S -> OPMVV(F, FuType.vipu, VipuType.dummy, T, F, F, T), 269c6661c33SHaojin Tang VNMSAC_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 270c6661c33SHaojin Tang VNMSUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 271c6661c33SHaojin Tang VREDAND_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 272c6661c33SHaojin Tang VREDMAX_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 273c6661c33SHaojin Tang VREDMAXU_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 274c6661c33SHaojin Tang VREDMIN_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 275c6661c33SHaojin Tang VREDMINU_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 276c6661c33SHaojin Tang VREDOR_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 277c6661c33SHaojin Tang VREDSUM_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 278c6661c33SHaojin Tang VREDXOR_VS -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 279c6661c33SHaojin Tang VREM_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 280c6661c33SHaojin Tang VREMU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 281c6661c33SHaojin Tang VSEXT_VF2 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 282c6661c33SHaojin Tang VSEXT_VF4 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 283c6661c33SHaojin Tang VSEXT_VF8 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 284c6661c33SHaojin Tang VZEXT_VF2 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 285c6661c33SHaojin Tang VZEXT_VF4 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 286c6661c33SHaojin Tang VZEXT_VF8 -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 287c6661c33SHaojin Tang VWADD_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 288c6661c33SHaojin Tang VWADD_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 289c6661c33SHaojin Tang VWADDU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 290c6661c33SHaojin Tang VWADDU_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 291c6661c33SHaojin Tang VWMACC_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F, T), 292c6661c33SHaojin Tang VWMACCSU_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F, T), 293c6661c33SHaojin Tang VWMACCU_VV -> OPMVV(T, FuType.vipu, VipuType.dummy, F, T, F, T), 294c6661c33SHaojin Tang VWMUL_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 295c6661c33SHaojin Tang VWMULSU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 296c6661c33SHaojin Tang VWMULU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 297c6661c33SHaojin Tang VWSUB_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 298c6661c33SHaojin Tang VWSUB_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 299c6661c33SHaojin Tang VWSUBU_VV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T), 300c6661c33SHaojin Tang VWSUBU_WV -> OPMVV(F, FuType.vipu, VipuType.dummy, F, T, F, T) 301c6661c33SHaojin Tang ) 302c6661c33SHaojin Tang val opmvx: Array[(BitPat, OPMVX)] = Array( 303c6661c33SHaojin Tang VAADD_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 304c6661c33SHaojin Tang VAADDU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 305c6661c33SHaojin Tang VASUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 306c6661c33SHaojin Tang VASUBU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 307c6661c33SHaojin Tang VDIV_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 308c6661c33SHaojin Tang VDIVU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 309c6661c33SHaojin Tang VMACC_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F, T), 310c6661c33SHaojin Tang VMADD_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F, T), 311c6661c33SHaojin Tang VMUL_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 312c6661c33SHaojin Tang VMULH_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 313c6661c33SHaojin Tang VMULHSU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 314c6661c33SHaojin Tang VMULHU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 315c6661c33SHaojin Tang VMV_S_X -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 316c6661c33SHaojin Tang VNMSAC_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 317c6661c33SHaojin Tang VNMSUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 318c6661c33SHaojin Tang VREM_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 319c6661c33SHaojin Tang VREMU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 320c6661c33SHaojin Tang VSLIDE1DOWN_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 321c6661c33SHaojin Tang VSLIDE1UP_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 322c6661c33SHaojin Tang VWADD_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 323c6661c33SHaojin Tang VWADD_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 324c6661c33SHaojin Tang VWADDU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 325c6661c33SHaojin Tang VWADDU_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 326c6661c33SHaojin Tang VWMACC_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F, T), 327c6661c33SHaojin Tang VWMACCSU_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F, T), 328c6661c33SHaojin Tang VWMACCU_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F, T), 329c6661c33SHaojin Tang VWMACCUS_VX -> OPMVX(T, FuType.vipu, VipuType.dummy, F, T, F, T), 330c6661c33SHaojin Tang VWMUL_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 331c6661c33SHaojin Tang VWMULSU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 332c6661c33SHaojin Tang VWMULU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 333c6661c33SHaojin Tang VWSUB_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 334c6661c33SHaojin Tang VWSUB_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 335c6661c33SHaojin Tang VWSUBU_VX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T), 336c6661c33SHaojin Tang VWSUBU_WX -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, T) 337c6661c33SHaojin Tang ) 338c6661c33SHaojin Tang val opmvvTable: Array[(BitPat, List[BitPat])] = opmvv.map(x => (x._1, x._2.generate())) 339c6661c33SHaojin Tang val opmvxTable: Array[(BitPat, List[BitPat])] = opmvx.map(x => (x._1, x._2.generate())) 3407f2b7720SXuan Hu 3417f2b7720SXuan Hu 342b448988dSczw val opfvvTable: Array[(BitPat, List[BitPat])] = Array( 343b448988dSczw // OPFVV(fu: BitPat, fuOp: BitPat, fWen: Boolean, vWen: Boolean, mWen: Boolean, others: Any) 344b448988dSczw// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 345f2844384SczwVFADD_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 346f2844384SczwVFSUB_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 347b448988dSczw 348b448988dSczw// 13.3. Vector Widening Floating-Point Add/Subtract Instructions 349f2844384SczwVFWADD_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 350f2844384SczwVFWSUB_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 351f2844384SczwVFWADD_WV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 352f2844384SczwVFWSUB_WV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 353b448988dSczw 354b448988dSczw// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 355f2844384SczwVFMUL_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 356f2844384SczwVFDIV_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 357b448988dSczw 358b448988dSczw// 13.5. Vector Widening Floating-Point Multiply 359f2844384SczwVFWMUL_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 360b448988dSczw 361b448988dSczw// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 362f2844384SczwVFMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 363f2844384SczwVFNMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 364f2844384SczwVFMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 365f2844384SczwVFNMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 366f2844384SczwVFMADD_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 367f2844384SczwVFNMADD_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 368f2844384SczwVFMSUB_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 369f2844384SczwVFNMSUB_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 370b448988dSczw 371b448988dSczw// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 372f2844384SczwVFWMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 373f2844384SczwVFWNMACC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 374f2844384SczwVFWMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 375f2844384SczwVFWNMSAC_VV -> OPFVV(SrcType.vp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 376b448988dSczw 377b448988dSczw// 13.8. Vector Floating-Point Square-Root Instruction 378f2844384SczwVFSQRT_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 379b448988dSczw 380b448988dSczw// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction 381f2844384SczwVFRSQRT7_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 382b448988dSczw 383b448988dSczw// 13.10. Vector Floating-Point Reciprocal Estimate Instruction 384f2844384SczwVFREC7_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 385b448988dSczw 386b448988dSczw// 13.11. Vector Floating-Point MIN/MAX Instructions 387f2844384SczwVFMIN_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 388f2844384SczwVFMAX_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 389b448988dSczw 390b448988dSczw// 13.12. Vector Floating-Point Sign-Injection Instructions 391f2844384SczwVFSGNJ_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 392f2844384SczwVFSGNJN_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 393f2844384SczwVFSGNJX_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 394b448988dSczw 395b448988dSczw// 13.13. Vector Floating-Point Compare Instructions 396f2844384SczwVMFEQ_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 397f2844384SczwVMFNE_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 398f2844384SczwVMFLT_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 399f2844384SczwVMFLE_VV -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 400b448988dSczw 401b448988dSczw// 13.14. Vector Floating-Point Classify Instruction 402f2844384SczwVFCLASS_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 403b448988dSczw 404b448988dSczw// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions 405f2844384SczwVFCVT_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 406f2844384SczwVFCVT_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 407f2844384SczwVFCVT_RTZ_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 408f2844384SczwVFCVT_RTZ_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 409f2844384SczwVFCVT_F_XU_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 410f2844384SczwVFCVT_F_X_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 411b448988dSczw 412b448988dSczw// 13.18. Widening Floating-Point/Integer Type-Convert Instructions 413f2844384SczwVFWCVT_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 414f2844384SczwVFWCVT_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 415f2844384SczwVFWCVT_RTZ_XU_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 416f2844384SczwVFWCVT_RTZ_X_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 417f2844384SczwVFWCVT_F_XU_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 418f2844384SczwVFWCVT_F_X_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 419f2844384SczwVFWCVT_F_F_V -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 420b448988dSczw 421b448988dSczw// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions 422f2844384SczwVFNCVT_XU_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 423f2844384SczwVFNCVT_X_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 424f2844384SczwVFNCVT_RTZ_XU_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 425f2844384SczwVFNCVT_RTZ_X_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 426f2844384SczwVFNCVT_F_XU_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 427f2844384SczwVFNCVT_F_X_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 428f2844384SczwVFNCVT_F_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 429f2844384SczwVFNCVT_ROD_F_F_W -> OPFVV(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 430b448988dSczw 431b448988dSczw// 14.3. Vector Single-Width Floating-Point Reduction Instructions 432f2844384SczwVFREDOSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 433f2844384SczwVFREDUSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 434f2844384SczwVFREDMAX_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 435f2844384SczwVFREDMIN_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 436b448988dSczw 437b448988dSczw// 14.4. Vector Widening Floating-Point Reduction Instructions 438f2844384SczwVFWREDOSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 439f2844384SczwVFWREDUSUM_VS -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 440b448988dSczw 441b448988dSczw// 16.2. Floating-Point Scalar Move Instructions 442f2844384SczwVFMV_F_S -> OPFVV(SrcType.vp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),// f[rd] = vs2[0] (rs1=0) 443b448988dSczw 444b448988dSczw 445b448988dSczw 446b448988dSczw ) 4477f2b7720SXuan Hu 4487f2b7720SXuan Hu val opfvfTable: Array[(BitPat, List[BitPat])] = Array( 449b448988dSczw// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 450b448988dSczwVFADD_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 451b448988dSczwVFSUB_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 452b448988dSczwVFRSUB_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 453b448988dSczw 454b448988dSczw// 13.3. Vector Widening Floating-Point Add/Subtract Instructions 455b448988dSczwVFWADD_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 456b448988dSczwVFWSUB_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 457b448988dSczwVFWADD_WF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 458b448988dSczwVFWSUB_WF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 459b448988dSczw 460b448988dSczw// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 461b448988dSczwVFMUL_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 462b448988dSczwVFDIV_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 463b448988dSczwVFRDIV_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 464b448988dSczw 465b448988dSczw// 13.5. Vector Widening Floating-Point Multiply 466b448988dSczwVFWMUL_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 467b448988dSczw 468b448988dSczw// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 469b448988dSczwVFMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 470b448988dSczwVFNMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 471b448988dSczwVFMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 472b448988dSczwVFNMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 473b448988dSczwVFMADD_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 474b448988dSczwVFNMADD_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 475b448988dSczwVFMSUB_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 476b448988dSczwVFNMSUB_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 477b448988dSczw 478b448988dSczw// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 479b448988dSczwVFWMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 480b448988dSczwVFWNMACC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 481b448988dSczwVFWMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 482b448988dSczwVFWNMSAC_VF -> OPFVF(SrcType.fp, SrcType.vp, FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 483b448988dSczw 484b448988dSczw// 13.11. Vector Floating-Point MIN/MAX Instructions 485b448988dSczwVFMIN_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 486b448988dSczwVFMAX_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 487b448988dSczw 488b448988dSczw// 13.12. Vector Floating-Point Sign-Injection Instructions 489b448988dSczwVFSGNJ_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 490b448988dSczwVFSGNJN_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 491b448988dSczwVFSGNJX_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 492b448988dSczw 493b448988dSczw// 13.13. Vector Floating-Point Compare Instructions 494b448988dSczwVMFEQ_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T).generate(), 495b448988dSczwVMFNE_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T).generate(), 496b448988dSczwVMFLT_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T).generate(), 497b448988dSczwVMFLE_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T).generate(), 498b448988dSczwVMFGT_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T).generate(), 499b448988dSczwVMFGE_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, F, T).generate(), 500b448988dSczw 501b448988dSczw// 13.15. Vector Floating-Point Merge Instruction 502b448988dSczwVFMERGE_VFM -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(), 503b448988dSczw 504b448988dSczw// 13.16. Vector Floating-Point Move Instruction 505b448988dSczwVFMV_V_F -> OPFVF(SrcType.X , SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),// src2=SrcType.X 506b448988dSczw 507b448988dSczw// 16.2. Floating-Point Scalar Move Instructions 508b448988dSczwVFMV_S_F -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),// vs2=0 509b448988dSczw 510b448988dSczw// 16.3.3. Vector Slide1up 511b448988dSczw// vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] 512b448988dSczwVFSLIDE1UP_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),// vd[0]=f[rs1], vd[i+1] = vs2[i] 513b448988dSczw 514b448988dSczw// 16.3.4. Vector Slide1down Instruction 515b448988dSczw// vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] 516b448988dSczwVFSLIDE1DOWN_VF -> OPFVF(SrcType.fp, SrcType.X , FuType.vfpu, VfpuType.dummy, F, T, F).generate(),// vd[i] = vs2[i+1], vd[vl-1]=f[rs1] 517b448988dSczw 5187f2b7720SXuan Hu ) 5197f2b7720SXuan Hu 5207f2b7720SXuan Hu val vsetTable: Array[(BitPat, List[BitPat])] = Array() 5217f2b7720SXuan Hu val vlsTable: Array[(BitPat, List[BitPat])] = Array() 5227f2b7720SXuan Hu 5237f2b7720SXuan Hu val table = opivvTable ++ opivxTable ++ opiviTable ++ 5247f2b7720SXuan Hu opmvvTable ++ opmvxTable ++ 5257f2b7720SXuan Hu opfvvTable ++ opfvfTable ++ 5267f2b7720SXuan Hu vsetTable ++ vlsTable 5277f2b7720SXuan Hu} 528