xref: /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala (revision e88008978ecb7073b9e8126282e0a0b913d9e6f7)
1/***************************************************************************************
2  * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3  * Copyright (c) 2020-2021 Peng Cheng Laboratory
4  *
5  * XiangShan is licensed under Mulan PSL v2.
6  * You can use this software according to the terms and conditions of the Mulan PSL v2.
7  * You may obtain a copy of Mulan PSL v2 at:
8  *          http://license.coscl.org.cn/MulanPSL2
9  *
10  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11  * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12  * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13  *
14  * See the Mulan PSL v2 for more details.
15  ***************************************************************************************/
16
17package xiangshan.backend.decode
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import freechips.rocketchip.rocket.Instructions
23import freechips.rocketchip.util.uintToBitPat
24import utils._
25import utility._
26import xiangshan.ExceptionNO.illegalInstr
27import xiangshan._
28import xiangshan.backend.fu.fpu.FPU
29import xiangshan.backend.fu.FuType
30import freechips.rocketchip.rocket.Instructions._
31import xiangshan.backend.Bundles.{DecodedInst, StaticInst}
32import xiangshan.backend.fu.vector.Bundles.{VType, VLmul, VSew}
33import yunsuan.VpermType
34
35class UopInfoGen (implicit p: Parameters) extends XSModule {
36  val io = IO(new UopInfoGenIO)
37
38  val typeOfSplit = io.in.preInfo.typeOfSplit
39  val vsew = Cat(0.U(1.W), io.in.preInfo.vsew)
40  val veew = Cat(0.U(1.W), io.in.preInfo.vwidth(1, 0))
41  val vmvn = io.in.preInfo.vmvn
42  val vlmul = io.in.preInfo.vlmul
43  val isComplex = io.out.isComplex
44
45  val lmul = MuxLookup(vlmul, 1.U(4.W), Array(
46    "b001".U -> 2.U,
47    "b010".U -> 4.U,
48    "b011".U -> 8.U
49  ))
50
51  val vemul: UInt = veew.asUInt + 1.U + vlmul.asUInt + ~vsew.asUInt
52
53  val emul = MuxLookup(vemul, 1.U(4.W), Array(
54    "b001".U -> 2.U,
55    "b010".U -> 4.U,
56    "b011".U -> 8.U
57  ))                                                              //TODO : eew and emul illegal exception need to be handled
58
59  val numOfUopVslide = MuxLookup(vlmul, 1.U(log2Up(MaxUopSize + 1).W), Array(
60    "b001".U -> 3.U,
61    "b010".U -> 10.U,
62    "b011".U -> 36.U
63  ))
64  val numOfUopVrgather = MuxLookup(vlmul, 1.U(log2Up(MaxUopSize + 1).W), Array(
65    "b001".U -> 4.U,
66    "b010".U -> 16.U,
67    "b011".U -> 64.U
68  ))
69  val numOfUopVrgatherei16 = Mux((!vsew.orR) && (vlmul =/= "b011".U),
70    Cat(numOfUopVrgather, 0.U(1.W)),
71    numOfUopVrgather
72  )
73  val numOfUopVcompress = MuxLookup(vlmul, 1.U(4.W), Array(
74    "b001".U -> 4.U,
75    "b010".U -> 13.U,
76    "b011".U -> 43.U
77  ))
78  val numOfUopVFRED = {
79    // addTime include add frs1
80     val addTime = MuxLookup(vlmul, 1.U(4.W), Array(
81       VLmul.m2 -> 2.U,
82       VLmul.m4 -> 4.U,
83       VLmul.m8 -> 8.U,
84     ))
85    val foldLastVlmul = MuxLookup(vsew, "b000".U, Array(
86      VSew.e16 -> VLmul.mf8,
87      VSew.e32 -> VLmul.mf4,
88      VSew.e64 -> VLmul.mf2,
89    ))
90    // lmul < 1, foldTime = vlmul - foldFastVlmul
91    // lmul >= 1, foldTime = 0.U - foldFastVlmul
92    val foldTime = Mux(vlmul(2), vlmul, 0.U) - foldLastVlmul
93    addTime + foldTime
94  }
95  val numOfUopVFREDOSUM = {
96    val uvlMax = MuxLookup(vsew, 0.U, Array(
97      VSew.e16 -> 8.U,
98      VSew.e32 -> 4.U,
99      VSew.e64 -> 2.U,
100    ))
101    val vlMax = Wire(UInt(7.W))
102    vlMax := Mux(vlmul(2), uvlMax >> (-vlmul)(1,0), uvlMax << vlmul(1,0)).asUInt
103    vlMax
104  }
105
106  //number of uop
107  val numOfUop = MuxLookup(typeOfSplit, 1.U(log2Up(MaxUopSize + 1).W), Array(
108    UopSplitType.VEC_0XV -> 2.U,
109    UopSplitType.VEC_VVV -> lmul,
110    UopSplitType.VEC_VFV -> lmul,
111    UopSplitType.VEC_EXT2 -> lmul,
112    UopSplitType.VEC_EXT4 -> lmul,
113    UopSplitType.VEC_EXT8 -> lmul,
114    UopSplitType.VEC_VVM -> lmul,
115    UopSplitType.VEC_VFM -> lmul,
116    UopSplitType.VEC_VFRED -> numOfUopVFRED,
117    UopSplitType.VEC_VFREDOSUM -> numOfUopVFREDOSUM,
118    UopSplitType.VEC_VXM -> (lmul +& 1.U),
119    UopSplitType.VEC_VXV -> (lmul +& 1.U),
120    UopSplitType.VEC_VIV -> (lmul +& 1.U),
121    UopSplitType.VEC_VFW -> Cat(lmul, 0.U(1.W)), // lmul <= 4
122    UopSplitType.VEC_WFW -> Cat(lmul, 0.U(1.W)), // lmul <= 4
123    UopSplitType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4
124    UopSplitType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4
125    UopSplitType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4
126    UopSplitType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4
127    UopSplitType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4
128    UopSplitType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4
129    UopSplitType.VEC_SLIDE1UP -> (lmul +& 1.U),
130    UopSplitType.VEC_FSLIDE1UP -> lmul,
131    UopSplitType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)),
132    UopSplitType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) - 1.U),
133    UopSplitType.VEC_VRED -> lmul,
134    UopSplitType.VEC_SLIDEUP -> (numOfUopVslide + 1.U),
135    UopSplitType.VEC_ISLIDEUP -> numOfUopVslide,
136    UopSplitType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U),
137    UopSplitType.VEC_ISLIDEDOWN -> numOfUopVslide,
138    UopSplitType.VEC_M0X -> (lmul +& 1.U),
139    UopSplitType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) - 1.U),
140    UopSplitType.VEC_M0X_VFIRST -> 2.U,
141    UopSplitType.VEC_VWW -> Cat(lmul, 0.U(1.W)),
142    UopSplitType.VEC_RGATHER -> numOfUopVrgather,
143    UopSplitType.VEC_RGATHER_VX -> (numOfUopVrgather +& 1.U),
144    UopSplitType.VEC_RGATHEREI16 -> numOfUopVrgatherei16,
145    UopSplitType.VEC_US_LD -> (emul +& 1.U),
146    UopSplitType.VEC_MVNR -> (vmvn +& 1.U),
147  ))
148
149  isComplex := (numOfUop > 1.U) || (typeOfSplit === UopSplitType.DIR)
150  io.out.uopInfo.numOfUop := numOfUop
151  io.out.uopInfo.lmul := lmul
152
153}
154
155class UopInfoGenIO(implicit p: Parameters) extends XSBundle {
156  val in = new Bundle {
157    val preInfo = Input(new PreInfo)
158  }
159  val out = new Bundle {
160    val isComplex = Output(Bool())
161    val uopInfo = Output(new UopInfo)
162  }
163}
164
165class PreInfo(implicit p: Parameters) extends XSBundle {
166  val typeOfSplit = UopSplitType()
167  val vsew = VSew()          //2 bit
168  val vlmul = VLmul()
169  val vwidth = UInt(3.W)     //eew
170  val vmvn = UInt(3.W)       // vmvnr
171}
172
173class UopInfo(implicit p: Parameters) extends XSBundle {
174  val numOfUop = UInt(log2Up(MaxUopSize + 1).W)
175  val lmul = UInt(4.W)
176}