1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.fu.vector.Bundles.{VType, VLmul, VSew} 33import yunsuan.VpermType 34 35class UopInfoGen (implicit p: Parameters) extends XSModule { 36 val io = IO(new UopInfoGenIO) 37 38 val typeOfSplit = io.in.preInfo.typeOfSplit 39 val vsew = Cat(0.U(1.W), io.in.preInfo.vsew) 40 val veew = Cat(0.U(1.W), io.in.preInfo.vwidth(1, 0)) 41 val vlmul = io.in.preInfo.vlmul 42 val isComplex = io.out.isComplex 43 44 val lmul = MuxLookup(vlmul, 1.U(4.W), Array( 45 "b001".U -> 2.U, 46 "b010".U -> 4.U, 47 "b011".U -> 8.U 48 )) 49 50 val vemul: UInt = veew.asUInt + 1.U + vlmul.asUInt + ~vsew.asUInt 51 52 val emul = MuxLookup(vemul, 1.U(4.W), Array( 53 "b001".U -> 2.U, 54 "b010".U -> 4.U, 55 "b011".U -> 8.U 56 )) //TODO : eew and emul illegal exception need to be handled 57 58 val numOfUopVslide = MuxLookup(vlmul, 1.U(log2Up(MaxUopSize + 1).W), Array( 59 "b001".U -> 3.U, 60 "b010".U -> 10.U, 61 "b011".U -> 36.U 62 )) 63 val numOfUopVrgather = MuxLookup(vlmul, 1.U(log2Up(MaxUopSize + 1).W), Array( 64 "b001".U -> 4.U, 65 "b010".U -> 16.U, 66 "b011".U -> 64.U 67 )) 68 val numOfUopVrgatherei16 = Mux((!vsew.orR) && (vlmul =/= "b011".U), 69 Cat(numOfUopVrgather, 0.U(1.W)), 70 numOfUopVrgather 71 ) 72 val numOfUopVcompress = MuxLookup(vlmul, 1.U(4.W), Array( 73 "b001".U -> 4.U, 74 "b010".U -> 13.U, 75 "b011".U -> 43.U 76 )) 77 78 //number of uop 79 val numOfUop = MuxLookup(typeOfSplit, 1.U(log2Up(MaxUopSize + 1).W), Array( 80 UopSplitType.VEC_0XV -> 2.U, 81 UopSplitType.VEC_VVV -> lmul, 82 UopSplitType.VEC_EXT2 -> lmul, 83 UopSplitType.VEC_EXT4 -> lmul, 84 UopSplitType.VEC_EXT8 -> lmul, 85 UopSplitType.VEC_VVM -> lmul, 86 UopSplitType.VEC_VXM -> (lmul +& 1.U), 87 UopSplitType.VEC_VXV -> (lmul +& 1.U), 88 UopSplitType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 89 UopSplitType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 90 UopSplitType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 91 UopSplitType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 92 UopSplitType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 93 UopSplitType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 94 UopSplitType.VEC_SLIDE1UP -> (lmul +& 1.U), 95 UopSplitType.VEC_FSLIDE1UP -> lmul, 96 UopSplitType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 97 UopSplitType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) - 1.U), 98 UopSplitType.VEC_VRED -> lmul, 99 UopSplitType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 100 UopSplitType.VEC_ISLIDEUP -> numOfUopVslide, 101 UopSplitType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 102 UopSplitType.VEC_ISLIDEDOWN -> numOfUopVslide, 103 UopSplitType.VEC_M0X -> (lmul +& 1.U), 104 UopSplitType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) - 1.U), 105 UopSplitType.VEC_M0X_VFIRST -> 2.U, 106 UopSplitType.VEC_VWW -> Cat(lmul, 0.U(1.W)), 107 UopSplitType.VEC_RGATHER -> numOfUopVrgather, 108 UopSplitType.VEC_RGATHER_VX -> (numOfUopVrgather +& 1.U), 109 UopSplitType.VEC_RGATHEREI16 -> numOfUopVrgatherei16, 110 UopSplitType.VEC_US_LD -> (emul +& 1.U), 111 )) 112 113 isComplex := (numOfUop > 1.U) || (typeOfSplit === UopSplitType.DIR) 114 io.out.uopInfo.numOfUop := numOfUop 115 io.out.uopInfo.lmul := lmul 116 117} 118 119class UopInfoGenIO(implicit p: Parameters) extends XSBundle { 120 val in = new Bundle { 121 val preInfo = Input(new PreInfo) 122 } 123 val out = new Bundle { 124 val isComplex = Output(Bool()) 125 val uopInfo = Output(new UopInfo) 126 } 127} 128 129class PreInfo(implicit p: Parameters) extends XSBundle { 130 val typeOfSplit = UopSplitType() 131 val vsew = VSew() //2 bit 132 val vlmul = VLmul() 133 val vwidth = UInt(3.W) //eew 134} 135 136class UopInfo(implicit p: Parameters) extends XSBundle { 137 val numOfUop = UInt(log2Up(MaxUopSize + 1).W) 138 val lmul = UInt(4.W) 139}