1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.fu.vector.Bundles.{VType, VLmul, VSew} 33import yunsuan.VpermType 34 35class UopInfoGen (implicit p: Parameters) extends XSModule { 36 val io = IO(new UopInfoGenIO) 37 38 val typeOfSplit = io.in.preInfo.typeOfSplit 39 val vsew = Cat(0.U(1.W), io.in.preInfo.vsew) 40 val veew = Cat(0.U(1.W), io.in.preInfo.vwidth(1, 0)) 41 val vlmul = io.in.preInfo.vlmul 42 val isComplex = io.out.isComplex 43 44 val lmul = MuxLookup(vlmul, 1.U(4.W), Array( 45 "b001".U -> 2.U, 46 "b010".U -> 4.U, 47 "b011".U -> 8.U 48 )) 49 50 val vemul: UInt = veew.asUInt + 1.U + vlmul.asUInt + ~vsew.asUInt 51 52 val emul = MuxLookup(vemul, 1.U(4.W), Array( 53 "b001".U -> 2.U, 54 "b010".U -> 4.U, 55 "b011".U -> 8.U 56 )) //TODO : eew and emul illegal exception need to be handled 57 58 val numOfUopVslide = MuxLookup(vlmul, 1.U(log2Up(MaxUopSize + 1).W), Array( 59 "b001".U -> 3.U, 60 "b010".U -> 10.U, 61 "b011".U -> 36.U 62 )) 63 val numOfUopVrgather = MuxLookup(vlmul, 1.U(log2Up(MaxUopSize + 1).W), Array( 64 "b001".U -> 4.U, 65 "b010".U -> 16.U, 66 "b011".U -> 64.U 67 )) 68 val numOfUopVrgatherei16 = Mux((!vsew.orR) && (vlmul =/= "b011".U), 69 Cat(numOfUopVrgather, 0.U(1.W)), 70 numOfUopVrgather 71 ) 72 val numOfUopVcompress = MuxLookup(vlmul, 1.U(4.W), Array( 73 "b001".U -> 4.U, 74 "b010".U -> 13.U, 75 "b011".U -> 43.U 76 )) 77 val numOfUopVFRED = { 78 // addTime include add frs1 79 val addTime = MuxLookup(vlmul, 1.U(4.W), Array( 80 VLmul.m2 -> 2.U, 81 VLmul.m4 -> 4.U, 82 VLmul.m8 -> 8.U, 83 )) 84 val foldLastVlmul = MuxLookup(vsew, "b000".U, Array( 85 VSew.e16 -> VLmul.mf8, 86 VSew.e32 -> VLmul.mf4, 87 VSew.e64 -> VLmul.mf2, 88 )) 89 // lmul < 1, foldTime = vlmul - foldFastVlmul 90 // lmul >= 1, foldTime = 0.U - foldFastVlmul 91 val foldTime = Mux(vlmul(2), vlmul, 0.U) - foldLastVlmul 92 addTime + foldTime 93 } 94 val numOfUopVFREDOSUM = { 95 val uvlMax = MuxLookup(vsew, 0.U, Array( 96 VSew.e16 -> 8.U, 97 VSew.e32 -> 4.U, 98 VSew.e64 -> 2.U, 99 )) 100 val vlMax = Wire(UInt(7.W)) 101 vlMax := Mux(vlmul(2), uvlMax >> (-vlmul)(1,0), uvlMax << vlmul(1,0)).asUInt 102 vlMax 103 } 104 105 //number of uop 106 val numOfUop = MuxLookup(typeOfSplit, 1.U(log2Up(MaxUopSize + 1).W), Array( 107 UopSplitType.VEC_0XV -> 2.U, 108 UopSplitType.VEC_VVV -> lmul, 109 UopSplitType.VEC_VFV -> lmul, 110 UopSplitType.VEC_EXT2 -> lmul, 111 UopSplitType.VEC_EXT4 -> lmul, 112 UopSplitType.VEC_EXT8 -> lmul, 113 UopSplitType.VEC_VVM -> lmul, 114 UopSplitType.VEC_VFM -> lmul, 115 UopSplitType.VEC_VFRED -> numOfUopVFRED, 116 UopSplitType.VEC_VFREDOSUM -> numOfUopVFREDOSUM, 117 UopSplitType.VEC_VXM -> (lmul +& 1.U), 118 UopSplitType.VEC_VXV -> (lmul +& 1.U), 119 UopSplitType.VEC_VFW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 120 UopSplitType.VEC_WFW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 121 UopSplitType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 122 UopSplitType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 123 UopSplitType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 124 UopSplitType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 125 UopSplitType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 126 UopSplitType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 127 UopSplitType.VEC_SLIDE1UP -> (lmul +& 1.U), 128 UopSplitType.VEC_FSLIDE1UP -> lmul, 129 UopSplitType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 130 UopSplitType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) - 1.U), 131 UopSplitType.VEC_VRED -> lmul, 132 UopSplitType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 133 UopSplitType.VEC_ISLIDEUP -> numOfUopVslide, 134 UopSplitType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 135 UopSplitType.VEC_ISLIDEDOWN -> numOfUopVslide, 136 UopSplitType.VEC_M0X -> (lmul +& 1.U), 137 UopSplitType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) - 1.U), 138 UopSplitType.VEC_M0X_VFIRST -> 2.U, 139 UopSplitType.VEC_VWW -> Cat(lmul, 0.U(1.W)), 140 UopSplitType.VEC_RGATHER -> numOfUopVrgather, 141 UopSplitType.VEC_RGATHER_VX -> (numOfUopVrgather +& 1.U), 142 UopSplitType.VEC_RGATHEREI16 -> numOfUopVrgatherei16, 143 UopSplitType.VEC_US_LD -> (emul +& 1.U), 144 )) 145 146 isComplex := (numOfUop > 1.U) || (typeOfSplit === UopSplitType.DIR) 147 io.out.uopInfo.numOfUop := numOfUop 148 io.out.uopInfo.lmul := lmul 149 150} 151 152class UopInfoGenIO(implicit p: Parameters) extends XSBundle { 153 val in = new Bundle { 154 val preInfo = Input(new PreInfo) 155 } 156 val out = new Bundle { 157 val isComplex = Output(Bool()) 158 val uopInfo = Output(new UopInfo) 159 } 160} 161 162class PreInfo(implicit p: Parameters) extends XSBundle { 163 val typeOfSplit = UopSplitType() 164 val vsew = VSew() //2 bit 165 val vlmul = VLmul() 166 val vwidth = UInt(3.W) //eew 167} 168 169class UopInfo(implicit p: Parameters) extends XSBundle { 170 val numOfUop = UInt(log2Up(MaxUopSize + 1).W) 171 val lmul = UInt(4.W) 172}