1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.fu.vector.Bundles.{VType, VLmul, VSew} 33import yunsuan.VpermType 34import chisel3.util.experimental.decode.{QMCMinimizer, TruthTable, decoder} 35 36class strdiedLSNumOfUopTable() extends Module { 37 val src = IO(Input(UInt(5.W))) 38 val out = IO(Output(UInt(4.W))) 39 // strided load/store 40 var combVemulNf : Seq[(Int, Int, Int)] = Seq() 41 for (emul <- 0 until 4) { 42 for (nf <- 0 until 8) { 43 if ((1 << emul) * (nf + 1) <= 8) { 44 combVemulNf :+= (emul, nf, (1 << emul) * (nf + 1)) 45 } else { 46 combVemulNf :+= (emul, nf, 0) 47 } 48 } 49 } 50 out := decoder(QMCMinimizer, src, TruthTable(combVemulNf.map { 51 case (emul, nf, uopNum) => (BitPat((emul << 3 | nf).U(5.W)), BitPat(uopNum.U(4.W))) 52 }, BitPat.N(4))) 53} 54 55class indexedLSNumOfUopTable() extends Module { 56 val src = IO(Input(UInt(7.W))) 57 val out = IO(Output(UInt(7.W))) 58 // strided load/store 59 var combVemulNf : Seq[(Int, Int, Int, Int)] = Seq() 60 for (emul <- 0 until 4) { 61 for (lmul <- 0 until 4) { 62 var max_mul = if (lmul > emul) lmul else emul 63 for (nf <- 0 until 8) { 64 if ((1 << lmul) * (nf + 1) <= 8) { // indexed load/store must ensure that the lmul * nf is less or equal to 8 65 combVemulNf :+= (emul, lmul, nf, (1 << max_mul) * (nf + 1)) 66 } else { 67 combVemulNf :+= (emul, lmul, nf, 0) 68 } 69 } 70 } 71 } 72 out := decoder(QMCMinimizer, src, TruthTable(combVemulNf.map { 73 case (emul, lmul, nf, uopNum) => (BitPat((emul << 5 | lmul << 3 | nf).U(7.W)), BitPat(uopNum.U(7.W))) 74 }, BitPat.N(7))) 75} 76 77class UopInfoGen (implicit p: Parameters) extends XSModule { 78 val io = IO(new UopInfoGenIO) 79 80 val stridedLSTable = Module(new strdiedLSNumOfUopTable) // decoder for strided load/store 81 val indexedLSTable = Module(new indexedLSNumOfUopTable) // decoder for indexed load/store 82 83 val typeOfSplit = io.in.preInfo.typeOfSplit 84 val vsew = Cat(0.U(1.W), io.in.preInfo.vsew) 85 val veew = Cat(0.U(1.W), io.in.preInfo.vwidth(1, 0)) 86 val vmvn = io.in.preInfo.vmvn 87 val vlmul = io.in.preInfo.vlmul 88 val nf = io.in.preInfo.nf 89 val isComplex = io.out.isComplex 90 91 val lmul = MuxLookup(vlmul, 1.U(4.W), Array( 92 "b001".U -> 2.U, 93 "b010".U -> 4.U, 94 "b011".U -> 8.U 95 )) 96 val simple_lmul = MuxLookup(vlmul, 0.U(2.W), Array( 97 "b001".U -> 1.U, 98 "b010".U -> 2.U, 99 "b011".U -> 3.U 100 )) 101 102 val vemul: UInt = veew.asUInt + 1.U + vlmul.asUInt + ~vsew.asUInt 103 104 val emul = MuxLookup(vemul, 1.U(4.W), Array( 105 "b001".U -> 2.U, 106 "b010".U -> 4.U, 107 "b011".U -> 8.U 108 )) //TODO : eew and emul illegal exception need to be handled 109 val simple_emul = MuxLookup(vemul, 0.U(2.W), Array( 110 "b001".U -> 1.U, 111 "b010".U -> 2.U, 112 "b011".U -> 3.U 113 )) 114 115 val numOfUopVslide = MuxLookup(vlmul, 1.U(log2Up(MaxUopSize + 1).W), Array( 116 "b001".U -> 3.U, 117 "b010".U -> 10.U, 118 "b011".U -> 36.U 119 )) 120 val numOfUopVrgather = MuxLookup(vlmul, 1.U(log2Up(MaxUopSize + 1).W), Array( 121 "b001".U -> 4.U, 122 "b010".U -> 16.U, 123 "b011".U -> 64.U 124 )) 125 val numOfUopVrgatherei16 = Mux((!vsew.orR) && (vlmul =/= "b011".U), 126 Cat(numOfUopVrgather, 0.U(1.W)), 127 numOfUopVrgather 128 ) 129 val numOfUopVcompress = MuxLookup(vlmul, 1.U(4.W), Array( 130 "b001".U -> 4.U, 131 "b010".U -> 13.U, 132 "b011".U -> 43.U 133 )) 134 val numOfUopVFRED = { 135 // addTime include add frs1 136 val addTime = MuxLookup(vlmul, 1.U(4.W), Array( 137 VLmul.m2 -> 2.U, 138 VLmul.m4 -> 4.U, 139 VLmul.m8 -> 8.U, 140 )) 141 val foldLastVlmul = MuxLookup(vsew, "b000".U, Array( 142 VSew.e16 -> VLmul.mf8, 143 VSew.e32 -> VLmul.mf4, 144 VSew.e64 -> VLmul.mf2, 145 )) 146 // lmul < 1, foldTime = vlmul - foldFastVlmul 147 // lmul >= 1, foldTime = 0.U - foldFastVlmul 148 val foldTime = Mux(vlmul(2), vlmul, 0.U) - foldLastVlmul 149 addTime + foldTime 150 } 151 val numOfUopVFREDOSUM = { 152 val uvlMax = MuxLookup(vsew, 0.U, Array( 153 VSew.e16 -> 8.U, 154 VSew.e32 -> 4.U, 155 VSew.e64 -> 2.U, 156 )) 157 val vlMax = Wire(UInt(7.W)) 158 vlMax := Mux(vlmul(2), uvlMax >> (-vlmul)(1,0), uvlMax << vlmul(1,0)).asUInt 159 vlMax 160 } 161 162 stridedLSTable.src := Cat(simple_emul, nf) 163 val numOfUopVLoadStoreStrided = stridedLSTable.out 164 indexedLSTable.src := Cat(simple_emul, simple_lmul, nf) 165 val numOfUopVLoadStoreIndexed = indexedLSTable.out 166 167 //number of uop 168 val numOfUop = MuxLookup(typeOfSplit, 1.U(log2Up(MaxUopSize + 1).W), Array( 169 UopSplitType.VEC_0XV -> 2.U, 170 UopSplitType.VEC_VVV -> lmul, 171 UopSplitType.VEC_VFV -> lmul, 172 UopSplitType.VEC_EXT2 -> lmul, 173 UopSplitType.VEC_EXT4 -> lmul, 174 UopSplitType.VEC_EXT8 -> lmul, 175 UopSplitType.VEC_VVM -> lmul, 176 UopSplitType.VEC_VFM -> lmul, 177 UopSplitType.VEC_VFRED -> numOfUopVFRED, 178 UopSplitType.VEC_VFREDOSUM -> numOfUopVFREDOSUM, 179 UopSplitType.VEC_VXM -> (lmul +& 1.U), 180 UopSplitType.VEC_VXV -> (lmul +& 1.U), 181 UopSplitType.VEC_VFW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 182 UopSplitType.VEC_WFW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 183 UopSplitType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 184 UopSplitType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 185 UopSplitType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 186 UopSplitType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 187 UopSplitType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 188 UopSplitType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 189 UopSplitType.VEC_SLIDE1UP -> (lmul +& 1.U), 190 UopSplitType.VEC_FSLIDE1UP -> lmul, 191 UopSplitType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 192 UopSplitType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) - 1.U), 193 UopSplitType.VEC_VRED -> lmul, 194 UopSplitType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 195 UopSplitType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 196 UopSplitType.VEC_M0X -> (lmul +& 1.U), 197 UopSplitType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) - 1.U), 198 UopSplitType.VEC_M0X_VFIRST -> 2.U, 199 UopSplitType.VEC_VWW -> Cat(lmul, 0.U(1.W)), 200 UopSplitType.VEC_RGATHER -> numOfUopVrgather, 201 UopSplitType.VEC_RGATHER_VX -> (numOfUopVrgather +& 1.U), 202 UopSplitType.VEC_RGATHEREI16 -> numOfUopVrgatherei16, 203 UopSplitType.VEC_MVNR -> (vmvn +& 1.U), 204 UopSplitType.VEC_US_LDST -> (numOfUopVLoadStoreStrided +& 1.U), // with one move instruction 205 UopSplitType.VEC_S_LDST -> (numOfUopVLoadStoreStrided +& 2.U), // with two move instructions 206 UopSplitType.VEC_I_LDST -> (numOfUopVLoadStoreIndexed +& 1.U), 207 )) 208 209 isComplex := (numOfUop > 1.U) || (typeOfSplit === UopSplitType.DIR) 210 io.out.uopInfo.numOfUop := numOfUop 211 io.out.uopInfo.lmul := lmul 212 213} 214 215class UopInfoGenIO(implicit p: Parameters) extends XSBundle { 216 val in = new Bundle { 217 val preInfo = Input(new PreInfo) 218 } 219 val out = new Bundle { 220 val isComplex = Output(Bool()) 221 val uopInfo = Output(new UopInfo) 222 } 223} 224 225class PreInfo(implicit p: Parameters) extends XSBundle { 226 val typeOfSplit = UopSplitType() 227 val vsew = VSew() //2 bit 228 val vlmul = VLmul() 229 val vwidth = UInt(3.W) //eew 230 val nf = UInt(3.W) 231 val vmvn = UInt(3.W) // vmvnr 232} 233 234class UopInfo(implicit p: Parameters) extends XSBundle { 235 val numOfUop = UInt(log2Up(MaxUopSize + 1).W) 236 val lmul = UInt(4.W) 237}