1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VpermType 31import scala.collection.Seq 32 33trait VectorConstants { 34 val MAX_VLMUL = 8 35 val INT_VCONFIG = 32 36 val FP_TMP_REG_MV = 32 37 val VECTOR_TMP_REG_LMUL = 32 // 32~38 -> 7 38} 39 40class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 41 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 42 val vconfig = Input(new VConfig) 43 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 44 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 45 val readyFromRename = Input(Vec(RenameWidth, Bool())) 46 val deq = new Bundle { 47 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 48 val isVset = Output(Bool()) 49 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 50 val validToRename = Output(Vec(RenameWidth, Bool())) 51 val complexNum = Output(UInt(3.W)) 52 } 53 val csrCtrl = Input(new CustomCSRCtrlIO) 54} 55 56class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 57 val io = IO(new DecodeUnitCompIO) 58 //input bits 59 val ctrl_flow = Wire(new CtrlFlow) 60 ctrl_flow := io.enq.ctrl_flow 61 //output bits 62 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 63 val validToRename = Wire(Vec(RenameWidth, Bool())) 64 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 65 val complexNum = Wire(UInt(3.W)) 66 67 //output of DecodeUnit 68 val cf_ctrl_u = Wire(new CfCtrl) 69 val isVset_u = Wire(Bool()) 70 71 //pre decode 72 val simple = Module(new DecodeUnit) 73 simple.io.enq.ctrl_flow := ctrl_flow 74 simple.io.vconfig := io.vconfig 75 simple.io.csrCtrl := io.csrCtrl 76 cf_ctrl_u := simple.io.deq.cf_ctrl 77 isVset_u := simple.io.deq.isVset 78 79 //Type of uop Div 80 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 81 82 //LMUL 83 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(4.W), Array( 84 "b001".U -> 2.U, 85 "b010".U -> 4.U, 86 "b011".U -> 8.U 87 )) 88 val numOfUopVslide = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(log2Up(maxNumOfUop+1).W), Array( 89 "b001".U -> 3.U, 90 "b010".U -> 10.U, 91 "b011".U -> 36.U 92 )) 93 //number of uop 94 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxNumOfUop+1).W), Array( 95 UopDivType.VEC_0XV -> 2.U, 96 UopDivType.DIR -> 2.U, 97 UopDivType.VEC_VVV -> lmul, 98 UopDivType.VEC_EXT2 -> lmul, 99 UopDivType.VEC_EXT4 -> lmul, 100 UopDivType.VEC_EXT8 -> lmul, 101 UopDivType.VEC_VVM -> lmul, 102 UopDivType.VEC_VXM -> (lmul +& 1.U), 103 UopDivType.VEC_VXV -> (lmul +& 1.U), 104 UopDivType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 105 UopDivType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 106 UopDivType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 107 UopDivType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 108 UopDivType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 109 UopDivType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 110 UopDivType.VEC_SLIDE1UP -> (lmul +& 1.U), 111 UopDivType.VEC_FSLIDE1UP -> lmul, 112 UopDivType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 113 UopDivType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 114 UopDivType.VEC_VRED -> lmul, 115 UopDivType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 116 UopDivType.VEC_ISLIDEUP -> numOfUopVslide, 117 UopDivType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 118 UopDivType.VEC_ISLIDEDOWN -> numOfUopVslide, 119 )) 120 121 val src1 = Cat(0.U(1.W), ctrl_flow.instr(19, 15)) 122 val src2 = Cat(0.U(1.W), ctrl_flow.instr(24, 20)) 123 val dest = Cat(0.U(1.W), ctrl_flow.instr(11, 7 )) 124 125 //uop div up to maxNumOfUop 126 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 127 csBundle.map { case dst => 128 dst := cf_ctrl_u 129 dst.ctrl.firstUop := false.B 130 dst.ctrl.lastUop := false.B 131 } 132 133 csBundle(0).ctrl.firstUop := true.B 134 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 135 136 switch(typeOfDiv) { 137 is(UopDivType.DIR) { 138 when(isVset_u) { 139 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR || ALUOpType.isVsetvl(cf_ctrl_u.ctrl.fuOpType) 140 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 141 csBundle(1).ctrl.ldest := INT_VCONFIG.U 142 csBundle(1).ctrl.flushPipe := false.B 143 } 144 } 145 is(UopDivType.VEC_VVV) { 146 for (i <- 0 until MAX_VLMUL) { 147 csBundle(i).ctrl.lsrc(0) := src1 + i.U 148 csBundle(i).ctrl.lsrc(1) := src2 + i.U 149 csBundle(i).ctrl.lsrc(2) := dest + i.U 150 csBundle(i).ctrl.ldest := dest + i.U 151 csBundle(i).ctrl.uopIdx := i.U 152 } 153 } 154 is(UopDivType.VEC_EXT2) { 155 for (i <- 0 until MAX_VLMUL / 2) { 156 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 157 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 158 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 159 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 160 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 161 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 162 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 163 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 164 } 165 } 166 is(UopDivType.VEC_EXT4) { 167 for (i <- 0 until MAX_VLMUL / 4) { 168 csBundle(4 * i).ctrl.lsrc(1) := src2 + i.U 169 csBundle(4 * i).ctrl.lsrc(2) := dest + (4 * i).U 170 csBundle(4 * i).ctrl.ldest := dest + (4 * i).U 171 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 172 csBundle(4 * i + 1).ctrl.lsrc(1) := src2 + i.U 173 csBundle(4 * i + 1).ctrl.lsrc(2) := dest + (4 * i + 1).U 174 csBundle(4 * i + 1).ctrl.ldest := dest + (4 * i + 1).U 175 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 176 csBundle(4 * i + 2).ctrl.lsrc(1) := src2 + i.U 177 csBundle(4 * i + 2).ctrl.lsrc(2) := dest + (4 * i + 2).U 178 csBundle(4 * i + 2).ctrl.ldest := dest + (4 * i + 2).U 179 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 180 csBundle(4 * i + 3).ctrl.lsrc(1) := src2 + i.U 181 csBundle(4 * i + 3).ctrl.lsrc(2) := dest + (4 * i + 3).U 182 csBundle(4 * i + 3).ctrl.ldest := dest + (4 * i + 3).U 183 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 184 } 185 } 186 is(UopDivType.VEC_EXT8) { 187 for (i <- 0 until MAX_VLMUL) { 188 csBundle(i).ctrl.lsrc(1) := src2 189 csBundle(i).ctrl.lsrc(2) := dest + i.U 190 csBundle(i).ctrl.ldest := dest + i.U 191 csBundle(i).ctrl.uopIdx := i.U 192 } 193 } 194 is(UopDivType.VEC_0XV) { 195 /* 196 FMV.D.X 197 */ 198 csBundle(0).ctrl.srcType(0) := SrcType.reg 199 csBundle(0).ctrl.srcType(1) := SrcType.imm 200 csBundle(0).ctrl.lsrc(1) := 0.U 201 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 202 csBundle(0).ctrl.fuType := FuType.i2f 203 csBundle(0).ctrl.rfWen := false.B 204 csBundle(0).ctrl.fpWen := true.B 205 csBundle(0).ctrl.vecWen := false.B 206 csBundle(0).ctrl.fpu.isAddSub := false.B 207 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 208 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 209 csBundle(0).ctrl.fpu.fromInt := true.B 210 csBundle(0).ctrl.fpu.wflags := false.B 211 csBundle(0).ctrl.fpu.fpWen := true.B 212 csBundle(0).ctrl.fpu.div := false.B 213 csBundle(0).ctrl.fpu.sqrt := false.B 214 csBundle(0).ctrl.fpu.fcvt := false.B 215 /* 216 vfmv.s.f 217 */ 218 csBundle(1).ctrl.srcType(0) := SrcType.fp 219 csBundle(1).ctrl.srcType(1) := SrcType.vp 220 csBundle(1).ctrl.srcType(2) := SrcType.vp 221 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 222 csBundle(1).ctrl.lsrc(1) := 0.U 223 csBundle(1).ctrl.lsrc(2) := dest 224 csBundle(1).ctrl.ldest := dest 225 csBundle(1).ctrl.fuType := FuType.vppu 226 csBundle(1).ctrl.fuOpType := VpermType.vfmv_s_f 227 csBundle(1).ctrl.rfWen := false.B 228 csBundle(1).ctrl.fpWen := false.B 229 csBundle(1).ctrl.vecWen := true.B 230 } 231 is(UopDivType.VEC_VXV) { 232 /* 233 FMV.D.X 234 */ 235 csBundle(0).ctrl.srcType(0) := SrcType.reg 236 csBundle(0).ctrl.srcType(1) := SrcType.imm 237 csBundle(0).ctrl.lsrc(1) := 0.U 238 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 239 csBundle(0).ctrl.fuType := FuType.i2f 240 csBundle(0).ctrl.rfWen := false.B 241 csBundle(0).ctrl.fpWen := true.B 242 csBundle(0).ctrl.vecWen := false.B 243 csBundle(0).ctrl.fpu.isAddSub := false.B 244 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 245 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 246 csBundle(0).ctrl.fpu.fromInt := true.B 247 csBundle(0).ctrl.fpu.wflags := false.B 248 csBundle(0).ctrl.fpu.fpWen := true.B 249 csBundle(0).ctrl.fpu.div := false.B 250 csBundle(0).ctrl.fpu.sqrt := false.B 251 csBundle(0).ctrl.fpu.fcvt := false.B 252 /* 253 LMUL 254 */ 255 for (i <- 0 until MAX_VLMUL) { 256 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 257 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 258 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 259 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 260 csBundle(i + 1).ctrl.ldest := dest + i.U 261 csBundle(i + 1).ctrl.uopIdx := i.U 262 } 263 } 264 is(UopDivType.VEC_VVW) { 265 for (i <- 0 until MAX_VLMUL / 2) { 266 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 267 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 268 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 269 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 270 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 271 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 272 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 273 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 274 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 275 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 276 } 277 } 278 is(UopDivType.VEC_WVW) { 279 for (i <- 0 until MAX_VLMUL / 2) { 280 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 281 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 282 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 283 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 284 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 285 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 286 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 287 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 288 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 289 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 290 } 291 } 292 is(UopDivType.VEC_VXW) { 293 /* 294 FMV.D.X 295 */ 296 csBundle(0).ctrl.srcType(0) := SrcType.reg 297 csBundle(0).ctrl.srcType(1) := SrcType.imm 298 csBundle(0).ctrl.lsrc(1) := 0.U 299 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 300 csBundle(0).ctrl.fuType := FuType.i2f 301 csBundle(0).ctrl.rfWen := false.B 302 csBundle(0).ctrl.fpWen := true.B 303 csBundle(0).ctrl.vecWen := false.B 304 csBundle(0).ctrl.fpu.isAddSub := false.B 305 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 306 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 307 csBundle(0).ctrl.fpu.fromInt := true.B 308 csBundle(0).ctrl.fpu.wflags := false.B 309 csBundle(0).ctrl.fpu.fpWen := true.B 310 csBundle(0).ctrl.fpu.div := false.B 311 csBundle(0).ctrl.fpu.sqrt := false.B 312 csBundle(0).ctrl.fpu.fcvt := false.B 313 314 for (i <- 0 until MAX_VLMUL / 2) { 315 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 316 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 317 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 318 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 319 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 320 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 321 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 322 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 323 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U 324 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 325 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 326 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 327 } 328 } 329 is(UopDivType.VEC_WXW) { 330 /* 331 FMV.D.X 332 */ 333 csBundle(0).ctrl.srcType(0) := SrcType.reg 334 csBundle(0).ctrl.srcType(1) := SrcType.imm 335 csBundle(0).ctrl.lsrc(1) := 0.U 336 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 337 csBundle(0).ctrl.fuType := FuType.i2f 338 csBundle(0).ctrl.rfWen := false.B 339 csBundle(0).ctrl.fpWen := true.B 340 csBundle(0).ctrl.vecWen := false.B 341 csBundle(0).ctrl.fpu.isAddSub := false.B 342 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 343 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 344 csBundle(0).ctrl.fpu.fromInt := true.B 345 csBundle(0).ctrl.fpu.wflags := false.B 346 csBundle(0).ctrl.fpu.fpWen := true.B 347 csBundle(0).ctrl.fpu.div := false.B 348 csBundle(0).ctrl.fpu.sqrt := false.B 349 csBundle(0).ctrl.fpu.fcvt := false.B 350 351 for (i <- 0 until MAX_VLMUL / 2) { 352 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 353 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 354 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 355 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 356 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 357 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 358 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 359 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 360 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 361 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 362 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 363 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 364 } 365 } 366 is(UopDivType.VEC_WVV) { 367 for (i <- 0 until MAX_VLMUL / 2) { 368 369 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 370 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 371 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 372 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 373 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 374 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 375 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 376 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 377 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 378 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 379 } 380 } 381 is(UopDivType.VEC_WXV) { 382 /* 383 FMV.D.X 384 */ 385 csBundle(0).ctrl.srcType(0) := SrcType.reg 386 csBundle(0).ctrl.srcType(1) := SrcType.imm 387 csBundle(0).ctrl.lsrc(1) := 0.U 388 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 389 csBundle(0).ctrl.fuType := FuType.i2f 390 csBundle(0).ctrl.rfWen := false.B 391 csBundle(0).ctrl.fpWen := true.B 392 csBundle(0).ctrl.vecWen := false.B 393 csBundle(0).ctrl.fpu.isAddSub := false.B 394 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 395 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 396 csBundle(0).ctrl.fpu.fromInt := true.B 397 csBundle(0).ctrl.fpu.wflags := false.B 398 csBundle(0).ctrl.fpu.fpWen := true.B 399 csBundle(0).ctrl.fpu.div := false.B 400 csBundle(0).ctrl.fpu.sqrt := false.B 401 csBundle(0).ctrl.fpu.fcvt := false.B 402 403 for (i <- 0 until MAX_VLMUL / 2) { 404 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 405 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 406 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 407 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 408 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 409 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 410 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 411 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 412 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 413 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 414 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 415 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 416 } 417 } 418 is(UopDivType.VEC_VVM) { 419 csBundle(0).ctrl.lsrc(2) := dest 420 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 421 csBundle(0).ctrl.uopIdx := 0.U 422 for(i <- 1 until MAX_VLMUL) { 423 csBundle(i).ctrl.lsrc(0) := src1 + i.U 424 csBundle(i).ctrl.lsrc(1) := src2 + i.U 425 csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 426 csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 427 csBundle(i).ctrl.uopIdx := i.U 428 } 429 csBundle(numOfUop - 1.U).ctrl.ldest := dest 430 } 431 is(UopDivType.VEC_VXM) { 432 /* 433 FMV.D.X 434 */ 435 csBundle(0).ctrl.srcType(0) := SrcType.reg 436 csBundle(0).ctrl.srcType(1) := SrcType.imm 437 csBundle(0).ctrl.lsrc(1) := 0.U 438 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 439 csBundle(0).ctrl.fuType := FuType.i2f 440 csBundle(0).ctrl.rfWen := false.B 441 csBundle(0).ctrl.fpWen := true.B 442 csBundle(0).ctrl.vecWen := false.B 443 csBundle(0).ctrl.fpu.isAddSub := false.B 444 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 445 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 446 csBundle(0).ctrl.fpu.fromInt := true.B 447 csBundle(0).ctrl.fpu.wflags := false.B 448 csBundle(0).ctrl.fpu.fpWen := true.B 449 csBundle(0).ctrl.fpu.div := false.B 450 csBundle(0).ctrl.fpu.sqrt := false.B 451 csBundle(0).ctrl.fpu.fcvt := false.B 452 //LMUL 453 csBundle(1).ctrl.srcType(0) := SrcType.fp 454 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 455 csBundle(1).ctrl.lsrc(2) := dest 456 csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 457 csBundle(1).ctrl.uopIdx := 0.U 458 for (i <- 1 until MAX_VLMUL) { 459 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 460 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 461 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 462 csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 463 csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 464 csBundle(i + 1).ctrl.uopIdx := i.U 465 } 466 csBundle(numOfUop - 1.U).ctrl.ldest := dest 467 } 468 is(UopDivType.VEC_SLIDE1UP) { 469 /* 470 FMV.D.X 471 */ 472 csBundle(0).ctrl.srcType(0) := SrcType.reg 473 csBundle(0).ctrl.srcType(1) := SrcType.imm 474 csBundle(0).ctrl.lsrc(1) := 0.U 475 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 476 csBundle(0).ctrl.fuType := FuType.i2f 477 csBundle(0).ctrl.rfWen := false.B 478 csBundle(0).ctrl.fpWen := true.B 479 csBundle(0).ctrl.vecWen := false.B 480 csBundle(0).ctrl.fpu.isAddSub := false.B 481 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 482 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 483 csBundle(0).ctrl.fpu.fromInt := true.B 484 csBundle(0).ctrl.fpu.wflags := false.B 485 csBundle(0).ctrl.fpu.fpWen := true.B 486 csBundle(0).ctrl.fpu.div := false.B 487 csBundle(0).ctrl.fpu.sqrt := false.B 488 csBundle(0).ctrl.fpu.fcvt := false.B 489 //LMUL 490 csBundle(1).ctrl.srcType(0) := SrcType.fp 491 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 492 csBundle(1).ctrl.lsrc(2) := dest 493 csBundle(1).ctrl.ldest := dest 494 csBundle(1).ctrl.uopIdx := 0.U 495 for (i <- 1 until MAX_VLMUL) { 496 csBundle(i + 1).ctrl.srcType(0) := SrcType.vp 497 csBundle(i + 1).ctrl.lsrc(0) := src2 + (i - 1).U 498 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 499 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 500 csBundle(i + 1).ctrl.ldest := dest + i.U 501 csBundle(i + 1).ctrl.uopIdx := i.U 502 } 503 } 504 is(UopDivType.VEC_FSLIDE1UP) { 505 //LMUL 506 csBundle(0).ctrl.srcType(0) := SrcType.fp 507 csBundle(0).ctrl.lsrc(0) := src1 508 csBundle(0).ctrl.lsrc(1) := src2 509 csBundle(0).ctrl.lsrc(2) := dest 510 csBundle(0).ctrl.ldest := dest 511 csBundle(0).ctrl.uopIdx := 0.U 512 for (i <- 1 until MAX_VLMUL) { 513 csBundle(i).ctrl.srcType(0) := SrcType.vp 514 csBundle(i).ctrl.lsrc(0) := src2 + (i - 1).U 515 csBundle(i).ctrl.lsrc(1) := src2 + i.U 516 csBundle(i).ctrl.lsrc(2) := dest + i.U 517 csBundle(i).ctrl.ldest := dest + i.U 518 csBundle(i).ctrl.uopIdx := i.U 519 } 520 } 521 is(UopDivType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 522 /* 523 FMV.D.X 524 */ 525 csBundle(0).ctrl.srcType(0) := SrcType.reg 526 csBundle(0).ctrl.srcType(1) := SrcType.imm 527 csBundle(0).ctrl.lsrc(1) := 0.U 528 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 529 csBundle(0).ctrl.fuType := FuType.i2f 530 csBundle(0).ctrl.rfWen := false.B 531 csBundle(0).ctrl.fpWen := true.B 532 csBundle(0).ctrl.vecWen := false.B 533 csBundle(0).ctrl.fpu.isAddSub := false.B 534 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 535 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 536 csBundle(0).ctrl.fpu.fromInt := true.B 537 csBundle(0).ctrl.fpu.wflags := false.B 538 csBundle(0).ctrl.fpu.fpWen := true.B 539 csBundle(0).ctrl.fpu.div := false.B 540 csBundle(0).ctrl.fpu.sqrt := false.B 541 csBundle(0).ctrl.fpu.fcvt := false.B 542 //LMUL 543 for (i <- 0 until MAX_VLMUL) { 544 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp 545 csBundle(2 * i + 1).ctrl.srcType(1) := SrcType.vp 546 csBundle(2 * i + 1).ctrl.lsrc(0) := src2 + (i+1).U 547 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 548 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 549 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 550 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 551 if (2 * i + 2 < MAX_VLMUL * 2 ){ 552 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 553 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 554 // csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U // DontCare 555 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 556 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 557 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 558 } 559 } 560 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 561 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := FP_TMP_REG_MV.U 562 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 563 } 564 is(UopDivType.VEC_FSLIDE1DOWN) { 565 //LMUL 566 for (i <- 0 until MAX_VLMUL) { 567 csBundle(2 * i).ctrl.srcType(0) := SrcType.vp 568 csBundle(2 * i).ctrl.srcType(1) := SrcType.vp 569 csBundle(2 * i).ctrl.lsrc(0) := src2 + (i+1).U 570 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 571 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 572 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 573 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 574 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 575 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 576 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 577 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 578 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 579 } 580 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 581 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1 582 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 583 } 584 is(UopDivType.VEC_VRED) { 585 when(simple.io.vconfig.vtype.vlmul === "b001".U){ 586 csBundle(0).ctrl.srcType(2) := SrcType.DC 587 csBundle(0).ctrl.lsrc(0) := src2 + 1.U 588 csBundle(0).ctrl.lsrc(1) := src2 589 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 590 csBundle(0).ctrl.uopIdx := 0.U 591 } 592 when(simple.io.vconfig.vtype.vlmul === "b010".U) { 593 csBundle(0).ctrl.srcType(2) := SrcType.DC 594 csBundle(0).ctrl.lsrc(0) := src2 + 1.U 595 csBundle(0).ctrl.lsrc(1) := src2 596 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 597 csBundle(0).ctrl.uopIdx := 0.U 598 599 csBundle(1).ctrl.srcType(2) := SrcType.DC 600 csBundle(1).ctrl.lsrc(0) := src2 + 3.U 601 csBundle(1).ctrl.lsrc(1) := src2 + 2.U 602 csBundle(1).ctrl.ldest := (VECTOR_TMP_REG_LMUL+1).U 603 csBundle(1).ctrl.uopIdx := 1.U 604 605 csBundle(2).ctrl.srcType(2) := SrcType.DC 606 csBundle(2).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL+1).U 607 csBundle(2).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U 608 csBundle(2).ctrl.ldest := (VECTOR_TMP_REG_LMUL+2).U 609 csBundle(2).ctrl.uopIdx := 2.U 610 } 611 when(simple.io.vconfig.vtype.vlmul === "b011".U) { 612 for(i <- 0 until MAX_VLMUL){ 613 if(i < MAX_VLMUL - MAX_VLMUL/2){ 614 csBundle(i).ctrl.lsrc(0) := src2 + (i * 2 + 1).U 615 csBundle(i).ctrl.lsrc(1) := src2 + (i * 2).U 616 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 617 } else if (i < MAX_VLMUL - MAX_VLMUL/4) { 618 csBundle(i).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2 + 1).U 619 csBundle(i).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2).U 620 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 621 }else if (i < MAX_VLMUL - MAX_VLMUL/8) { 622 csBundle(6).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 623 csBundle(6).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 624 csBundle(6).ctrl.ldest := (VECTOR_TMP_REG_LMUL + 6).U 625 } 626 csBundle(i).ctrl.srcType(2) := SrcType.DC 627 csBundle(i).ctrl.uopIdx := i.U 628 } 629 } 630 when (simple.io.vconfig.vtype.vlmul.orR()){ 631 csBundle(numOfUop - 1.U).ctrl.srcType(2) := SrcType.vp 632 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1 633 csBundle(numOfUop - 1.U).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 634 csBundle(numOfUop - 1.U).ctrl.lsrc(2) := dest 635 csBundle(numOfUop - 1.U).ctrl.ldest := dest 636 csBundle(numOfUop - 1.U).ctrl.uopIdx := numOfUop - 1.U 637 } 638 } 639 640 is(UopDivType.VEC_SLIDEUP) { 641 // FMV.D.X 642 csBundle(0).ctrl.srcType(0) := SrcType.reg 643 csBundle(0).ctrl.srcType(1) := SrcType.imm 644 csBundle(0).ctrl.lsrc(1) := 0.U 645 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 646 csBundle(0).ctrl.fuType := FuType.i2f 647 csBundle(0).ctrl.rfWen := false.B 648 csBundle(0).ctrl.fpWen := true.B 649 csBundle(0).ctrl.vecWen := false.B 650 csBundle(0).ctrl.fpu.isAddSub := false.B 651 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 652 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 653 csBundle(0).ctrl.fpu.fromInt := true.B 654 csBundle(0).ctrl.fpu.wflags := false.B 655 csBundle(0).ctrl.fpu.fpWen := true.B 656 csBundle(0).ctrl.fpu.div := false.B 657 csBundle(0).ctrl.fpu.sqrt := false.B 658 csBundle(0).ctrl.fpu.fcvt := false.B 659 // LMUL 660 for(i <- 0 until MAX_VLMUL) 661 for(j <- 0 to i){ 662 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 663 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 664 csBundle(i*(i+1)/2+j+1).ctrl.srcType(0) := SrcType.fp 665 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 666 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(1) := src2 + j.U 667 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(2) := old_vd 668 csBundle(i*(i+1)/2+j+1).ctrl.ldest := vd 669 csBundle(i*(i+1)/2+j+1).ctrl.uopIdx := (i*(i+1)/2+j).U 670 } 671 } 672 673 is(UopDivType.VEC_ISLIDEUP) { 674 // LMUL 675 for(i <- 0 until MAX_VLMUL) 676 for(j <- 0 to i){ 677 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 678 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 679 csBundle(i*(i+1)/2+j).ctrl.lsrc(1) := src2 + j.U 680 csBundle(i*(i+1)/2+j).ctrl.lsrc(2) := old_vd 681 csBundle(i*(i+1)/2+j).ctrl.ldest := vd 682 csBundle(i*(i+1)/2+j).ctrl.uopIdx := (i*(i+1)/2+j).U 683 } 684 } 685 686 is(UopDivType.VEC_SLIDEDOWN) { 687 // FMV.D.X 688 csBundle(0).ctrl.srcType(0) := SrcType.reg 689 csBundle(0).ctrl.srcType(1) := SrcType.imm 690 csBundle(0).ctrl.lsrc(1) := 0.U 691 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 692 csBundle(0).ctrl.fuType := FuType.i2f 693 csBundle(0).ctrl.rfWen := false.B 694 csBundle(0).ctrl.fpWen := true.B 695 csBundle(0).ctrl.vecWen := false.B 696 csBundle(0).ctrl.fpu.isAddSub := false.B 697 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 698 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 699 csBundle(0).ctrl.fpu.fromInt := true.B 700 csBundle(0).ctrl.fpu.wflags := false.B 701 csBundle(0).ctrl.fpu.fpWen := true.B 702 csBundle(0).ctrl.fpu.div := false.B 703 csBundle(0).ctrl.fpu.sqrt := false.B 704 csBundle(0).ctrl.fpu.fcvt := false.B 705 // LMUL 706 for(i <- 0 until MAX_VLMUL) 707 for(j <- (0 to i).reverse){ 708 when(i.U < lmul){ 709 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 710 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 711 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.srcType(0) := SrcType.fp 712 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(0) := FP_TMP_REG_MV.U 713 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(1) := src2 + lmul - 1.U - j.U 714 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(2) := old_vd 715 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.ldest := vd 716 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.uopIdx := numOfUop-(i*(i+1)/2+i-j+2).U 717 } 718 } 719 } 720 721 is(UopDivType.VEC_ISLIDEDOWN) { 722 // LMUL 723 for(i <- 0 until MAX_VLMUL) 724 for(j <- (0 to i).reverse){ 725 when(i.U < lmul){ 726 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 727 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 728 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(1) := src2 + lmul - 1.U - j.U 729 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(2) := old_vd 730 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.ldest := vd 731 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.uopIdx := numOfUop-(i*(i+1)/2+i-j+1).U 732 } 733 } 734 } 735 } 736 737 //uops dispatch 738 val normal :: ext :: Nil = Enum(2) 739 val stateReg = RegInit(normal) 740 val uopRes = RegInit(0.U) 741 742 //readyFromRename Counter 743 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 744 745 switch(stateReg) { 746 is(normal) { 747 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 748 } 749 is(ext) { 750 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 751 } 752 } 753 754 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 755 val uopResJudge = Mux(stateReg === normal, 756 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 757 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 758 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 759 760 for(i <- 0 until RenameWidth) { 761 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 762 (stateReg === normal) -> csBundle(i), 763 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 764 )) 765 } 766 767 768 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 769 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 770 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 771 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 772 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 773 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 774 notInfVec(0) := true.B 775 776 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 777 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 778 1.U) 779 validToRename.zipWithIndex.foreach{ 780 case(dst, i) => 781 dst := MuxCase(false.B, Seq( 782 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 783 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 784 )) 785 } 786 787 readyToIBuf.zipWithIndex.foreach { 788 case (dst, i) => 789 dst := MuxCase(true.B, Seq( 790 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 791 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 792 )) 793 } 794 795 io.deq.cf_ctrl := cf_ctrl 796 io.deq.isVset := isVset_u 797 io.deq.complexNum := complexNum 798 io.deq.validToRename := validToRename 799 io.deq.readyToIBuf := readyToIBuf 800 801} 802 803