1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VppuType 31import scala.collection.Seq 32 33trait VectorConstants { 34 val MAX_VLMUL = 8 35 val FP_TMP_REG_MV = 32 36 val VECTOR_TMP_REG_LMUL = 32 37} 38 39class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 40 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 41 val vconfig = Input(new VConfig) 42 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 43 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 44 val readyFromRename = Input(Vec(RenameWidth, Bool())) 45 val deq = new Bundle { 46 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 47 val isVset = Output(Bool()) 48 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 49 val validToRename = Output(Vec(RenameWidth, Bool())) 50 val complexNum = Output(UInt(3.W)) 51 } 52 val csrCtrl = Input(new CustomCSRCtrlIO) 53} 54 55class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 56 val io = IO(new DecodeUnitCompIO) 57 //input bits 58 val ctrl_flow = Wire(new CtrlFlow) 59 ctrl_flow := io.enq.ctrl_flow 60 //output bits 61 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 62 val validToRename = Wire(Vec(RenameWidth, Bool())) 63 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 64 val complexNum = Wire(UInt(3.W)) 65 66 //output of DecodeUnit 67 val cf_ctrl_u = Wire(new CfCtrl) 68 val isVset_u = Wire(Bool()) 69 70 //pre decode 71 val simple = Module(new DecodeUnit) 72 simple.io.enq.ctrl_flow := ctrl_flow 73 simple.io.vconfig := io.vconfig 74 simple.io.csrCtrl := io.csrCtrl 75 cf_ctrl_u := simple.io.deq.cf_ctrl 76 isVset_u := simple.io.deq.isVset 77 78 //Type of uop Div 79 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 80 81 //LMUL 82 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U, Array( 83 "b001".U -> 2.U, 84 "b010".U -> 4.U, 85 "b011".U -> 8.U 86 )) 87 //number of uop 88 val numOfUop = MuxLookup(typeOfDiv, 1.U, Array( 89 UopDivType.VEC_0XV -> 2.U, 90 UopDivType.DIR -> 2.U, 91 UopDivType.VEC_VVV -> lmul, 92 UopDivType.VEC_EXT2 -> lmul, 93 UopDivType.VEC_EXT4 -> lmul, 94 UopDivType.VEC_EXT8 -> lmul, 95 UopDivType.VEC_VVM -> lmul, 96 UopDivType.VEC_VXM -> (lmul + 1.U), 97 UopDivType.VEC_VXV -> (lmul + 1.U), 98 UopDivType.VEC_VVW -> (lmul + lmul), // lmul <= 4 99 UopDivType.VEC_WVW -> (lmul + lmul), // lmul <= 4 100 UopDivType.VEC_VXW -> (lmul + lmul + 1.U), // lmul <= 4 101 UopDivType.VEC_WXW -> (lmul + lmul + 1.U), // lmul <= 4 102 UopDivType.VEC_WVV -> (lmul + lmul), // lmul <= 4 103 UopDivType.VEC_WXV -> (lmul + lmul + 1.U) // lmul <= 4 104 )) 105 106 //uop div up to maxNumOfUop 107 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 108 csBundle.map { case dst => 109 dst := cf_ctrl_u 110 dst.ctrl.firstUop := false.B 111 dst.ctrl.lastUop := false.B 112 } 113 114 csBundle(0).ctrl.firstUop := true.B 115 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 116 117 switch(typeOfDiv) { 118 is(UopDivType.DIR) { 119 when(isVset_u) { 120 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR 121 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 122 csBundle(1).ctrl.ldest := 32.U 123 csBundle(1).ctrl.flushPipe := false.B 124 } 125 } 126 is(UopDivType.VEC_VVV) { 127 for (i <- 0 until MAX_VLMUL) { 128 csBundle(i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 129 csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 130 csBundle(i).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 131 csBundle(i).ctrl.uopIdx := i.U 132 } 133 } 134 is(UopDivType.VEC_EXT2) { 135 for (i <- 0 until MAX_VLMUL / 2) { 136 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 137 csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 138 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 139 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 140 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 141 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 142 } 143 } 144 is(UopDivType.VEC_EXT4) { 145 for (i <- 0 until MAX_VLMUL / 4) { 146 csBundle(4 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 147 csBundle(4 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i).U 148 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 149 csBundle(4 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 150 csBundle(4 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 1).U 151 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 152 csBundle(4 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 153 csBundle(4 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 2).U 154 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 155 csBundle(4 * i + 3).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 156 csBundle(4 * i + 3).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 3).U 157 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 158 } 159 } 160 is(UopDivType.VEC_EXT8) { 161 for (i <- 0 until MAX_VLMUL) { 162 csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) 163 csBundle(i).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 164 csBundle(i).ctrl.uopIdx := i.U 165 } 166 } 167 is(UopDivType.VEC_0XV) { 168 /* 169 FMV.D.X 170 */ 171 csBundle(0).ctrl.srcType(0) := SrcType.reg 172 csBundle(0).ctrl.srcType(1) := SrcType.imm 173 csBundle(0).ctrl.lsrc(1) := 0.U 174 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 175 csBundle(0).ctrl.fuType := FuType.i2f 176 csBundle(0).ctrl.rfWen := false.B 177 csBundle(0).ctrl.fpWen := true.B 178 csBundle(0).ctrl.vecWen := false.B 179 csBundle(0).ctrl.fpu.isAddSub := false.B 180 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 181 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 182 csBundle(0).ctrl.fpu.fromInt := true.B 183 csBundle(0).ctrl.fpu.wflags := false.B 184 csBundle(0).ctrl.fpu.fpWen := true.B 185 csBundle(0).ctrl.fpu.div := false.B 186 csBundle(0).ctrl.fpu.sqrt := false.B 187 csBundle(0).ctrl.fpu.fcvt := false.B 188 /* 189 vfmv.s.f 190 */ 191 csBundle(1).ctrl.srcType(0) := SrcType.fp 192 csBundle(1).ctrl.srcType(1) := SrcType.vp 193 csBundle(1).ctrl.srcType(2) := SrcType.vp 194 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 195 csBundle(1).ctrl.lsrc(1) := 0.U 196 csBundle(1).ctrl.lsrc(2) := ctrl_flow.instr(11, 7) 197 csBundle(1).ctrl.ldest := ctrl_flow.instr(11, 7) 198 csBundle(1).ctrl.fuType := FuType.vppu 199 csBundle(1).ctrl.fuOpType := VppuType.f2s 200 csBundle(1).ctrl.rfWen := false.B 201 csBundle(1).ctrl.fpWen := false.B 202 csBundle(1).ctrl.vecWen := true.B 203 } 204 is(UopDivType.VEC_VXV) { 205 /* 206 FMV.D.X 207 */ 208 csBundle(0).ctrl.srcType(0) := SrcType.reg 209 csBundle(0).ctrl.srcType(1) := SrcType.imm 210 csBundle(0).ctrl.lsrc(1) := 0.U 211 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 212 csBundle(0).ctrl.fuType := FuType.i2f 213 csBundle(0).ctrl.rfWen := false.B 214 csBundle(0).ctrl.fpWen := true.B 215 csBundle(0).ctrl.vecWen := false.B 216 csBundle(0).ctrl.fpu.isAddSub := false.B 217 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 218 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 219 csBundle(0).ctrl.fpu.fromInt := true.B 220 csBundle(0).ctrl.fpu.wflags := false.B 221 csBundle(0).ctrl.fpu.fpWen := false.B 222 csBundle(0).ctrl.fpu.div := false.B 223 csBundle(0).ctrl.fpu.sqrt := false.B 224 csBundle(0).ctrl.fpu.fcvt := false.B 225 /* 226 LMUL 227 */ 228 for (i <- 0 until MAX_VLMUL) { 229 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 230 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 231 csBundle(i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 232 csBundle(i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 233 csBundle(i + 1).ctrl.uopIdx := i.U 234 } 235 } 236 is(UopDivType.VEC_VVW) { 237 for (i <- 0 until MAX_VLMUL / 2) { 238 csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 239 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 240 csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 241 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 242 csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 243 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 244 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 245 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 246 } 247 } 248 is(UopDivType.VEC_WVW) { 249 for (i <- 0 until MAX_VLMUL / 2) { 250 csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 251 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 252 csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 253 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 254 csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 255 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 256 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 257 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 258 } 259 } 260 is(UopDivType.VEC_VXW) { 261 /* 262 FMV.D.X 263 */ 264 csBundle(0).ctrl.srcType(0) := SrcType.reg 265 csBundle(0).ctrl.srcType(1) := SrcType.imm 266 csBundle(0).ctrl.lsrc(1) := 0.U 267 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 268 csBundle(0).ctrl.fuType := FuType.i2f 269 csBundle(0).ctrl.rfWen := false.B 270 csBundle(0).ctrl.fpWen := true.B 271 csBundle(0).ctrl.vecWen := false.B 272 csBundle(0).ctrl.fpu.isAddSub := false.B 273 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 274 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 275 csBundle(0).ctrl.fpu.fromInt := true.B 276 csBundle(0).ctrl.fpu.wflags := false.B 277 csBundle(0).ctrl.fpu.fpWen := false.B 278 csBundle(0).ctrl.fpu.div := false.B 279 csBundle(0).ctrl.fpu.sqrt := false.B 280 csBundle(0).ctrl.fpu.fcvt := false.B 281 282 for (i <- 0 until MAX_VLMUL / 2) { 283 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 284 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 285 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 286 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 287 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 288 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 289 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 290 csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 291 csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 292 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 293 } 294 } 295 is(UopDivType.VEC_WXW) { 296 /* 297 FMV.D.X 298 */ 299 csBundle(0).ctrl.srcType(0) := SrcType.reg 300 csBundle(0).ctrl.srcType(1) := SrcType.imm 301 csBundle(0).ctrl.lsrc(1) := 0.U 302 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 303 csBundle(0).ctrl.fuType := FuType.i2f 304 csBundle(0).ctrl.rfWen := false.B 305 csBundle(0).ctrl.fpWen := true.B 306 csBundle(0).ctrl.vecWen := false.B 307 csBundle(0).ctrl.fpu.isAddSub := false.B 308 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 309 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 310 csBundle(0).ctrl.fpu.fromInt := true.B 311 csBundle(0).ctrl.fpu.wflags := false.B 312 csBundle(0).ctrl.fpu.fpWen := false.B 313 csBundle(0).ctrl.fpu.div := false.B 314 csBundle(0).ctrl.fpu.sqrt := false.B 315 csBundle(0).ctrl.fpu.fcvt := false.B 316 317 for (i <- 0 until MAX_VLMUL / 2) { 318 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 319 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 320 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 321 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 322 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 323 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 324 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 325 csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 326 csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 327 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 328 } 329 } 330 is(UopDivType.VEC_WVV) { 331 for (i <- 0 until MAX_VLMUL / 2) { 332 333 csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 334 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 335 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 336 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 337 csBundle(2 * i + 1).ctrl.srcType(2) := SrcType.vp 338 csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 339 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 340 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 341 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 342 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 343 } 344 } 345 is(UopDivType.VEC_WXV) { 346 /* 347 FMV.D.X 348 */ 349 csBundle(0).ctrl.srcType(0) := SrcType.reg 350 csBundle(0).ctrl.srcType(1) := SrcType.imm 351 csBundle(0).ctrl.lsrc(1) := 0.U 352 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 353 csBundle(0).ctrl.fuType := FuType.i2f 354 csBundle(0).ctrl.rfWen := false.B 355 csBundle(0).ctrl.fpWen := true.B 356 csBundle(0).ctrl.vecWen := false.B 357 csBundle(0).ctrl.fpu.isAddSub := false.B 358 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 359 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 360 csBundle(0).ctrl.fpu.fromInt := true.B 361 csBundle(0).ctrl.fpu.wflags := false.B 362 csBundle(0).ctrl.fpu.fpWen := false.B 363 csBundle(0).ctrl.fpu.div := false.B 364 csBundle(0).ctrl.fpu.sqrt := false.B 365 csBundle(0).ctrl.fpu.fcvt := false.B 366 367 for (i <- 0 until MAX_VLMUL / 2) { 368 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 369 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 370 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 371 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 372 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 373 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 374 csBundle(2 * i + 2).ctrl.srcType(2) := SrcType.vp 375 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 376 csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 377 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 378 csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 379 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 380 } 381 } 382 is(UopDivType.VEC_VVM) { 383 csBundle(0).ctrl.srcType(2) := SrcType.vp 384 csBundle(0).ctrl.lsrc(2) := ctrl_flow.instr(11, 7) 385 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 386 csBundle(0).ctrl.uopIdx := 0.U 387 for(i <- 1 until MAX_VLMUL) { 388 csBundle(i).ctrl.srcType(2) := SrcType.vp 389 csBundle(i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 390 csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 391 csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 392 csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 393 csBundle(i).ctrl.uopIdx := i.U 394 } 395 csBundle(numOfUop - 1.U).ctrl.ldest := ctrl_flow.instr(11, 7) 396 } 397 is(UopDivType.VEC_VXM) { 398 /* 399 FMV.D.X 400 */ 401 csBundle(0).ctrl.srcType(0) := SrcType.reg 402 csBundle(0).ctrl.srcType(1) := SrcType.imm 403 csBundle(0).ctrl.lsrc(1) := 0.U 404 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 405 csBundle(0).ctrl.fuType := FuType.i2f 406 csBundle(0).ctrl.rfWen := false.B 407 csBundle(0).ctrl.fpWen := true.B 408 csBundle(0).ctrl.vecWen := false.B 409 csBundle(0).ctrl.fpu.isAddSub := false.B 410 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 411 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 412 csBundle(0).ctrl.fpu.fromInt := true.B 413 csBundle(0).ctrl.fpu.wflags := false.B 414 csBundle(0).ctrl.fpu.fpWen := false.B 415 csBundle(0).ctrl.fpu.div := false.B 416 csBundle(0).ctrl.fpu.sqrt := false.B 417 csBundle(0).ctrl.fpu.fcvt := false.B 418 //LMUL 419 csBundle(1).ctrl.srcType(0) := SrcType.fp 420 csBundle(1).ctrl.srcType(2) := SrcType.vp 421 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 422 csBundle(1).ctrl.lsrc(2) := ctrl_flow.instr(11, 7) 423 csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 424 csBundle(1).ctrl.uopIdx := 0.U 425 for (i <- 1 until MAX_VLMUL) { 426 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 427 csBundle(i + 1).ctrl.srcType(2) := SrcType.vp 428 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 429 csBundle(i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 430 csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 431 csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 432 csBundle(i + 1).ctrl.uopIdx := i.U 433 } 434 csBundle(numOfUop - 1.U).ctrl.ldest := ctrl_flow.instr(11,7) 435 } 436 } 437 438 //uops dispatch 439 val normal :: ext :: Nil = Enum(2) 440 val stateReg = RegInit(normal) 441 val uopRes = RegInit(0.U) 442 443 //readyFromRename Counter 444 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 445 446 switch(stateReg) { 447 is(normal) { 448 when(!io.validFromIBuf(0)) { 449 stateReg := normal 450 uopRes := 0.U 451 }.elsewhen((numOfUop > readyCounter) && (readyCounter =/= 0.U)){ 452 stateReg := ext 453 uopRes := numOfUop - readyCounter 454 }.otherwise { 455 stateReg := normal 456 uopRes := 0.U 457 } 458 } 459 is(ext) { 460 when(!io.validFromIBuf(0)) { 461 stateReg := normal 462 uopRes := 0.U 463 }.elsewhen(uopRes > readyCounter) { 464 stateReg := ext 465 uopRes := uopRes - readyCounter 466 }.otherwise { 467 stateReg := normal 468 uopRes := 0.U 469 } 470 } 471 } 472 473 for(i <- 0 until RenameWidth) { 474 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 475 (stateReg === normal) -> csBundle(i), 476 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 477 )) 478 } 479 480 481 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 482 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 483 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 484 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 485 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 486 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 487 notInfVec(0) := true.B 488 489 complexNum := 1.U 490 validToRename.map{ case dst => dst := false.B } 491 readyToIBuf .map{ case dst => dst := false.B } 492 switch(stateReg) { 493 is(normal) { 494 when(!io.validFromIBuf(0)) { 495 complexNum := 1.U 496 validToRename(0) := false.B 497 for (i <- 1 until RenameWidth) { 498 validToRename(i) := notInfVec(i - 1) && validSimple(i - 1) 499 } 500 readyToIBuf(0) := io.readyFromRename(0) 501 for(i <- 1 until DecodeWidth) { 502 readyToIBuf(i) := notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i) 503 } 504 }.elsewhen(numOfUop > readyCounter) { 505 complexNum := Mux(readyCounter === 0.U, 1.U, readyCounter) 506 for (i <- 0 until RenameWidth) { 507 validToRename(i) := Mux(readyCounter > i.U, true.B, false.B) 508 } 509 readyToIBuf.map{ case dst => dst := false.B } 510 }.otherwise { 511 complexNum := numOfUop 512 for (i <- 0 until RenameWidth) { 513 validToRename(i) := Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)) 514 } 515 readyToIBuf(0) := true.B 516 for (i <- 1 until DecodeWidth) { 517 readyToIBuf(i) := Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B) 518 } 519 } 520 } 521 is(ext) { 522 when(!io.validFromIBuf(0)) { 523 complexNum := 1.U 524 validToRename.map{ case dst => dst := false.B } 525 readyToIBuf.map{ case dst => dst := true.B } 526 }.elsewhen(uopRes > readyCounter) { 527 complexNum := Mux(readyCounter === 0.U, 1.U, readyCounter) 528 for (i <- 0 until RenameWidth) { 529 validToRename(i) := Mux(readyCounter > i.U, true.B, false.B) 530 } 531 readyToIBuf.map{ case dst => dst := false.B } 532 }.otherwise { 533 complexNum := uopRes 534 for (i <- 0 until RenameWidth) { 535 validToRename(i) := Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)) 536 } 537 readyToIBuf(0) := true.B 538 for (i <- 1 until DecodeWidth) { 539 readyToIBuf(i) := Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B) 540 } 541 } 542 } 543 } 544 545 io.deq.cf_ctrl := cf_ctrl 546 io.deq.isVset := isVset_u 547 io.deq.complexNum := complexNum 548 io.deq.validToRename := validToRename 549 io.deq.readyToIBuf := readyToIBuf 550 551} 552 553