1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VppuType 31import scala.collection.Seq 32 33trait VectorConstants { 34 val MAX_VLMUL = 8 35 val FP_TMP_REG_MV = 33 36 // val FP_TMP_REG_MV = 34 37 val VECTOR_TMP_REG_LMUL = 34 38} 39 40class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 41 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 42 val vconfig = Input(new VConfig) 43 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 44 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 45 val readyFromRename = Input(Vec(RenameWidth, Bool())) 46 val deq = new Bundle { 47 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 48 val isVset = Output(Bool()) 49 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 50 val validToRename = Output(Vec(RenameWidth, Bool())) 51 val complexNum = Output(UInt(3.W)) 52 } 53 val csrCtrl = Input(new CustomCSRCtrlIO) 54} 55 56class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 57 val io = IO(new DecodeUnitCompIO) 58 //input bits 59 val ctrl_flow = Wire(new CtrlFlow) 60 ctrl_flow := io.enq.ctrl_flow 61 //output bits 62 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 63 val validToRename = Wire(Vec(RenameWidth, Bool())) 64 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 65 val complexNum = Wire(UInt(3.W)) 66 67 //output of DecodeUnit 68 val cf_ctrl_u = Wire(new CfCtrl) 69 val isVset_u = Wire(Bool()) 70 71 //pre decode 72 val simple = Module(new DecodeUnit) 73 simple.io.enq.ctrl_flow := ctrl_flow 74 simple.io.vconfig := io.vconfig 75 simple.io.csrCtrl := io.csrCtrl 76 cf_ctrl_u := simple.io.deq.cf_ctrl 77 isVset_u := simple.io.deq.isVset 78 79 //Type of uop Div 80 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 81 82 //LMUL 83 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U, Array( 84 "b001".U -> 2.U, 85 "b010".U -> 4.U, 86 "b011".U -> 8.U 87 )) 88 //number of uop 89 val numOfUop = MuxLookup(typeOfDiv, 1.U, Array( 90 UopDivType.VEC_0XV -> 2.U, 91 UopDivType.DIR -> 2.U, 92 UopDivType.VEC_VVV -> lmul, 93 UopDivType.VEC_EXT2 -> lmul, 94 UopDivType.VEC_EXT4 -> lmul, 95 UopDivType.VEC_EXT8 -> lmul, 96 UopDivType.VEC_VVM -> lmul, 97 UopDivType.VEC_VXM -> (lmul + 1.U), 98 UopDivType.VEC_VXV -> (lmul + 1.U), 99 UopDivType.VEC_VVW -> (lmul + lmul), // lmul <= 4 100 UopDivType.VEC_WVW -> (lmul + lmul), // lmul <= 4 101 UopDivType.VEC_VXW -> (lmul + lmul + 1.U), // lmul <= 4 102 UopDivType.VEC_WXW -> (lmul + lmul + 1.U), // lmul <= 4 103 UopDivType.VEC_WVV -> (lmul + lmul), // lmul <= 4 104 UopDivType.VEC_WXV -> (lmul + lmul + 1.U) // lmul <= 4 105 )) 106 107 //uop div up to maxNumOfUop 108 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 109 csBundle.map { case dst => 110 dst := cf_ctrl_u 111 dst.ctrl.firstUop := false.B 112 dst.ctrl.lastUop := false.B 113 } 114 115 csBundle(0).ctrl.firstUop := true.B 116 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 117 118 switch(typeOfDiv) { 119 is(UopDivType.DIR) { 120 when(isVset_u) { 121 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR 122 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 123 csBundle(1).ctrl.ldest := 32.U 124 csBundle(1).ctrl.flushPipe := false.B 125 } 126 } 127 is(UopDivType.VEC_VVV) { 128 for (i <- 0 until MAX_VLMUL) { 129 csBundle(i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 130 csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 131 csBundle(i).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 132 csBundle(i).ctrl.uopIdx := i.U 133 } 134 } 135 is(UopDivType.VEC_EXT2) { 136 for (i <- 0 until MAX_VLMUL / 2) { 137 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 138 csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 139 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 140 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 141 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 142 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 143 } 144 } 145 is(UopDivType.VEC_EXT4) { 146 for (i <- 0 until MAX_VLMUL / 4) { 147 csBundle(4 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 148 csBundle(4 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i).U 149 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 150 csBundle(4 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 151 csBundle(4 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 1).U 152 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 153 csBundle(4 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 154 csBundle(4 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 2).U 155 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 156 csBundle(4 * i + 3).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 157 csBundle(4 * i + 3).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 3).U 158 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 159 } 160 } 161 is(UopDivType.VEC_EXT8) { 162 for (i <- 0 until MAX_VLMUL) { 163 csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) 164 csBundle(i).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 165 csBundle(i).ctrl.uopIdx := i.U 166 } 167 } 168 is(UopDivType.VEC_0XV) { 169 /* 170 FMV.D.X 171 */ 172 csBundle(0).ctrl.srcType(0) := SrcType.reg 173 csBundle(0).ctrl.srcType(1) := SrcType.imm 174 csBundle(0).ctrl.lsrc(1) := 0.U 175 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 176 csBundle(0).ctrl.fuType := FuType.i2f 177 csBundle(0).ctrl.rfWen := false.B 178 csBundle(0).ctrl.fpWen := true.B 179 csBundle(0).ctrl.vecWen := false.B 180 csBundle(0).ctrl.fpu.isAddSub := false.B 181 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 182 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 183 csBundle(0).ctrl.fpu.fromInt := true.B 184 csBundle(0).ctrl.fpu.wflags := false.B 185 csBundle(0).ctrl.fpu.fpWen := true.B 186 csBundle(0).ctrl.fpu.div := false.B 187 csBundle(0).ctrl.fpu.sqrt := false.B 188 csBundle(0).ctrl.fpu.fcvt := false.B 189 /* 190 vfmv.s.f 191 */ 192 csBundle(1).ctrl.srcType(0) := SrcType.fp 193 csBundle(1).ctrl.srcType(1) := SrcType.vp 194 csBundle(1).ctrl.srcType(2) := SrcType.vp 195 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 196 csBundle(1).ctrl.lsrc(1) := 0.U 197 csBundle(1).ctrl.lsrc(2) := ctrl_flow.instr(11, 7) 198 csBundle(1).ctrl.ldest := ctrl_flow.instr(11, 7) 199 csBundle(1).ctrl.fuType := FuType.vppu 200 csBundle(1).ctrl.fuOpType := VppuType.f2s 201 csBundle(1).ctrl.rfWen := false.B 202 csBundle(1).ctrl.fpWen := false.B 203 csBundle(1).ctrl.vecWen := true.B 204 } 205 is(UopDivType.VEC_VXV) { 206 /* 207 FMV.D.X 208 */ 209 csBundle(0).ctrl.srcType(0) := SrcType.reg 210 csBundle(0).ctrl.srcType(1) := SrcType.imm 211 csBundle(0).ctrl.lsrc(1) := 0.U 212 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 213 csBundle(0).ctrl.fuType := FuType.i2f 214 csBundle(0).ctrl.rfWen := false.B 215 csBundle(0).ctrl.fpWen := true.B 216 csBundle(0).ctrl.vecWen := false.B 217 csBundle(0).ctrl.fpu.isAddSub := false.B 218 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 219 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 220 csBundle(0).ctrl.fpu.fromInt := true.B 221 csBundle(0).ctrl.fpu.wflags := false.B 222 csBundle(0).ctrl.fpu.fpWen := false.B 223 csBundle(0).ctrl.fpu.div := false.B 224 csBundle(0).ctrl.fpu.sqrt := false.B 225 csBundle(0).ctrl.fpu.fcvt := false.B 226 /* 227 LMUL 228 */ 229 for (i <- 0 until MAX_VLMUL) { 230 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 231 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 232 csBundle(i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 233 csBundle(i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 234 csBundle(i + 1).ctrl.uopIdx := i.U 235 } 236 } 237 is(UopDivType.VEC_VVW) { 238 for (i <- 0 until MAX_VLMUL / 2) { 239 csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 240 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 241 csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 242 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 243 csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 244 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 245 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 246 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 247 } 248 } 249 is(UopDivType.VEC_WVW) { 250 for (i <- 0 until MAX_VLMUL / 2) { 251 csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 252 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 253 csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 254 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 255 csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 256 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 257 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 258 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 259 } 260 } 261 is(UopDivType.VEC_VXW) { 262 /* 263 FMV.D.X 264 */ 265 csBundle(0).ctrl.srcType(0) := SrcType.reg 266 csBundle(0).ctrl.srcType(1) := SrcType.imm 267 csBundle(0).ctrl.lsrc(1) := 0.U 268 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 269 csBundle(0).ctrl.fuType := FuType.i2f 270 csBundle(0).ctrl.rfWen := false.B 271 csBundle(0).ctrl.fpWen := true.B 272 csBundle(0).ctrl.vecWen := false.B 273 csBundle(0).ctrl.fpu.isAddSub := false.B 274 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 275 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 276 csBundle(0).ctrl.fpu.fromInt := true.B 277 csBundle(0).ctrl.fpu.wflags := false.B 278 csBundle(0).ctrl.fpu.fpWen := false.B 279 csBundle(0).ctrl.fpu.div := false.B 280 csBundle(0).ctrl.fpu.sqrt := false.B 281 csBundle(0).ctrl.fpu.fcvt := false.B 282 283 for (i <- 0 until MAX_VLMUL / 2) { 284 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 285 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 286 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 287 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 288 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 289 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 290 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 291 csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 292 csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 293 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 294 } 295 } 296 is(UopDivType.VEC_WXW) { 297 /* 298 FMV.D.X 299 */ 300 csBundle(0).ctrl.srcType(0) := SrcType.reg 301 csBundle(0).ctrl.srcType(1) := SrcType.imm 302 csBundle(0).ctrl.lsrc(1) := 0.U 303 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 304 csBundle(0).ctrl.fuType := FuType.i2f 305 csBundle(0).ctrl.rfWen := false.B 306 csBundle(0).ctrl.fpWen := true.B 307 csBundle(0).ctrl.vecWen := false.B 308 csBundle(0).ctrl.fpu.isAddSub := false.B 309 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 310 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 311 csBundle(0).ctrl.fpu.fromInt := true.B 312 csBundle(0).ctrl.fpu.wflags := false.B 313 csBundle(0).ctrl.fpu.fpWen := false.B 314 csBundle(0).ctrl.fpu.div := false.B 315 csBundle(0).ctrl.fpu.sqrt := false.B 316 csBundle(0).ctrl.fpu.fcvt := false.B 317 318 for (i <- 0 until MAX_VLMUL / 2) { 319 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 320 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 321 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 322 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 323 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 324 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 325 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 326 csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 327 csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 328 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 329 } 330 } 331 is(UopDivType.VEC_WVV) { 332 for (i <- 0 until MAX_VLMUL / 2) { 333 334 csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 335 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 336 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 337 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 338 csBundle(2 * i + 1).ctrl.srcType(2) := SrcType.vp 339 csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 340 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 341 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 342 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 343 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 344 } 345 } 346 is(UopDivType.VEC_WXV) { 347 /* 348 FMV.D.X 349 */ 350 csBundle(0).ctrl.srcType(0) := SrcType.reg 351 csBundle(0).ctrl.srcType(1) := SrcType.imm 352 csBundle(0).ctrl.lsrc(1) := 0.U 353 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 354 csBundle(0).ctrl.fuType := FuType.i2f 355 csBundle(0).ctrl.rfWen := false.B 356 csBundle(0).ctrl.fpWen := true.B 357 csBundle(0).ctrl.vecWen := false.B 358 csBundle(0).ctrl.fpu.isAddSub := false.B 359 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 360 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 361 csBundle(0).ctrl.fpu.fromInt := true.B 362 csBundle(0).ctrl.fpu.wflags := false.B 363 csBundle(0).ctrl.fpu.fpWen := false.B 364 csBundle(0).ctrl.fpu.div := false.B 365 csBundle(0).ctrl.fpu.sqrt := false.B 366 csBundle(0).ctrl.fpu.fcvt := false.B 367 368 for (i <- 0 until MAX_VLMUL / 2) { 369 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 370 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 371 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 372 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 373 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 374 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 375 csBundle(2 * i + 2).ctrl.srcType(2) := SrcType.vp 376 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 377 csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 378 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 379 csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 380 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 381 } 382 } 383 is(UopDivType.VEC_VVM) { 384 csBundle(0).ctrl.srcType(2) := SrcType.vp 385 csBundle(0).ctrl.lsrc(2) := ctrl_flow.instr(11, 7) 386 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 387 csBundle(0).ctrl.uopIdx := 0.U 388 for(i <- 1 until MAX_VLMUL) { 389 csBundle(i).ctrl.srcType(2) := SrcType.vp 390 csBundle(i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 391 csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 392 csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 393 csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 394 csBundle(i).ctrl.uopIdx := i.U 395 } 396 csBundle(numOfUop - 1.U).ctrl.ldest := ctrl_flow.instr(11, 7) 397 } 398 is(UopDivType.VEC_VXM) { 399 /* 400 FMV.D.X 401 */ 402 csBundle(0).ctrl.srcType(0) := SrcType.reg 403 csBundle(0).ctrl.srcType(1) := SrcType.imm 404 csBundle(0).ctrl.lsrc(1) := 0.U 405 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 406 csBundle(0).ctrl.fuType := FuType.i2f 407 csBundle(0).ctrl.rfWen := false.B 408 csBundle(0).ctrl.fpWen := true.B 409 csBundle(0).ctrl.vecWen := false.B 410 csBundle(0).ctrl.fpu.isAddSub := false.B 411 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 412 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 413 csBundle(0).ctrl.fpu.fromInt := true.B 414 csBundle(0).ctrl.fpu.wflags := false.B 415 csBundle(0).ctrl.fpu.fpWen := false.B 416 csBundle(0).ctrl.fpu.div := false.B 417 csBundle(0).ctrl.fpu.sqrt := false.B 418 csBundle(0).ctrl.fpu.fcvt := false.B 419 //LMUL 420 csBundle(1).ctrl.srcType(0) := SrcType.fp 421 csBundle(1).ctrl.srcType(2) := SrcType.vp 422 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 423 csBundle(1).ctrl.lsrc(2) := ctrl_flow.instr(11, 7) 424 csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 425 csBundle(1).ctrl.uopIdx := 0.U 426 for (i <- 1 until MAX_VLMUL) { 427 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 428 csBundle(i + 1).ctrl.srcType(2) := SrcType.vp 429 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 430 csBundle(i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 431 csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 432 csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 433 csBundle(i + 1).ctrl.uopIdx := i.U 434 } 435 csBundle(numOfUop - 1.U).ctrl.ldest := ctrl_flow.instr(11,7) 436 } 437 } 438 439 //uops dispatch 440 val normal :: ext :: Nil = Enum(2) 441 val stateReg = RegInit(normal) 442 val uopRes = RegInit(0.U) 443 444 //readyFromRename Counter 445 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 446 447 switch(stateReg) { 448 is(normal) { 449 when(!io.validFromIBuf(0)) { 450 stateReg := normal 451 uopRes := 0.U 452 }.elsewhen((numOfUop > readyCounter) && (readyCounter =/= 0.U)){ 453 stateReg := ext 454 uopRes := numOfUop - readyCounter 455 }.otherwise { 456 stateReg := normal 457 uopRes := 0.U 458 } 459 } 460 is(ext) { 461 when(!io.validFromIBuf(0)) { 462 stateReg := normal 463 uopRes := 0.U 464 }.elsewhen(uopRes > readyCounter) { 465 stateReg := ext 466 uopRes := uopRes - readyCounter 467 }.otherwise { 468 stateReg := normal 469 uopRes := 0.U 470 } 471 } 472 } 473 474 for(i <- 0 until RenameWidth) { 475 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 476 (stateReg === normal) -> csBundle(i), 477 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 478 )) 479 } 480 481 482 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 483 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 484 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 485 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 486 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 487 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 488 notInfVec(0) := true.B 489 490 complexNum := 1.U 491 validToRename.map{ case dst => dst := false.B } 492 readyToIBuf .map{ case dst => dst := false.B } 493 switch(stateReg) { 494 is(normal) { 495 when(!io.validFromIBuf(0)) { 496 complexNum := 1.U 497 validToRename(0) := false.B 498 for (i <- 1 until RenameWidth) { 499 validToRename(i) := notInfVec(i - 1) && validSimple(i - 1) 500 } 501 readyToIBuf(0) := io.readyFromRename(0) 502 for(i <- 1 until DecodeWidth) { 503 readyToIBuf(i) := notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i) 504 } 505 }.elsewhen(numOfUop > readyCounter) { 506 complexNum := Mux(readyCounter === 0.U, 1.U, readyCounter) 507 for (i <- 0 until RenameWidth) { 508 validToRename(i) := Mux(readyCounter > i.U, true.B, false.B) 509 } 510 readyToIBuf.map{ case dst => dst := false.B } 511 }.otherwise { 512 complexNum := numOfUop 513 for (i <- 0 until RenameWidth) { 514 validToRename(i) := Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)) 515 } 516 readyToIBuf(0) := true.B 517 for (i <- 1 until DecodeWidth) { 518 readyToIBuf(i) := Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B) 519 } 520 } 521 } 522 is(ext) { 523 when(!io.validFromIBuf(0)) { 524 complexNum := 1.U 525 validToRename.map{ case dst => dst := false.B } 526 readyToIBuf.map{ case dst => dst := true.B } 527 }.elsewhen(uopRes > readyCounter) { 528 complexNum := Mux(readyCounter === 0.U, 1.U, readyCounter) 529 for (i <- 0 until RenameWidth) { 530 validToRename(i) := Mux(readyCounter > i.U, true.B, false.B) 531 } 532 readyToIBuf.map{ case dst => dst := false.B } 533 }.otherwise { 534 complexNum := uopRes 535 for (i <- 0 until RenameWidth) { 536 validToRename(i) := Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)) 537 } 538 readyToIBuf(0) := true.B 539 for (i <- 1 until DecodeWidth) { 540 readyToIBuf(i) := Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B) 541 } 542 } 543 } 544 } 545 546 io.deq.cf_ctrl := cf_ctrl 547 io.deq.isVset := isVset_u 548 io.deq.complexNum := complexNum 549 io.deq.validToRename := validToRename 550 io.deq.readyToIBuf := readyToIBuf 551 552} 553 554