1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VpermType 31import scala.collection.Seq 32 33trait VectorConstants { 34 val MAX_VLMUL = 8 35 val INT_VCONFIG = 32 36 val FP_TMP_REG_MV = 32 37 val VECTOR_TMP_REG_LMUL = 32 // 32~38 -> 7 38} 39 40class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 41 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 42 val vconfig = Input(new VConfig) 43 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 44 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 45 val readyFromRename = Input(Vec(RenameWidth, Bool())) 46 val deq = new Bundle { 47 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 48 val isVset = Output(Bool()) 49 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 50 val validToRename = Output(Vec(RenameWidth, Bool())) 51 val complexNum = Output(UInt(3.W)) 52 } 53 val csrCtrl = Input(new CustomCSRCtrlIO) 54} 55 56class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 57 val io = IO(new DecodeUnitCompIO) 58 //input bits 59 val ctrl_flow = Wire(new CtrlFlow) 60 ctrl_flow := io.enq.ctrl_flow 61 //output bits 62 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 63 val validToRename = Wire(Vec(RenameWidth, Bool())) 64 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 65 val complexNum = Wire(UInt(3.W)) 66 67 //output of DecodeUnit 68 val cf_ctrl_u = Wire(new CfCtrl) 69 val isVset_u = Wire(Bool()) 70 71 //pre decode 72 val simple = Module(new DecodeUnit) 73 simple.io.enq.ctrl_flow := ctrl_flow 74 simple.io.vconfig := io.vconfig 75 simple.io.csrCtrl := io.csrCtrl 76 cf_ctrl_u := simple.io.deq.cf_ctrl 77 isVset_u := simple.io.deq.isVset 78 79 //Type of uop Div 80 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 81 82 //LMUL 83 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(4.W), Array( 84 "b001".U -> 2.U, 85 "b010".U -> 4.U, 86 "b011".U -> 8.U 87 )) 88 //number of uop 89 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxNumOfUop+1).W), Array( 90 UopDivType.VEC_0XV -> 2.U, 91 UopDivType.DIR -> 2.U, 92 UopDivType.VEC_VVV -> lmul, 93 UopDivType.VEC_EXT2 -> lmul, 94 UopDivType.VEC_EXT4 -> lmul, 95 UopDivType.VEC_EXT8 -> lmul, 96 UopDivType.VEC_VVM -> lmul, 97 UopDivType.VEC_VXM -> (lmul +& 1.U), 98 UopDivType.VEC_VXV -> (lmul +& 1.U), 99 UopDivType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 100 UopDivType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 101 UopDivType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 102 UopDivType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 103 UopDivType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 104 UopDivType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 105 UopDivType.VEC_SLIDE1UP -> (lmul +& 1.U), 106 UopDivType.VEC_FSLIDE1UP -> lmul, 107 UopDivType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 108 UopDivType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 109 UopDivType.VEC_VRED -> lmul, 110 )) 111 112 val src1 = ctrl_flow.instr(19, 15) 113 val src2 = ctrl_flow.instr(24, 20) 114 val dest = ctrl_flow.instr(11, 7) 115 116 //uop div up to maxNumOfUop 117 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 118 csBundle.map { case dst => 119 dst := cf_ctrl_u 120 dst.ctrl.firstUop := false.B 121 dst.ctrl.lastUop := false.B 122 } 123 124 csBundle(0).ctrl.firstUop := true.B 125 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 126 127 switch(typeOfDiv) { 128 is(UopDivType.DIR) { 129 when(isVset_u) { 130 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR || ALUOpType.isVsetvl(cf_ctrl_u.ctrl.fuOpType) 131 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 132 csBundle(1).ctrl.ldest := INT_VCONFIG.U 133 csBundle(1).ctrl.flushPipe := false.B 134 } 135 } 136 is(UopDivType.VEC_VVV) { 137 for (i <- 0 until MAX_VLMUL) { 138 csBundle(i).ctrl.lsrc(0) := src1 + i.U 139 csBundle(i).ctrl.lsrc(1) := src2 + i.U 140 csBundle(i).ctrl.lsrc(2) := dest + i.U 141 csBundle(i).ctrl.ldest := dest + i.U 142 csBundle(i).ctrl.uopIdx := i.U 143 } 144 } 145 is(UopDivType.VEC_EXT2) { 146 for (i <- 0 until MAX_VLMUL / 2) { 147 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 148 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 149 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 150 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 151 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 152 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 153 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 154 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 155 } 156 } 157 is(UopDivType.VEC_EXT4) { 158 for (i <- 0 until MAX_VLMUL / 4) { 159 csBundle(4 * i).ctrl.lsrc(1) := src2 + i.U 160 csBundle(4 * i).ctrl.lsrc(2) := dest + (4 * i).U 161 csBundle(4 * i).ctrl.ldest := dest + (4 * i).U 162 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 163 csBundle(4 * i + 1).ctrl.lsrc(1) := src2 + i.U 164 csBundle(4 * i + 1).ctrl.lsrc(2) := dest + (4 * i + 1).U 165 csBundle(4 * i + 1).ctrl.ldest := dest + (4 * i + 1).U 166 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 167 csBundle(4 * i + 2).ctrl.lsrc(1) := src2 + i.U 168 csBundle(4 * i + 2).ctrl.lsrc(2) := dest + (4 * i + 2).U 169 csBundle(4 * i + 2).ctrl.ldest := dest + (4 * i + 2).U 170 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 171 csBundle(4 * i + 3).ctrl.lsrc(1) := src2 + i.U 172 csBundle(4 * i + 3).ctrl.lsrc(2) := dest + (4 * i + 3).U 173 csBundle(4 * i + 3).ctrl.ldest := dest + (4 * i + 3).U 174 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 175 } 176 } 177 is(UopDivType.VEC_EXT8) { 178 for (i <- 0 until MAX_VLMUL) { 179 csBundle(i).ctrl.lsrc(1) := src2 180 csBundle(i).ctrl.lsrc(2) := dest + i.U 181 csBundle(i).ctrl.ldest := dest + i.U 182 csBundle(i).ctrl.uopIdx := i.U 183 } 184 } 185 is(UopDivType.VEC_0XV) { 186 /* 187 FMV.D.X 188 */ 189 csBundle(0).ctrl.srcType(0) := SrcType.reg 190 csBundle(0).ctrl.srcType(1) := SrcType.imm 191 csBundle(0).ctrl.lsrc(1) := 0.U 192 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 193 csBundle(0).ctrl.fuType := FuType.i2f 194 csBundle(0).ctrl.rfWen := false.B 195 csBundle(0).ctrl.fpWen := true.B 196 csBundle(0).ctrl.vecWen := false.B 197 csBundle(0).ctrl.fpu.isAddSub := false.B 198 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 199 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 200 csBundle(0).ctrl.fpu.fromInt := true.B 201 csBundle(0).ctrl.fpu.wflags := false.B 202 csBundle(0).ctrl.fpu.fpWen := true.B 203 csBundle(0).ctrl.fpu.div := false.B 204 csBundle(0).ctrl.fpu.sqrt := false.B 205 csBundle(0).ctrl.fpu.fcvt := false.B 206 /* 207 vfmv.s.f 208 */ 209 csBundle(1).ctrl.srcType(0) := SrcType.fp 210 csBundle(1).ctrl.srcType(1) := SrcType.vp 211 csBundle(1).ctrl.srcType(2) := SrcType.vp 212 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 213 csBundle(1).ctrl.lsrc(1) := 0.U 214 csBundle(1).ctrl.lsrc(2) := dest 215 csBundle(1).ctrl.ldest := dest 216 csBundle(1).ctrl.fuType := FuType.vppu 217 csBundle(1).ctrl.fuOpType := VpermType.vfmv_s_f 218 csBundle(1).ctrl.rfWen := false.B 219 csBundle(1).ctrl.fpWen := false.B 220 csBundle(1).ctrl.vecWen := true.B 221 } 222 is(UopDivType.VEC_VXV) { 223 /* 224 FMV.D.X 225 */ 226 csBundle(0).ctrl.srcType(0) := SrcType.reg 227 csBundle(0).ctrl.srcType(1) := SrcType.imm 228 csBundle(0).ctrl.lsrc(1) := 0.U 229 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 230 csBundle(0).ctrl.fuType := FuType.i2f 231 csBundle(0).ctrl.rfWen := false.B 232 csBundle(0).ctrl.fpWen := true.B 233 csBundle(0).ctrl.vecWen := false.B 234 csBundle(0).ctrl.fpu.isAddSub := false.B 235 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 236 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 237 csBundle(0).ctrl.fpu.fromInt := true.B 238 csBundle(0).ctrl.fpu.wflags := false.B 239 csBundle(0).ctrl.fpu.fpWen := true.B 240 csBundle(0).ctrl.fpu.div := false.B 241 csBundle(0).ctrl.fpu.sqrt := false.B 242 csBundle(0).ctrl.fpu.fcvt := false.B 243 /* 244 LMUL 245 */ 246 for (i <- 0 until MAX_VLMUL) { 247 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 248 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 249 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 250 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 251 csBundle(i + 1).ctrl.ldest := dest + i.U 252 csBundle(i + 1).ctrl.uopIdx := i.U 253 } 254 } 255 is(UopDivType.VEC_VVW) { 256 for (i <- 0 until MAX_VLMUL / 2) { 257 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 258 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 259 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 260 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 261 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 262 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 263 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 264 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 265 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 266 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 267 } 268 } 269 is(UopDivType.VEC_WVW) { 270 for (i <- 0 until MAX_VLMUL / 2) { 271 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 272 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 273 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 274 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 275 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 276 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 277 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 278 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 279 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 280 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 281 } 282 } 283 is(UopDivType.VEC_VXW) { 284 /* 285 FMV.D.X 286 */ 287 csBundle(0).ctrl.srcType(0) := SrcType.reg 288 csBundle(0).ctrl.srcType(1) := SrcType.imm 289 csBundle(0).ctrl.lsrc(1) := 0.U 290 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 291 csBundle(0).ctrl.fuType := FuType.i2f 292 csBundle(0).ctrl.rfWen := false.B 293 csBundle(0).ctrl.fpWen := true.B 294 csBundle(0).ctrl.vecWen := false.B 295 csBundle(0).ctrl.fpu.isAddSub := false.B 296 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 297 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 298 csBundle(0).ctrl.fpu.fromInt := true.B 299 csBundle(0).ctrl.fpu.wflags := false.B 300 csBundle(0).ctrl.fpu.fpWen := true.B 301 csBundle(0).ctrl.fpu.div := false.B 302 csBundle(0).ctrl.fpu.sqrt := false.B 303 csBundle(0).ctrl.fpu.fcvt := false.B 304 305 for (i <- 0 until MAX_VLMUL / 2) { 306 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 307 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 308 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 309 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 310 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 311 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 312 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 313 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 314 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U 315 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 316 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 317 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 318 } 319 } 320 is(UopDivType.VEC_WXW) { 321 /* 322 FMV.D.X 323 */ 324 csBundle(0).ctrl.srcType(0) := SrcType.reg 325 csBundle(0).ctrl.srcType(1) := SrcType.imm 326 csBundle(0).ctrl.lsrc(1) := 0.U 327 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 328 csBundle(0).ctrl.fuType := FuType.i2f 329 csBundle(0).ctrl.rfWen := false.B 330 csBundle(0).ctrl.fpWen := true.B 331 csBundle(0).ctrl.vecWen := false.B 332 csBundle(0).ctrl.fpu.isAddSub := false.B 333 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 334 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 335 csBundle(0).ctrl.fpu.fromInt := true.B 336 csBundle(0).ctrl.fpu.wflags := false.B 337 csBundle(0).ctrl.fpu.fpWen := true.B 338 csBundle(0).ctrl.fpu.div := false.B 339 csBundle(0).ctrl.fpu.sqrt := false.B 340 csBundle(0).ctrl.fpu.fcvt := false.B 341 342 for (i <- 0 until MAX_VLMUL / 2) { 343 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 344 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 345 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 346 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 347 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 348 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 349 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 350 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 351 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 352 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 353 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 354 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 355 } 356 } 357 is(UopDivType.VEC_WVV) { 358 for (i <- 0 until MAX_VLMUL / 2) { 359 360 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 361 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 362 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 363 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 364 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 365 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 366 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 367 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 368 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 369 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 370 } 371 } 372 is(UopDivType.VEC_WXV) { 373 /* 374 FMV.D.X 375 */ 376 csBundle(0).ctrl.srcType(0) := SrcType.reg 377 csBundle(0).ctrl.srcType(1) := SrcType.imm 378 csBundle(0).ctrl.lsrc(1) := 0.U 379 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 380 csBundle(0).ctrl.fuType := FuType.i2f 381 csBundle(0).ctrl.rfWen := false.B 382 csBundle(0).ctrl.fpWen := true.B 383 csBundle(0).ctrl.vecWen := false.B 384 csBundle(0).ctrl.fpu.isAddSub := false.B 385 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 386 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 387 csBundle(0).ctrl.fpu.fromInt := true.B 388 csBundle(0).ctrl.fpu.wflags := false.B 389 csBundle(0).ctrl.fpu.fpWen := true.B 390 csBundle(0).ctrl.fpu.div := false.B 391 csBundle(0).ctrl.fpu.sqrt := false.B 392 csBundle(0).ctrl.fpu.fcvt := false.B 393 394 for (i <- 0 until MAX_VLMUL / 2) { 395 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 396 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 397 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 398 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 399 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 400 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 401 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 402 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 403 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 404 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 405 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 406 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 407 } 408 } 409 is(UopDivType.VEC_VVM) { 410 csBundle(0).ctrl.lsrc(2) := dest 411 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 412 csBundle(0).ctrl.uopIdx := 0.U 413 for(i <- 1 until MAX_VLMUL) { 414 csBundle(i).ctrl.lsrc(0) := src1 + i.U 415 csBundle(i).ctrl.lsrc(1) := src2 + i.U 416 csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 417 csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 418 csBundle(i).ctrl.uopIdx := i.U 419 } 420 csBundle(numOfUop - 1.U).ctrl.ldest := dest 421 } 422 is(UopDivType.VEC_VXM) { 423 /* 424 FMV.D.X 425 */ 426 csBundle(0).ctrl.srcType(0) := SrcType.reg 427 csBundle(0).ctrl.srcType(1) := SrcType.imm 428 csBundle(0).ctrl.lsrc(1) := 0.U 429 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 430 csBundle(0).ctrl.fuType := FuType.i2f 431 csBundle(0).ctrl.rfWen := false.B 432 csBundle(0).ctrl.fpWen := true.B 433 csBundle(0).ctrl.vecWen := false.B 434 csBundle(0).ctrl.fpu.isAddSub := false.B 435 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 436 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 437 csBundle(0).ctrl.fpu.fromInt := true.B 438 csBundle(0).ctrl.fpu.wflags := false.B 439 csBundle(0).ctrl.fpu.fpWen := true.B 440 csBundle(0).ctrl.fpu.div := false.B 441 csBundle(0).ctrl.fpu.sqrt := false.B 442 csBundle(0).ctrl.fpu.fcvt := false.B 443 //LMUL 444 csBundle(1).ctrl.srcType(0) := SrcType.fp 445 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 446 csBundle(1).ctrl.lsrc(2) := dest 447 csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 448 csBundle(1).ctrl.uopIdx := 0.U 449 for (i <- 1 until MAX_VLMUL) { 450 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 451 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 452 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 453 csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 454 csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 455 csBundle(i + 1).ctrl.uopIdx := i.U 456 } 457 csBundle(numOfUop - 1.U).ctrl.ldest := dest 458 } 459 is(UopDivType.VEC_SLIDE1UP) { 460 /* 461 FMV.D.X 462 */ 463 csBundle(0).ctrl.srcType(0) := SrcType.reg 464 csBundle(0).ctrl.srcType(1) := SrcType.imm 465 csBundle(0).ctrl.lsrc(1) := 0.U 466 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 467 csBundle(0).ctrl.fuType := FuType.i2f 468 csBundle(0).ctrl.rfWen := false.B 469 csBundle(0).ctrl.fpWen := true.B 470 csBundle(0).ctrl.vecWen := false.B 471 csBundle(0).ctrl.fpu.isAddSub := false.B 472 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 473 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 474 csBundle(0).ctrl.fpu.fromInt := true.B 475 csBundle(0).ctrl.fpu.wflags := false.B 476 csBundle(0).ctrl.fpu.fpWen := true.B 477 csBundle(0).ctrl.fpu.div := false.B 478 csBundle(0).ctrl.fpu.sqrt := false.B 479 csBundle(0).ctrl.fpu.fcvt := false.B 480 //LMUL 481 csBundle(1).ctrl.srcType(0) := SrcType.fp 482 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 483 csBundle(1).ctrl.lsrc(2) := dest 484 csBundle(1).ctrl.ldest := dest 485 csBundle(1).ctrl.uopIdx := 0.U 486 for (i <- 1 until MAX_VLMUL) { 487 csBundle(i + 1).ctrl.srcType(0) := SrcType.vp 488 csBundle(i + 1).ctrl.lsrc(0) := src2 + (i - 1).U 489 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 490 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 491 csBundle(i + 1).ctrl.ldest := dest + i.U 492 csBundle(i + 1).ctrl.uopIdx := i.U 493 } 494 } 495 is(UopDivType.VEC_FSLIDE1UP) { 496 //LMUL 497 csBundle(0).ctrl.srcType(0) := SrcType.fp 498 csBundle(0).ctrl.lsrc(0) := src1 499 csBundle(0).ctrl.lsrc(1) := src2 500 csBundle(0).ctrl.lsrc(2) := dest 501 csBundle(0).ctrl.ldest := dest 502 csBundle(0).ctrl.uopIdx := 0.U 503 for (i <- 1 until MAX_VLMUL) { 504 csBundle(i).ctrl.srcType(0) := SrcType.vp 505 csBundle(i).ctrl.lsrc(0) := src2 + (i - 1).U 506 csBundle(i).ctrl.lsrc(1) := src2 + i.U 507 csBundle(i).ctrl.lsrc(2) := dest + i.U 508 csBundle(i).ctrl.ldest := dest + i.U 509 csBundle(i).ctrl.uopIdx := i.U 510 } 511 } 512 is(UopDivType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 513 /* 514 FMV.D.X 515 */ 516 csBundle(0).ctrl.srcType(0) := SrcType.reg 517 csBundle(0).ctrl.srcType(1) := SrcType.imm 518 csBundle(0).ctrl.lsrc(1) := 0.U 519 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 520 csBundle(0).ctrl.fuType := FuType.i2f 521 csBundle(0).ctrl.rfWen := false.B 522 csBundle(0).ctrl.fpWen := true.B 523 csBundle(0).ctrl.vecWen := false.B 524 csBundle(0).ctrl.fpu.isAddSub := false.B 525 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 526 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 527 csBundle(0).ctrl.fpu.fromInt := true.B 528 csBundle(0).ctrl.fpu.wflags := false.B 529 csBundle(0).ctrl.fpu.fpWen := true.B 530 csBundle(0).ctrl.fpu.div := false.B 531 csBundle(0).ctrl.fpu.sqrt := false.B 532 csBundle(0).ctrl.fpu.fcvt := false.B 533 //LMUL 534 for (i <- 0 until MAX_VLMUL) { 535 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp 536 csBundle(2 * i + 1).ctrl.srcType(1) := SrcType.vp 537 csBundle(2 * i + 1).ctrl.lsrc(0) := src2 + (i+1).U 538 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 539 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 540 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 541 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 542 if (2 * i + 2 < MAX_VLMUL * 2 ){ 543 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 544 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 545 // csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U // DontCare 546 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 547 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 548 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 549 } 550 } 551 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 552 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := FP_TMP_REG_MV.U 553 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 554 } 555 is(UopDivType.VEC_FSLIDE1DOWN) { 556 //LMUL 557 for (i <- 0 until MAX_VLMUL) { 558 csBundle(2 * i).ctrl.srcType(0) := SrcType.vp 559 csBundle(2 * i).ctrl.srcType(1) := SrcType.vp 560 csBundle(2 * i).ctrl.lsrc(0) := src2 + (i+1).U 561 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 562 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 563 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 564 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 565 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 566 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 567 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 568 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 569 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 570 } 571 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 572 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1 573 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 574 } 575 is(UopDivType.VEC_VRED) { 576 when(simple.io.vconfig.vtype.vlmul === "b001".U){ 577 csBundle(0).ctrl.srcType(2) := SrcType.DC 578 csBundle(0).ctrl.lsrc(0) := src2 + 1.U 579 csBundle(0).ctrl.lsrc(1) := src2 580 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 581 csBundle(0).ctrl.uopIdx := 0.U 582 } 583 when(simple.io.vconfig.vtype.vlmul === "b010".U) { 584 csBundle(0).ctrl.srcType(2) := SrcType.DC 585 csBundle(0).ctrl.lsrc(0) := src2 + 1.U 586 csBundle(0).ctrl.lsrc(1) := src2 587 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 588 csBundle(0).ctrl.uopIdx := 0.U 589 590 csBundle(1).ctrl.srcType(2) := SrcType.DC 591 csBundle(1).ctrl.lsrc(0) := src2 + 3.U 592 csBundle(1).ctrl.lsrc(1) := src2 + 2.U 593 csBundle(1).ctrl.ldest := (VECTOR_TMP_REG_LMUL+1).U 594 csBundle(1).ctrl.uopIdx := 1.U 595 596 csBundle(2).ctrl.srcType(2) := SrcType.DC 597 csBundle(2).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL+1).U 598 csBundle(2).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U 599 csBundle(2).ctrl.ldest := (VECTOR_TMP_REG_LMUL+2).U 600 csBundle(2).ctrl.uopIdx := 2.U 601 } 602 when(simple.io.vconfig.vtype.vlmul === "b011".U) { 603 for(i <- 0 until MAX_VLMUL){ 604 if(i < MAX_VLMUL - MAX_VLMUL/2){ 605 csBundle(i).ctrl.lsrc(0) := src2 + (i * 2 + 1).U 606 csBundle(i).ctrl.lsrc(1) := src2 + (i * 2).U 607 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 608 } else if (i < MAX_VLMUL - MAX_VLMUL/4) { 609 csBundle(i).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2 + 1).U 610 csBundle(i).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2).U 611 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 612 }else if (i < MAX_VLMUL - MAX_VLMUL/8) { 613 csBundle(6).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 614 csBundle(6).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 615 csBundle(6).ctrl.ldest := (VECTOR_TMP_REG_LMUL + 6).U 616 } 617 csBundle(i).ctrl.srcType(2) := SrcType.DC 618 csBundle(i).ctrl.uopIdx := i.U 619 } 620 } 621 when (simple.io.vconfig.vtype.vlmul.orR()){ 622 csBundle(numOfUop - 1.U).ctrl.srcType(2) := SrcType.vp 623 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1 624 csBundle(numOfUop - 1.U).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 625 csBundle(numOfUop - 1.U).ctrl.lsrc(2) := dest 626 csBundle(numOfUop - 1.U).ctrl.ldest := dest 627 csBundle(numOfUop - 1.U).ctrl.uopIdx := numOfUop - 1.U 628 } 629 } 630 } 631 632 //uops dispatch 633 val normal :: ext :: Nil = Enum(2) 634 val stateReg = RegInit(normal) 635 val uopRes = RegInit(0.U) 636 637 //readyFromRename Counter 638 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 639 640 switch(stateReg) { 641 is(normal) { 642 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 643 } 644 is(ext) { 645 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 646 } 647 } 648 649 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 650 val uopResJudge = Mux(stateReg === normal, 651 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 652 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 653 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 654 655 for(i <- 0 until RenameWidth) { 656 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 657 (stateReg === normal) -> csBundle(i), 658 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 659 )) 660 } 661 662 663 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 664 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 665 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 666 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 667 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 668 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 669 notInfVec(0) := true.B 670 671 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 672 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 673 1.U) 674 validToRename.zipWithIndex.foreach{ 675 case(dst, i) => 676 dst := MuxCase(false.B, Seq( 677 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 678 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 679 )) 680 } 681 682 readyToIBuf.zipWithIndex.foreach { 683 case (dst, i) => 684 dst := MuxCase(true.B, Seq( 685 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 686 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 687 )) 688 } 689 690 io.deq.cf_ctrl := cf_ctrl 691 io.deq.isVset := isVset_u 692 io.deq.complexNum := complexNum 693 io.deq.validToRename := validToRename 694 io.deq.readyToIBuf := readyToIBuf 695 696} 697 698