1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VppuType 31import scala.collection.Seq 32 33trait VectorConstants { 34 val MAX_VLMUL = 8 35 val INT_VCONFIG = 32 36 val FP_TMP_REG_MV = 32 37 val VECTOR_TMP_REG_LMUL = 32 38} 39 40class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 41 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 42 val vconfig = Input(new VConfig) 43 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 44 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 45 val readyFromRename = Input(Vec(RenameWidth, Bool())) 46 val deq = new Bundle { 47 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 48 val isVset = Output(Bool()) 49 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 50 val validToRename = Output(Vec(RenameWidth, Bool())) 51 val complexNum = Output(UInt(3.W)) 52 } 53 val csrCtrl = Input(new CustomCSRCtrlIO) 54} 55 56class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 57 val io = IO(new DecodeUnitCompIO) 58 //input bits 59 val ctrl_flow = Wire(new CtrlFlow) 60 ctrl_flow := io.enq.ctrl_flow 61 //output bits 62 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 63 val validToRename = Wire(Vec(RenameWidth, Bool())) 64 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 65 val complexNum = Wire(UInt(3.W)) 66 67 //output of DecodeUnit 68 val cf_ctrl_u = Wire(new CfCtrl) 69 val isVset_u = Wire(Bool()) 70 71 //pre decode 72 val simple = Module(new DecodeUnit) 73 simple.io.enq.ctrl_flow := ctrl_flow 74 simple.io.vconfig := io.vconfig 75 simple.io.csrCtrl := io.csrCtrl 76 cf_ctrl_u := simple.io.deq.cf_ctrl 77 isVset_u := simple.io.deq.isVset 78 79 //Type of uop Div 80 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 81 82 //LMUL 83 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U, Array( 84 "b001".U -> 2.U, 85 "b010".U -> 4.U, 86 "b011".U -> 8.U 87 )) 88 //number of uop 89 val numOfUop = MuxLookup(typeOfDiv, 1.U, Array( 90 UopDivType.VEC_0XV -> 2.U, 91 UopDivType.DIR -> 2.U, 92 UopDivType.VEC_VVV -> lmul, 93 UopDivType.VEC_EXT2 -> lmul, 94 UopDivType.VEC_EXT4 -> lmul, 95 UopDivType.VEC_EXT8 -> lmul, 96 UopDivType.VEC_VVM -> lmul, 97 UopDivType.VEC_VXM -> (lmul + 1.U), 98 UopDivType.VEC_VXV -> (lmul + 1.U), 99 UopDivType.VEC_VVW -> (lmul + lmul), // lmul <= 4 100 UopDivType.VEC_WVW -> (lmul + lmul), // lmul <= 4 101 UopDivType.VEC_VXW -> (lmul + lmul + 1.U), // lmul <= 4 102 UopDivType.VEC_WXW -> (lmul + lmul + 1.U), // lmul <= 4 103 UopDivType.VEC_WVV -> (lmul + lmul), // lmul <= 4 104 UopDivType.VEC_WXV -> (lmul + lmul + 1.U), // lmul <= 4 105 UopDivType.VEC_SLIDE1UP -> (lmul + 1.U) 106 )) 107 108 val src1 = ctrl_flow.instr(19, 15) 109 val src2 = ctrl_flow.instr(24, 20) 110 val dest = ctrl_flow.instr(11, 7) 111 112 //uop div up to maxNumOfUop 113 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 114 csBundle.map { case dst => 115 dst := cf_ctrl_u 116 dst.ctrl.firstUop := false.B 117 dst.ctrl.lastUop := false.B 118 } 119 120 csBundle(0).ctrl.firstUop := true.B 121 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 122 123 switch(typeOfDiv) { 124 is(UopDivType.DIR) { 125 when(isVset_u) { 126 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR 127 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 128 csBundle(1).ctrl.ldest := INT_VCONFIG.U 129 csBundle(1).ctrl.flushPipe := false.B 130 } 131 } 132 is(UopDivType.VEC_VVV) { 133 for (i <- 0 until MAX_VLMUL) { 134 csBundle(i).ctrl.lsrc(0) := src1 + i.U 135 csBundle(i).ctrl.lsrc(1) := src2 + i.U 136 csBundle(i).ctrl.ldest := dest + i.U 137 csBundle(i).ctrl.uopIdx := i.U 138 } 139 } 140 is(UopDivType.VEC_EXT2) { 141 for (i <- 0 until MAX_VLMUL / 2) { 142 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 143 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 144 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 145 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 146 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 147 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 148 } 149 } 150 is(UopDivType.VEC_EXT4) { 151 for (i <- 0 until MAX_VLMUL / 4) { 152 csBundle(4 * i).ctrl.lsrc(1) := src2 + i.U 153 csBundle(4 * i).ctrl.ldest := dest + (4 * i).U 154 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 155 csBundle(4 * i + 1).ctrl.lsrc(1) := src2 + i.U 156 csBundle(4 * i + 1).ctrl.ldest := dest + (4 * i + 1).U 157 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 158 csBundle(4 * i + 2).ctrl.lsrc(1) := src2 + i.U 159 csBundle(4 * i + 2).ctrl.ldest := dest + (4 * i + 2).U 160 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 161 csBundle(4 * i + 3).ctrl.lsrc(1) := src2 + i.U 162 csBundle(4 * i + 3).ctrl.ldest := dest + (4 * i + 3).U 163 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 164 } 165 } 166 is(UopDivType.VEC_EXT8) { 167 for (i <- 0 until MAX_VLMUL) { 168 csBundle(i).ctrl.lsrc(1) := src2 169 csBundle(i).ctrl.ldest := dest + i.U 170 csBundle(i).ctrl.uopIdx := i.U 171 } 172 } 173 is(UopDivType.VEC_0XV) { 174 /* 175 FMV.D.X 176 */ 177 csBundle(0).ctrl.srcType(0) := SrcType.reg 178 csBundle(0).ctrl.srcType(1) := SrcType.imm 179 csBundle(0).ctrl.lsrc(1) := 0.U 180 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 181 csBundle(0).ctrl.fuType := FuType.i2f 182 csBundle(0).ctrl.rfWen := false.B 183 csBundle(0).ctrl.fpWen := true.B 184 csBundle(0).ctrl.vecWen := false.B 185 csBundle(0).ctrl.fpu.isAddSub := false.B 186 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 187 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 188 csBundle(0).ctrl.fpu.fromInt := true.B 189 csBundle(0).ctrl.fpu.wflags := false.B 190 csBundle(0).ctrl.fpu.fpWen := true.B 191 csBundle(0).ctrl.fpu.div := false.B 192 csBundle(0).ctrl.fpu.sqrt := false.B 193 csBundle(0).ctrl.fpu.fcvt := false.B 194 /* 195 vfmv.s.f 196 */ 197 csBundle(1).ctrl.srcType(0) := SrcType.fp 198 csBundle(1).ctrl.srcType(1) := SrcType.vp 199 csBundle(1).ctrl.srcType(2) := SrcType.vp 200 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 201 csBundle(1).ctrl.lsrc(1) := 0.U 202 csBundle(1).ctrl.lsrc(2) := dest 203 csBundle(1).ctrl.ldest := dest 204 csBundle(1).ctrl.fuType := FuType.vppu 205 csBundle(1).ctrl.fuOpType := VppuType.f2s 206 csBundle(1).ctrl.rfWen := false.B 207 csBundle(1).ctrl.fpWen := false.B 208 csBundle(1).ctrl.vecWen := true.B 209 } 210 is(UopDivType.VEC_VXV) { 211 /* 212 FMV.D.X 213 */ 214 csBundle(0).ctrl.srcType(0) := SrcType.reg 215 csBundle(0).ctrl.srcType(1) := SrcType.imm 216 csBundle(0).ctrl.lsrc(1) := 0.U 217 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 218 csBundle(0).ctrl.fuType := FuType.i2f 219 csBundle(0).ctrl.rfWen := false.B 220 csBundle(0).ctrl.fpWen := true.B 221 csBundle(0).ctrl.vecWen := false.B 222 csBundle(0).ctrl.fpu.isAddSub := false.B 223 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 224 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 225 csBundle(0).ctrl.fpu.fromInt := true.B 226 csBundle(0).ctrl.fpu.wflags := false.B 227 csBundle(0).ctrl.fpu.fpWen := true.B 228 csBundle(0).ctrl.fpu.div := false.B 229 csBundle(0).ctrl.fpu.sqrt := false.B 230 csBundle(0).ctrl.fpu.fcvt := false.B 231 /* 232 LMUL 233 */ 234 for (i <- 0 until MAX_VLMUL) { 235 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 236 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 237 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 238 csBundle(i + 1).ctrl.ldest := dest + i.U 239 csBundle(i + 1).ctrl.uopIdx := i.U 240 } 241 } 242 is(UopDivType.VEC_VVW) { 243 for (i <- 0 until MAX_VLMUL / 2) { 244 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 245 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 246 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 247 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 248 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 249 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 250 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 251 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 252 } 253 } 254 is(UopDivType.VEC_WVW) { 255 for (i <- 0 until MAX_VLMUL / 2) { 256 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 257 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 258 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 259 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 260 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 261 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 262 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 263 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 264 } 265 } 266 is(UopDivType.VEC_VXW) { 267 /* 268 FMV.D.X 269 */ 270 csBundle(0).ctrl.srcType(0) := SrcType.reg 271 csBundle(0).ctrl.srcType(1) := SrcType.imm 272 csBundle(0).ctrl.lsrc(1) := 0.U 273 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 274 csBundle(0).ctrl.fuType := FuType.i2f 275 csBundle(0).ctrl.rfWen := false.B 276 csBundle(0).ctrl.fpWen := true.B 277 csBundle(0).ctrl.vecWen := false.B 278 csBundle(0).ctrl.fpu.isAddSub := false.B 279 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 280 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 281 csBundle(0).ctrl.fpu.fromInt := true.B 282 csBundle(0).ctrl.fpu.wflags := false.B 283 csBundle(0).ctrl.fpu.fpWen := true.B 284 csBundle(0).ctrl.fpu.div := false.B 285 csBundle(0).ctrl.fpu.sqrt := false.B 286 csBundle(0).ctrl.fpu.fcvt := false.B 287 288 for (i <- 0 until MAX_VLMUL / 2) { 289 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 290 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 291 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 292 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 293 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 294 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 295 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 296 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U 297 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 298 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 299 } 300 } 301 is(UopDivType.VEC_WXW) { 302 /* 303 FMV.D.X 304 */ 305 csBundle(0).ctrl.srcType(0) := SrcType.reg 306 csBundle(0).ctrl.srcType(1) := SrcType.imm 307 csBundle(0).ctrl.lsrc(1) := 0.U 308 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 309 csBundle(0).ctrl.fuType := FuType.i2f 310 csBundle(0).ctrl.rfWen := false.B 311 csBundle(0).ctrl.fpWen := true.B 312 csBundle(0).ctrl.vecWen := false.B 313 csBundle(0).ctrl.fpu.isAddSub := false.B 314 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 315 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 316 csBundle(0).ctrl.fpu.fromInt := true.B 317 csBundle(0).ctrl.fpu.wflags := false.B 318 csBundle(0).ctrl.fpu.fpWen := true.B 319 csBundle(0).ctrl.fpu.div := false.B 320 csBundle(0).ctrl.fpu.sqrt := false.B 321 csBundle(0).ctrl.fpu.fcvt := false.B 322 323 for (i <- 0 until MAX_VLMUL / 2) { 324 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 325 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 326 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 327 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 328 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 329 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 330 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 331 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 332 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 333 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 334 } 335 } 336 is(UopDivType.VEC_WVV) { 337 for (i <- 0 until MAX_VLMUL / 2) { 338 339 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 340 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 341 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 342 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 343 csBundle(2 * i + 1).ctrl.srcType(2) := SrcType.vp 344 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 345 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 346 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 347 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 348 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 349 } 350 } 351 is(UopDivType.VEC_WXV) { 352 /* 353 FMV.D.X 354 */ 355 csBundle(0).ctrl.srcType(0) := SrcType.reg 356 csBundle(0).ctrl.srcType(1) := SrcType.imm 357 csBundle(0).ctrl.lsrc(1) := 0.U 358 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 359 csBundle(0).ctrl.fuType := FuType.i2f 360 csBundle(0).ctrl.rfWen := false.B 361 csBundle(0).ctrl.fpWen := true.B 362 csBundle(0).ctrl.vecWen := false.B 363 csBundle(0).ctrl.fpu.isAddSub := false.B 364 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 365 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 366 csBundle(0).ctrl.fpu.fromInt := true.B 367 csBundle(0).ctrl.fpu.wflags := false.B 368 csBundle(0).ctrl.fpu.fpWen := true.B 369 csBundle(0).ctrl.fpu.div := false.B 370 csBundle(0).ctrl.fpu.sqrt := false.B 371 csBundle(0).ctrl.fpu.fcvt := false.B 372 373 for (i <- 0 until MAX_VLMUL / 2) { 374 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 375 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 376 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 377 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 378 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 379 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 380 csBundle(2 * i + 2).ctrl.srcType(2) := SrcType.vp 381 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 382 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 383 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 384 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 385 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 386 } 387 } 388 is(UopDivType.VEC_VVM) { 389 csBundle(0).ctrl.srcType(2) := SrcType.vp 390 csBundle(0).ctrl.lsrc(2) := dest 391 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 392 csBundle(0).ctrl.uopIdx := 0.U 393 for(i <- 1 until MAX_VLMUL) { 394 csBundle(i).ctrl.srcType(2) := SrcType.vp 395 csBundle(i).ctrl.lsrc(0) := src1 + i.U 396 csBundle(i).ctrl.lsrc(1) := src2 + i.U 397 csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 398 csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 399 csBundle(i).ctrl.uopIdx := i.U 400 } 401 csBundle(numOfUop - 1.U).ctrl.ldest := dest 402 } 403 is(UopDivType.VEC_VXM) { 404 /* 405 FMV.D.X 406 */ 407 csBundle(0).ctrl.srcType(0) := SrcType.reg 408 csBundle(0).ctrl.srcType(1) := SrcType.imm 409 csBundle(0).ctrl.lsrc(1) := 0.U 410 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 411 csBundle(0).ctrl.fuType := FuType.i2f 412 csBundle(0).ctrl.rfWen := false.B 413 csBundle(0).ctrl.fpWen := true.B 414 csBundle(0).ctrl.vecWen := false.B 415 csBundle(0).ctrl.fpu.isAddSub := false.B 416 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 417 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 418 csBundle(0).ctrl.fpu.fromInt := true.B 419 csBundle(0).ctrl.fpu.wflags := false.B 420 csBundle(0).ctrl.fpu.fpWen := true.B 421 csBundle(0).ctrl.fpu.div := false.B 422 csBundle(0).ctrl.fpu.sqrt := false.B 423 csBundle(0).ctrl.fpu.fcvt := false.B 424 //LMUL 425 csBundle(1).ctrl.srcType(0) := SrcType.fp 426 csBundle(1).ctrl.srcType(2) := SrcType.vp 427 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 428 csBundle(1).ctrl.lsrc(2) := dest 429 csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 430 csBundle(1).ctrl.uopIdx := 0.U 431 for (i <- 1 until MAX_VLMUL) { 432 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 433 csBundle(i + 1).ctrl.srcType(2) := SrcType.vp 434 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 435 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 436 csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 437 csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 438 csBundle(i + 1).ctrl.uopIdx := i.U 439 } 440 csBundle(numOfUop - 1.U).ctrl.ldest := dest 441 } 442 is(UopDivType.VEC_SLIDE1UP) { 443 /* 444 FMV.D.X 445 */ 446 csBundle(0).ctrl.srcType(0) := SrcType.reg 447 csBundle(0).ctrl.srcType(1) := SrcType.imm 448 csBundle(0).ctrl.lsrc(1) := 0.U 449 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 450 csBundle(0).ctrl.fuType := FuType.i2f 451 csBundle(0).ctrl.rfWen := false.B 452 csBundle(0).ctrl.fpWen := true.B 453 csBundle(0).ctrl.vecWen := false.B 454 csBundle(0).ctrl.fpu.isAddSub := false.B 455 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 456 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 457 csBundle(0).ctrl.fpu.fromInt := true.B 458 csBundle(0).ctrl.fpu.wflags := false.B 459 csBundle(0).ctrl.fpu.fpWen := true.B 460 csBundle(0).ctrl.fpu.div := false.B 461 csBundle(0).ctrl.fpu.sqrt := false.B 462 csBundle(0).ctrl.fpu.fcvt := false.B 463 //LMUL 464 csBundle(1).ctrl.srcType(0) := SrcType.fp 465 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 466 csBundle(1).ctrl.lsrc(2) := dest 467 csBundle(1).ctrl.ldest := dest 468 csBundle(1).ctrl.uopIdx := 0.U 469 for (i <- 1 until MAX_VLMUL) { 470 csBundle(i + 1).ctrl.srcType(0) := SrcType.vp 471 csBundle(i + 1).ctrl.lsrc(0) := src2 + (i - 1).U 472 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 473 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 474 csBundle(i + 1).ctrl.ldest := dest + i.U 475 csBundle(i + 1).ctrl.uopIdx := i.U 476 } 477 } 478 } 479 480 //uops dispatch 481 val normal :: ext :: Nil = Enum(2) 482 val stateReg = RegInit(normal) 483 val uopRes = RegInit(0.U) 484 485 //readyFromRename Counter 486 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 487 488 switch(stateReg) { 489 is(normal) { 490 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 491 } 492 is(ext) { 493 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 494 } 495 } 496 497 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 498 val uopResJudge = Mux(stateReg === normal, 499 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 500 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 501 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 502 503 for(i <- 0 until RenameWidth) { 504 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 505 (stateReg === normal) -> csBundle(i), 506 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 507 )) 508 } 509 510 511 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 512 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 513 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 514 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 515 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 516 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 517 notInfVec(0) := true.B 518 519 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 520 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 521 1.U) 522 validToRename.zipWithIndex.foreach{ 523 case(dst, i) => 524 dst := MuxCase(false.B, Seq( 525 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 526 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 527 )) 528 } 529 530 readyToIBuf.zipWithIndex.foreach { 531 case (dst, i) => 532 dst := MuxCase(true.B, Seq( 533 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 534 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 535 )) 536 } 537 538 io.deq.cf_ctrl := cf_ctrl 539 io.deq.isVset := isVset_u 540 io.deq.complexNum := complexNum 541 io.deq.validToRename := validToRename 542 io.deq.readyToIBuf := readyToIBuf 543 544} 545 546