1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VpermType 31import scala.collection.Seq 32 33trait VectorConstants { 34 val MAX_VLMUL = 8 35 val INT_VCONFIG = 32 36 val FP_TMP_REG_MV = 32 37 val VECTOR_TMP_REG_LMUL = 32 // 32~46 -> 15 38} 39 40class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 41 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 42 val vconfig = Input(new VConfig) 43 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 44 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 45 val readyFromRename = Input(Vec(RenameWidth, Bool())) 46 val deq = new Bundle { 47 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 48 val isVset = Output(Bool()) 49 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 50 val validToRename = Output(Vec(RenameWidth, Bool())) 51 val complexNum = Output(UInt(3.W)) 52 } 53 val csrCtrl = Input(new CustomCSRCtrlIO) 54} 55 56class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 57 val io = IO(new DecodeUnitCompIO) 58 //input bits 59 val ctrl_flow = Wire(new CtrlFlow) 60 ctrl_flow := io.enq.ctrl_flow 61 //output bits 62 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 63 val validToRename = Wire(Vec(RenameWidth, Bool())) 64 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 65 val complexNum = Wire(UInt(3.W)) 66 67 //output of DecodeUnit 68 val cf_ctrl_u = Wire(new CfCtrl) 69 val isVset_u = Wire(Bool()) 70 71 //pre decode 72 val simple = Module(new DecodeUnit) 73 simple.io.enq.ctrl_flow := ctrl_flow 74 simple.io.vconfig := io.vconfig 75 simple.io.csrCtrl := io.csrCtrl 76 cf_ctrl_u := simple.io.deq.cf_ctrl 77 isVset_u := simple.io.deq.isVset 78 79 //Type of uop Div 80 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 81 82 //LMUL 83 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(4.W), Array( 84 "b001".U -> 2.U, 85 "b010".U -> 4.U, 86 "b011".U -> 8.U 87 )) 88 val numOfUopVslide = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(log2Up(maxNumOfUop+1).W), Array( 89 "b001".U -> 3.U, 90 "b010".U -> 10.U, 91 "b011".U -> 36.U 92 )) 93 //number of uop 94 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxNumOfUop+1).W), Array( 95 UopDivType.VEC_0XV -> 2.U, 96 UopDivType.DIR -> 2.U, 97 UopDivType.VEC_VVV -> lmul, 98 UopDivType.VEC_EXT2 -> lmul, 99 UopDivType.VEC_EXT4 -> lmul, 100 UopDivType.VEC_EXT8 -> lmul, 101 UopDivType.VEC_VVM -> lmul, 102 UopDivType.VEC_VXM -> (lmul +& 1.U), 103 UopDivType.VEC_VXV -> (lmul +& 1.U), 104 UopDivType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 105 UopDivType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 106 UopDivType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 107 UopDivType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 108 UopDivType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 109 UopDivType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 110 UopDivType.VEC_SLIDE1UP -> (lmul +& 1.U), 111 UopDivType.VEC_FSLIDE1UP -> lmul, 112 UopDivType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 113 UopDivType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 114 UopDivType.VEC_VRED -> lmul, 115 UopDivType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 116 UopDivType.VEC_ISLIDEUP -> numOfUopVslide, 117 UopDivType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 118 UopDivType.VEC_ISLIDEDOWN -> numOfUopVslide, 119 UopDivType.VEC_M0X -> (lmul +& 1.U), 120 UopDivType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) -1.U), 121 UopDivType.VEC_M0X_VFIRST -> 2.U, 122 UopDivType.VEC_VWW -> Cat(lmul, 0.U(1.W)), 123 )) 124 125 val src1 = Cat(0.U(1.W), ctrl_flow.instr(19, 15)) 126 val src2 = Cat(0.U(1.W), ctrl_flow.instr(24, 20)) 127 val dest = Cat(0.U(1.W), ctrl_flow.instr(11, 7 )) 128 129 //uop div up to maxNumOfUop 130 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 131 csBundle.map { case dst => 132 dst := cf_ctrl_u 133 dst.ctrl.firstUop := false.B 134 dst.ctrl.lastUop := false.B 135 } 136 137 csBundle(0).ctrl.firstUop := true.B 138 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 139 140 switch(typeOfDiv) { 141 is(UopDivType.DIR) { 142 when(isVset_u) { 143 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR || ALUOpType.isVsetvl(cf_ctrl_u.ctrl.fuOpType) 144 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 145 csBundle(1).ctrl.ldest := INT_VCONFIG.U 146 csBundle(1).ctrl.flushPipe := false.B 147 } 148 } 149 is(UopDivType.VEC_VVV) { 150 for (i <- 0 until MAX_VLMUL) { 151 csBundle(i).ctrl.lsrc(0) := src1 + i.U 152 csBundle(i).ctrl.lsrc(1) := src2 + i.U 153 csBundle(i).ctrl.lsrc(2) := dest + i.U 154 csBundle(i).ctrl.ldest := dest + i.U 155 csBundle(i).ctrl.uopIdx := i.U 156 } 157 } 158 is(UopDivType.VEC_EXT2) { 159 for (i <- 0 until MAX_VLMUL / 2) { 160 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 161 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 162 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 163 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 164 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 165 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 166 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 167 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 168 } 169 } 170 is(UopDivType.VEC_EXT4) { 171 for (i <- 0 until MAX_VLMUL / 4) { 172 csBundle(4 * i).ctrl.lsrc(1) := src2 + i.U 173 csBundle(4 * i).ctrl.lsrc(2) := dest + (4 * i).U 174 csBundle(4 * i).ctrl.ldest := dest + (4 * i).U 175 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 176 csBundle(4 * i + 1).ctrl.lsrc(1) := src2 + i.U 177 csBundle(4 * i + 1).ctrl.lsrc(2) := dest + (4 * i + 1).U 178 csBundle(4 * i + 1).ctrl.ldest := dest + (4 * i + 1).U 179 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 180 csBundle(4 * i + 2).ctrl.lsrc(1) := src2 + i.U 181 csBundle(4 * i + 2).ctrl.lsrc(2) := dest + (4 * i + 2).U 182 csBundle(4 * i + 2).ctrl.ldest := dest + (4 * i + 2).U 183 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 184 csBundle(4 * i + 3).ctrl.lsrc(1) := src2 + i.U 185 csBundle(4 * i + 3).ctrl.lsrc(2) := dest + (4 * i + 3).U 186 csBundle(4 * i + 3).ctrl.ldest := dest + (4 * i + 3).U 187 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 188 } 189 } 190 is(UopDivType.VEC_EXT8) { 191 for (i <- 0 until MAX_VLMUL) { 192 csBundle(i).ctrl.lsrc(1) := src2 193 csBundle(i).ctrl.lsrc(2) := dest + i.U 194 csBundle(i).ctrl.ldest := dest + i.U 195 csBundle(i).ctrl.uopIdx := i.U 196 } 197 } 198 is(UopDivType.VEC_0XV) { 199 /* 200 FMV.D.X 201 */ 202 csBundle(0).ctrl.srcType(0) := SrcType.reg 203 csBundle(0).ctrl.srcType(1) := SrcType.imm 204 csBundle(0).ctrl.lsrc(1) := 0.U 205 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 206 csBundle(0).ctrl.fuType := FuType.i2f 207 csBundle(0).ctrl.rfWen := false.B 208 csBundle(0).ctrl.fpWen := true.B 209 csBundle(0).ctrl.vecWen := false.B 210 csBundle(0).ctrl.fpu.isAddSub := false.B 211 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 212 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 213 csBundle(0).ctrl.fpu.fromInt := true.B 214 csBundle(0).ctrl.fpu.wflags := false.B 215 csBundle(0).ctrl.fpu.fpWen := true.B 216 csBundle(0).ctrl.fpu.div := false.B 217 csBundle(0).ctrl.fpu.sqrt := false.B 218 csBundle(0).ctrl.fpu.fcvt := false.B 219 /* 220 vfmv.s.f 221 */ 222 csBundle(1).ctrl.srcType(0) := SrcType.fp 223 csBundle(1).ctrl.srcType(1) := SrcType.vp 224 csBundle(1).ctrl.srcType(2) := SrcType.vp 225 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 226 csBundle(1).ctrl.lsrc(1) := 0.U 227 csBundle(1).ctrl.lsrc(2) := dest 228 csBundle(1).ctrl.ldest := dest 229 csBundle(1).ctrl.fuType := FuType.vppu 230 csBundle(1).ctrl.fuOpType := VpermType.vfmv_s_f 231 csBundle(1).ctrl.rfWen := false.B 232 csBundle(1).ctrl.fpWen := false.B 233 csBundle(1).ctrl.vecWen := true.B 234 } 235 is(UopDivType.VEC_VXV) { 236 /* 237 FMV.D.X 238 */ 239 csBundle(0).ctrl.srcType(0) := SrcType.reg 240 csBundle(0).ctrl.srcType(1) := SrcType.imm 241 csBundle(0).ctrl.lsrc(1) := 0.U 242 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 243 csBundle(0).ctrl.fuType := FuType.i2f 244 csBundle(0).ctrl.rfWen := false.B 245 csBundle(0).ctrl.fpWen := true.B 246 csBundle(0).ctrl.vecWen := false.B 247 csBundle(0).ctrl.fpu.isAddSub := false.B 248 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 249 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 250 csBundle(0).ctrl.fpu.fromInt := true.B 251 csBundle(0).ctrl.fpu.wflags := false.B 252 csBundle(0).ctrl.fpu.fpWen := true.B 253 csBundle(0).ctrl.fpu.div := false.B 254 csBundle(0).ctrl.fpu.sqrt := false.B 255 csBundle(0).ctrl.fpu.fcvt := false.B 256 /* 257 LMUL 258 */ 259 for (i <- 0 until MAX_VLMUL) { 260 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 261 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 262 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 263 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 264 csBundle(i + 1).ctrl.ldest := dest + i.U 265 csBundle(i + 1).ctrl.uopIdx := i.U 266 } 267 } 268 is(UopDivType.VEC_VVW) { 269 for (i <- 0 until MAX_VLMUL / 2) { 270 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 271 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 272 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 273 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 274 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 275 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 276 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 277 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 278 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 279 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 280 } 281 } 282 is(UopDivType.VEC_WVW) { 283 for (i <- 0 until MAX_VLMUL / 2) { 284 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 285 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 286 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 287 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 288 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 289 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 290 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 291 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 292 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 293 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 294 } 295 } 296 is(UopDivType.VEC_VXW) { 297 /* 298 FMV.D.X 299 */ 300 csBundle(0).ctrl.srcType(0) := SrcType.reg 301 csBundle(0).ctrl.srcType(1) := SrcType.imm 302 csBundle(0).ctrl.lsrc(1) := 0.U 303 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 304 csBundle(0).ctrl.fuType := FuType.i2f 305 csBundle(0).ctrl.rfWen := false.B 306 csBundle(0).ctrl.fpWen := true.B 307 csBundle(0).ctrl.vecWen := false.B 308 csBundle(0).ctrl.fpu.isAddSub := false.B 309 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 310 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 311 csBundle(0).ctrl.fpu.fromInt := true.B 312 csBundle(0).ctrl.fpu.wflags := false.B 313 csBundle(0).ctrl.fpu.fpWen := true.B 314 csBundle(0).ctrl.fpu.div := false.B 315 csBundle(0).ctrl.fpu.sqrt := false.B 316 csBundle(0).ctrl.fpu.fcvt := false.B 317 318 for (i <- 0 until MAX_VLMUL / 2) { 319 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 320 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 321 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 322 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 323 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 324 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 325 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 326 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 327 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U 328 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 329 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 330 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 331 } 332 } 333 is(UopDivType.VEC_WXW) { 334 /* 335 FMV.D.X 336 */ 337 csBundle(0).ctrl.srcType(0) := SrcType.reg 338 csBundle(0).ctrl.srcType(1) := SrcType.imm 339 csBundle(0).ctrl.lsrc(1) := 0.U 340 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 341 csBundle(0).ctrl.fuType := FuType.i2f 342 csBundle(0).ctrl.rfWen := false.B 343 csBundle(0).ctrl.fpWen := true.B 344 csBundle(0).ctrl.vecWen := false.B 345 csBundle(0).ctrl.fpu.isAddSub := false.B 346 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 347 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 348 csBundle(0).ctrl.fpu.fromInt := true.B 349 csBundle(0).ctrl.fpu.wflags := false.B 350 csBundle(0).ctrl.fpu.fpWen := true.B 351 csBundle(0).ctrl.fpu.div := false.B 352 csBundle(0).ctrl.fpu.sqrt := false.B 353 csBundle(0).ctrl.fpu.fcvt := false.B 354 355 for (i <- 0 until MAX_VLMUL / 2) { 356 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 357 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 358 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 359 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 360 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 361 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 362 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 363 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 364 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 365 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 366 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 367 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 368 } 369 } 370 is(UopDivType.VEC_WVV) { 371 for (i <- 0 until MAX_VLMUL / 2) { 372 373 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 374 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 375 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 376 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 377 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 378 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 379 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 380 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 381 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 382 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 383 } 384 } 385 is(UopDivType.VEC_WXV) { 386 /* 387 FMV.D.X 388 */ 389 csBundle(0).ctrl.srcType(0) := SrcType.reg 390 csBundle(0).ctrl.srcType(1) := SrcType.imm 391 csBundle(0).ctrl.lsrc(1) := 0.U 392 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 393 csBundle(0).ctrl.fuType := FuType.i2f 394 csBundle(0).ctrl.rfWen := false.B 395 csBundle(0).ctrl.fpWen := true.B 396 csBundle(0).ctrl.vecWen := false.B 397 csBundle(0).ctrl.fpu.isAddSub := false.B 398 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 399 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 400 csBundle(0).ctrl.fpu.fromInt := true.B 401 csBundle(0).ctrl.fpu.wflags := false.B 402 csBundle(0).ctrl.fpu.fpWen := true.B 403 csBundle(0).ctrl.fpu.div := false.B 404 csBundle(0).ctrl.fpu.sqrt := false.B 405 csBundle(0).ctrl.fpu.fcvt := false.B 406 407 for (i <- 0 until MAX_VLMUL / 2) { 408 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 409 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 410 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 411 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 412 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 413 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 414 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 415 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 416 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 417 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 418 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 419 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 420 } 421 } 422 is(UopDivType.VEC_VVM) { 423 csBundle(0).ctrl.lsrc(2) := dest 424 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 425 csBundle(0).ctrl.uopIdx := 0.U 426 for(i <- 1 until MAX_VLMUL) { 427 csBundle(i).ctrl.lsrc(0) := src1 + i.U 428 csBundle(i).ctrl.lsrc(1) := src2 + i.U 429 csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 430 csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 431 csBundle(i).ctrl.uopIdx := i.U 432 } 433 csBundle(numOfUop - 1.U).ctrl.ldest := dest 434 } 435 is(UopDivType.VEC_VXM) { 436 /* 437 FMV.D.X 438 */ 439 csBundle(0).ctrl.srcType(0) := SrcType.reg 440 csBundle(0).ctrl.srcType(1) := SrcType.imm 441 csBundle(0).ctrl.lsrc(1) := 0.U 442 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 443 csBundle(0).ctrl.fuType := FuType.i2f 444 csBundle(0).ctrl.rfWen := false.B 445 csBundle(0).ctrl.fpWen := true.B 446 csBundle(0).ctrl.vecWen := false.B 447 csBundle(0).ctrl.fpu.isAddSub := false.B 448 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 449 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 450 csBundle(0).ctrl.fpu.fromInt := true.B 451 csBundle(0).ctrl.fpu.wflags := false.B 452 csBundle(0).ctrl.fpu.fpWen := true.B 453 csBundle(0).ctrl.fpu.div := false.B 454 csBundle(0).ctrl.fpu.sqrt := false.B 455 csBundle(0).ctrl.fpu.fcvt := false.B 456 //LMUL 457 csBundle(1).ctrl.srcType(0) := SrcType.fp 458 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 459 csBundle(1).ctrl.lsrc(2) := dest 460 csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 461 csBundle(1).ctrl.uopIdx := 0.U 462 for (i <- 1 until MAX_VLMUL) { 463 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 464 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 465 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 466 csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 467 csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 468 csBundle(i + 1).ctrl.uopIdx := i.U 469 } 470 csBundle(numOfUop - 1.U).ctrl.ldest := dest 471 } 472 is(UopDivType.VEC_SLIDE1UP) { 473 /* 474 FMV.D.X 475 */ 476 csBundle(0).ctrl.srcType(0) := SrcType.reg 477 csBundle(0).ctrl.srcType(1) := SrcType.imm 478 csBundle(0).ctrl.lsrc(1) := 0.U 479 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 480 csBundle(0).ctrl.fuType := FuType.i2f 481 csBundle(0).ctrl.rfWen := false.B 482 csBundle(0).ctrl.fpWen := true.B 483 csBundle(0).ctrl.vecWen := false.B 484 csBundle(0).ctrl.fpu.isAddSub := false.B 485 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 486 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 487 csBundle(0).ctrl.fpu.fromInt := true.B 488 csBundle(0).ctrl.fpu.wflags := false.B 489 csBundle(0).ctrl.fpu.fpWen := true.B 490 csBundle(0).ctrl.fpu.div := false.B 491 csBundle(0).ctrl.fpu.sqrt := false.B 492 csBundle(0).ctrl.fpu.fcvt := false.B 493 //LMUL 494 csBundle(1).ctrl.srcType(0) := SrcType.fp 495 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 496 csBundle(1).ctrl.lsrc(2) := dest 497 csBundle(1).ctrl.ldest := dest 498 csBundle(1).ctrl.uopIdx := 0.U 499 for (i <- 1 until MAX_VLMUL) { 500 csBundle(i + 1).ctrl.srcType(0) := SrcType.vp 501 csBundle(i + 1).ctrl.lsrc(0) := src2 + (i - 1).U 502 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 503 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 504 csBundle(i + 1).ctrl.ldest := dest + i.U 505 csBundle(i + 1).ctrl.uopIdx := i.U 506 } 507 } 508 is(UopDivType.VEC_FSLIDE1UP) { 509 //LMUL 510 csBundle(0).ctrl.srcType(0) := SrcType.fp 511 csBundle(0).ctrl.lsrc(0) := src1 512 csBundle(0).ctrl.lsrc(1) := src2 513 csBundle(0).ctrl.lsrc(2) := dest 514 csBundle(0).ctrl.ldest := dest 515 csBundle(0).ctrl.uopIdx := 0.U 516 for (i <- 1 until MAX_VLMUL) { 517 csBundle(i).ctrl.srcType(0) := SrcType.vp 518 csBundle(i).ctrl.lsrc(0) := src2 + (i - 1).U 519 csBundle(i).ctrl.lsrc(1) := src2 + i.U 520 csBundle(i).ctrl.lsrc(2) := dest + i.U 521 csBundle(i).ctrl.ldest := dest + i.U 522 csBundle(i).ctrl.uopIdx := i.U 523 } 524 } 525 is(UopDivType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 526 /* 527 FMV.D.X 528 */ 529 csBundle(0).ctrl.srcType(0) := SrcType.reg 530 csBundle(0).ctrl.srcType(1) := SrcType.imm 531 csBundle(0).ctrl.lsrc(1) := 0.U 532 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 533 csBundle(0).ctrl.fuType := FuType.i2f 534 csBundle(0).ctrl.rfWen := false.B 535 csBundle(0).ctrl.fpWen := true.B 536 csBundle(0).ctrl.vecWen := false.B 537 csBundle(0).ctrl.fpu.isAddSub := false.B 538 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 539 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 540 csBundle(0).ctrl.fpu.fromInt := true.B 541 csBundle(0).ctrl.fpu.wflags := false.B 542 csBundle(0).ctrl.fpu.fpWen := true.B 543 csBundle(0).ctrl.fpu.div := false.B 544 csBundle(0).ctrl.fpu.sqrt := false.B 545 csBundle(0).ctrl.fpu.fcvt := false.B 546 //LMUL 547 for (i <- 0 until MAX_VLMUL) { 548 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp 549 csBundle(2 * i + 1).ctrl.srcType(1) := SrcType.vp 550 csBundle(2 * i + 1).ctrl.lsrc(0) := src2 + (i+1).U 551 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 552 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 553 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 554 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 555 if (2 * i + 2 < MAX_VLMUL * 2 ){ 556 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 557 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 558 // csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U // DontCare 559 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 560 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 561 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 562 } 563 } 564 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 565 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := FP_TMP_REG_MV.U 566 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 567 } 568 is(UopDivType.VEC_FSLIDE1DOWN) { 569 //LMUL 570 for (i <- 0 until MAX_VLMUL) { 571 csBundle(2 * i).ctrl.srcType(0) := SrcType.vp 572 csBundle(2 * i).ctrl.srcType(1) := SrcType.vp 573 csBundle(2 * i).ctrl.lsrc(0) := src2 + (i+1).U 574 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 575 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 576 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 577 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 578 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 579 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 580 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 581 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 582 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 583 } 584 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 585 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1 586 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 587 } 588 is(UopDivType.VEC_VRED) { 589 when(simple.io.vconfig.vtype.vlmul === "b001".U){ 590 csBundle(0).ctrl.srcType(2) := SrcType.DC 591 csBundle(0).ctrl.lsrc(0) := src2 + 1.U 592 csBundle(0).ctrl.lsrc(1) := src2 593 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 594 csBundle(0).ctrl.uopIdx := 0.U 595 } 596 when(simple.io.vconfig.vtype.vlmul === "b010".U) { 597 csBundle(0).ctrl.srcType(2) := SrcType.DC 598 csBundle(0).ctrl.lsrc(0) := src2 + 1.U 599 csBundle(0).ctrl.lsrc(1) := src2 600 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 601 csBundle(0).ctrl.uopIdx := 0.U 602 603 csBundle(1).ctrl.srcType(2) := SrcType.DC 604 csBundle(1).ctrl.lsrc(0) := src2 + 3.U 605 csBundle(1).ctrl.lsrc(1) := src2 + 2.U 606 csBundle(1).ctrl.ldest := (VECTOR_TMP_REG_LMUL+1).U 607 csBundle(1).ctrl.uopIdx := 1.U 608 609 csBundle(2).ctrl.srcType(2) := SrcType.DC 610 csBundle(2).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL+1).U 611 csBundle(2).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U 612 csBundle(2).ctrl.ldest := (VECTOR_TMP_REG_LMUL+2).U 613 csBundle(2).ctrl.uopIdx := 2.U 614 } 615 when(simple.io.vconfig.vtype.vlmul === "b011".U) { 616 for(i <- 0 until MAX_VLMUL){ 617 if(i < MAX_VLMUL - MAX_VLMUL/2){ 618 csBundle(i).ctrl.lsrc(0) := src2 + (i * 2 + 1).U 619 csBundle(i).ctrl.lsrc(1) := src2 + (i * 2).U 620 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 621 } else if (i < MAX_VLMUL - MAX_VLMUL/4) { 622 csBundle(i).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2 + 1).U 623 csBundle(i).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2).U 624 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 625 }else if (i < MAX_VLMUL - MAX_VLMUL/8) { 626 csBundle(6).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 627 csBundle(6).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 628 csBundle(6).ctrl.ldest := (VECTOR_TMP_REG_LMUL + 6).U 629 } 630 csBundle(i).ctrl.srcType(2) := SrcType.DC 631 csBundle(i).ctrl.uopIdx := i.U 632 } 633 } 634 when (simple.io.vconfig.vtype.vlmul.orR()){ 635 csBundle(numOfUop - 1.U).ctrl.srcType(2) := SrcType.vp 636 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1 637 csBundle(numOfUop - 1.U).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 638 csBundle(numOfUop - 1.U).ctrl.lsrc(2) := dest 639 csBundle(numOfUop - 1.U).ctrl.ldest := dest 640 csBundle(numOfUop - 1.U).ctrl.uopIdx := numOfUop - 1.U 641 } 642 } 643 644 is(UopDivType.VEC_SLIDEUP) { 645 // FMV.D.X 646 csBundle(0).ctrl.srcType(0) := SrcType.reg 647 csBundle(0).ctrl.srcType(1) := SrcType.imm 648 csBundle(0).ctrl.lsrc(1) := 0.U 649 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 650 csBundle(0).ctrl.fuType := FuType.i2f 651 csBundle(0).ctrl.rfWen := false.B 652 csBundle(0).ctrl.fpWen := true.B 653 csBundle(0).ctrl.vecWen := false.B 654 csBundle(0).ctrl.fpu.isAddSub := false.B 655 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 656 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 657 csBundle(0).ctrl.fpu.fromInt := true.B 658 csBundle(0).ctrl.fpu.wflags := false.B 659 csBundle(0).ctrl.fpu.fpWen := true.B 660 csBundle(0).ctrl.fpu.div := false.B 661 csBundle(0).ctrl.fpu.sqrt := false.B 662 csBundle(0).ctrl.fpu.fcvt := false.B 663 // LMUL 664 for(i <- 0 until MAX_VLMUL) 665 for(j <- 0 to i){ 666 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 667 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 668 csBundle(i*(i+1)/2+j+1).ctrl.srcType(0) := SrcType.fp 669 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 670 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(1) := src2 + j.U 671 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(2) := old_vd 672 csBundle(i*(i+1)/2+j+1).ctrl.ldest := vd 673 csBundle(i*(i+1)/2+j+1).ctrl.uopIdx := (i*(i+1)/2+j).U 674 } 675 } 676 677 is(UopDivType.VEC_ISLIDEUP) { 678 // LMUL 679 for(i <- 0 until MAX_VLMUL) 680 for(j <- 0 to i){ 681 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 682 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 683 csBundle(i*(i+1)/2+j).ctrl.lsrc(1) := src2 + j.U 684 csBundle(i*(i+1)/2+j).ctrl.lsrc(2) := old_vd 685 csBundle(i*(i+1)/2+j).ctrl.ldest := vd 686 csBundle(i*(i+1)/2+j).ctrl.uopIdx := (i*(i+1)/2+j).U 687 } 688 } 689 690 is(UopDivType.VEC_SLIDEDOWN) { 691 // FMV.D.X 692 csBundle(0).ctrl.srcType(0) := SrcType.reg 693 csBundle(0).ctrl.srcType(1) := SrcType.imm 694 csBundle(0).ctrl.lsrc(1) := 0.U 695 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 696 csBundle(0).ctrl.fuType := FuType.i2f 697 csBundle(0).ctrl.rfWen := false.B 698 csBundle(0).ctrl.fpWen := true.B 699 csBundle(0).ctrl.vecWen := false.B 700 csBundle(0).ctrl.fpu.isAddSub := false.B 701 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 702 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 703 csBundle(0).ctrl.fpu.fromInt := true.B 704 csBundle(0).ctrl.fpu.wflags := false.B 705 csBundle(0).ctrl.fpu.fpWen := true.B 706 csBundle(0).ctrl.fpu.div := false.B 707 csBundle(0).ctrl.fpu.sqrt := false.B 708 csBundle(0).ctrl.fpu.fcvt := false.B 709 // LMUL 710 for(i <- 0 until MAX_VLMUL) 711 for(j <- (0 to i).reverse){ 712 when(i.U < lmul){ 713 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 714 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 715 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.srcType(0) := SrcType.fp 716 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(0) := FP_TMP_REG_MV.U 717 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(1) := src2 + lmul - 1.U - j.U 718 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(2) := old_vd 719 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.ldest := vd 720 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.uopIdx := numOfUop-(i*(i+1)/2+i-j+2).U 721 } 722 } 723 } 724 725 is(UopDivType.VEC_ISLIDEDOWN) { 726 // LMUL 727 for(i <- 0 until MAX_VLMUL) 728 for(j <- (0 to i).reverse){ 729 when(i.U < lmul){ 730 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 731 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 732 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(1) := src2 + lmul - 1.U - j.U 733 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(2) := old_vd 734 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.ldest := vd 735 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.uopIdx := numOfUop-(i*(i+1)/2+i-j+1).U 736 } 737 } 738 } 739 740 is(UopDivType.VEC_M0X) { 741 // LMUL 742 for (i <- 0 until MAX_VLMUL) { 743 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 744 val ldest = (VECTOR_TMP_REG_LMUL + i).U 745 csBundle(i).ctrl.srcType(0) := srcType0 746 csBundle(i).ctrl.srcType(1) := SrcType.vp 747 csBundle(i).ctrl.rfWen := false.B 748 csBundle(i).ctrl.vecWen := true.B 749 csBundle(i).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 750 csBundle(i).ctrl.lsrc(1) := src2 751 // csBundle(i).ctrl.lsrc(2) := dest + i.U DontCare 752 csBundle(i).ctrl.ldest := ldest 753 csBundle(i).ctrl.uopIdx := i.U 754 } 755 csBundle(lmul-1.U).ctrl.vecWen := false.B 756 csBundle(lmul-1.U).ctrl.fpWen := true.B 757 csBundle(lmul-1.U).ctrl.ldest := FP_TMP_REG_MV.U 758 // FMV_X_D 759 csBundle(lmul).ctrl.srcType(0) := SrcType.fp 760 csBundle(lmul).ctrl.srcType(1) := SrcType.imm 761 csBundle(lmul).ctrl.lsrc(0) := FP_TMP_REG_MV.U 762 csBundle(lmul).ctrl.lsrc(1) := 0.U 763 csBundle(lmul).ctrl.ldest := dest 764 csBundle(lmul).ctrl.fuType := FuType.fmisc 765 csBundle(lmul).ctrl.rfWen := true.B 766 csBundle(lmul).ctrl.fpWen := false.B 767 csBundle(lmul).ctrl.vecWen := false.B 768 csBundle(lmul).ctrl.fpu.isAddSub := false.B 769 csBundle(lmul).ctrl.fpu.typeTagIn := FPU.D 770 csBundle(lmul).ctrl.fpu.typeTagOut := FPU.D 771 csBundle(lmul).ctrl.fpu.fromInt := false.B 772 csBundle(lmul).ctrl.fpu.wflags := false.B 773 csBundle(lmul).ctrl.fpu.fpWen := false.B 774 csBundle(lmul).ctrl.fpu.div := false.B 775 csBundle(lmul).ctrl.fpu.sqrt := false.B 776 csBundle(lmul).ctrl.fpu.fcvt := false.B 777 } 778 779 is(UopDivType.VEC_MVV) { 780 // LMUL 781 for (i <- 0 until MAX_VLMUL) { 782 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 783 csBundle(i*2+0).ctrl.srcType(0) := srcType0 784 csBundle(i*2+0).ctrl.srcType(1) := SrcType.vp 785 csBundle(i*2+0).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 786 csBundle(i*2+0).ctrl.lsrc(1) := src2 787 csBundle(i*2+0).ctrl.lsrc(2) := dest + i.U 788 csBundle(i*2+0).ctrl.ldest := dest + i.U 789 csBundle(i*2+0).ctrl.uopIdx := (i*2+0).U 790 791 csBundle(i*2+1).ctrl.srcType(0) := srcType0 792 csBundle(i*2+1).ctrl.srcType(1) := SrcType.vp 793 csBundle(i*2+1).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 794 csBundle(i*2+1).ctrl.lsrc(1) := src2 795 // csBundle(i).ctrl.lsrc(2) := dest + i.U DontCare 796 csBundle(i*2+1).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 797 csBundle(i*2+1).ctrl.uopIdx := (i*2+1).U 798 } 799 } 800 801 is(UopDivType.VEC_M0X_VFIRST) { 802 // LMUL 803 csBundle(0).ctrl.rfWen := false.B 804 csBundle(0).ctrl.fpWen := true.B 805 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 806 // FMV_X_D 807 csBundle(1).ctrl.srcType(0) := SrcType.fp 808 csBundle(1).ctrl.srcType(1) := SrcType.imm 809 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 810 csBundle(1).ctrl.lsrc(1) := 0.U 811 csBundle(1).ctrl.ldest := dest 812 csBundle(1).ctrl.fuType := FuType.fmisc 813 csBundle(1).ctrl.rfWen := true.B 814 csBundle(1).ctrl.fpWen := false.B 815 csBundle(1).ctrl.vecWen := false.B 816 csBundle(1).ctrl.fpu.isAddSub := false.B 817 csBundle(1).ctrl.fpu.typeTagIn := FPU.D 818 csBundle(1).ctrl.fpu.typeTagOut := FPU.D 819 csBundle(1).ctrl.fpu.fromInt := false.B 820 csBundle(1).ctrl.fpu.wflags := false.B 821 csBundle(1).ctrl.fpu.fpWen := false.B 822 csBundle(1).ctrl.fpu.div := false.B 823 csBundle(1).ctrl.fpu.sqrt := false.B 824 csBundle(1).ctrl.fpu.fcvt := false.B 825 } 826 827 is(UopDivType.VEC_VWW) { 828 for (i <- 0 until MAX_VLMUL*2) { 829 when(i.U < lmul){ 830 csBundle(i).ctrl.srcType(2) := SrcType.DC 831 csBundle(i).ctrl.lsrc(0) := src2 + i.U 832 csBundle(i).ctrl.lsrc(1) := src2 + i.U 833 // csBundle(i).ctrl.lsrc(2) := dest + (2 * i).U 834 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 835 csBundle(i).ctrl.uopIdx := i.U 836 } otherwise { 837 csBundle(i).ctrl.srcType(2) := SrcType.DC 838 csBundle(i).ctrl.lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 839 csBundle(i).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 840 // csBundle(i).ctrl.lsrc(2) := dest + (2 * i).U 841 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 842 csBundle(i).ctrl.uopIdx := i.U 843 } 844 csBundle(numOfUop-1.U).ctrl.srcType(2) := SrcType.vp 845 csBundle(numOfUop-1.U).ctrl.lsrc(0) := src1 846 csBundle(numOfUop-1.U).ctrl.lsrc(2) := dest 847 csBundle(numOfUop-1.U).ctrl.ldest := dest 848 } 849 } 850 } 851 852 //uops dispatch 853 val normal :: ext :: Nil = Enum(2) 854 val stateReg = RegInit(normal) 855 val uopRes = RegInit(0.U) 856 857 //readyFromRename Counter 858 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 859 860 switch(stateReg) { 861 is(normal) { 862 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 863 } 864 is(ext) { 865 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 866 } 867 } 868 869 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 870 val uopResJudge = Mux(stateReg === normal, 871 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 872 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 873 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 874 875 for(i <- 0 until RenameWidth) { 876 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 877 (stateReg === normal) -> csBundle(i), 878 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 879 )) 880 } 881 882 883 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 884 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 885 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 886 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 887 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 888 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 889 notInfVec(0) := true.B 890 891 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 892 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 893 1.U) 894 validToRename.zipWithIndex.foreach{ 895 case(dst, i) => 896 dst := MuxCase(false.B, Seq( 897 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 898 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 899 )) 900 } 901 902 readyToIBuf.zipWithIndex.foreach { 903 case (dst, i) => 904 dst := MuxCase(true.B, Seq( 905 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 906 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 907 )) 908 } 909 910 io.deq.cf_ctrl := cf_ctrl 911 io.deq.isVset := isVset_u 912 io.deq.complexNum := complexNum 913 io.deq.validToRename := validToRename 914 io.deq.readyToIBuf := readyToIBuf 915 916} 917 918