1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.VType 34import yunsuan.VpermType 35 36import scala.collection.Seq 37 38trait VectorConstants { 39 val MAX_VLMUL = 8 40 val FP_TMP_REG_MV = 32 41 val VECTOR_TMP_REG_LMUL = 33 // 33~47 -> 15 42} 43 44class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 45 val enq = new Bundle { val staticInst = Input(new StaticInst) } 46 val vtype = Input(new VType) 47 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 48 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 49 val readyFromRename = Input(Vec(RenameWidth, Bool())) 50 val deq = new Bundle { 51 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 52 val isVset = Output(Bool()) 53 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 54 val validToRename = Output(Vec(RenameWidth, Bool())) 55 val complexNum = Output(UInt(3.W)) 56 } 57 val csrCtrl = Input(new CustomCSRCtrlIO) 58} 59 60/** 61 * @author zly 62 */ 63class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 64 val io = IO(new DecodeUnitCompIO) 65 66 val maxUopSize = MaxUopSize 67 //input bits 68 val staticInst = Wire(new StaticInst) 69 private val inst: XSInstBitFields = staticInst.asTypeOf(new XSInstBitFields) 70 71 staticInst := io.enq.staticInst 72 73 val src1 = Cat(0.U(1.W), inst.RS1) 74 val src2 = Cat(0.U(1.W), inst.RS2) 75 val dest = Cat(0.U(1.W), inst.RD) 76 77 78 //output bits 79 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 80 val validToRename = Wire(Vec(RenameWidth, Bool())) 81 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 82 val complexNum = Wire(UInt(3.W)) 83 84 //output of DecodeUnit 85 val decodedInstsSimple = Wire(new DecodedInst) 86 val numOfUop = Wire(UInt(log2Up(maxUopSize+1).W)) 87 val lmul = Wire(UInt(4.W)) 88 val isVsetSimple = Wire(Bool()) 89 90 //pre decode 91 val simple = Module(new DecodeUnit) 92 simple.io.enq.ctrlFlow := staticInst 93 simple.io.enq.vtype := io.vtype 94 simple.io.csrCtrl := io.csrCtrl 95 decodedInstsSimple := simple.io.deq.decodedInst 96 lmul := simple.io.deq.uopInfo.lmul 97 isVsetSimple := simple.io.deq.decodedInst.isVset 98 when(isVsetSimple) { 99 when(dest === 0.U && src1 === 0.U) { 100 decodedInstsSimple.fuOpType := VSETOpType.keepVl(simple.io.deq.decodedInst.fuOpType) 101 }.elsewhen(src1 === 0.U) { 102 decodedInstsSimple.fuOpType := VSETOpType.setVlmax(simple.io.deq.decodedInst.fuOpType) 103 } 104 when(io.vtype.illegal){ 105 decodedInstsSimple.flushPipe := true.B 106 } 107 } 108 //Type of uop Div 109 val typeOfSplit = decodedInstsSimple.uopSplitType 110 111 when(typeOfSplit === UopSplitType.DIR) { 112 numOfUop := Mux(dest =/= 0.U, 2.U, 113 Mux(src1 =/= 0.U, 1.U, 114 Mux(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType), 2.U, 1.U))) 115 } .otherwise { 116 numOfUop := simple.io.deq.uopInfo.numOfUop 117 } 118 119 120 //uop div up to maxUopSize 121 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 122 csBundle.map { case dst => 123 dst := decodedInstsSimple 124 dst.firstUop := false.B 125 dst.lastUop := false.B 126 } 127 128 csBundle(0).numUops := numOfUop 129 csBundle(0).firstUop := true.B 130 csBundle(numOfUop - 1.U).lastUop := true.B 131 132 switch(typeOfSplit) { 133 is(UopSplitType.DIR) { 134 when(isVsetSimple) { 135 when(dest =/= 0.U) { 136 csBundle(0).fuType := FuType.vsetiwi.U 137 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInstsSimple.fuOpType) 138 csBundle(0).flushPipe := false.B 139 csBundle(0).rfWen := true.B 140 csBundle(0).vecWen := false.B 141 csBundle(1).ldest := VCONFIG_IDX.U 142 csBundle(1).rfWen := false.B 143 csBundle(1).vecWen := true.B 144 }.elsewhen(src1 =/= 0.U) { 145 csBundle(0).ldest := VCONFIG_IDX.U 146 }.elsewhen(VSETOpType.isVsetvli(decodedInstsSimple.fuOpType)) { 147 csBundle(0).fuType := FuType.vsetfwf.U 148 csBundle(0).srcType(0) := SrcType.vp 149 csBundle(0).lsrc(0) := VCONFIG_IDX.U 150 }.elsewhen(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType)) { 151 csBundle(0).srcType(0) := SrcType.reg 152 csBundle(0).srcType(1) := SrcType.imm 153 csBundle(0).lsrc(1) := 0.U 154 csBundle(0).ldest := FP_TMP_REG_MV.U 155 csBundle(0).fuType := FuType.i2f.U 156 csBundle(0).rfWen := false.B 157 csBundle(0).fpWen := true.B 158 csBundle(0).vecWen := false.B 159 csBundle(0).fpu.isAddSub := false.B 160 csBundle(0).fpu.typeTagIn := FPU.D 161 csBundle(0).fpu.typeTagOut := FPU.D 162 csBundle(0).fpu.fromInt := true.B 163 csBundle(0).fpu.wflags := false.B 164 csBundle(0).fpu.fpWen := true.B 165 csBundle(0).fpu.div := false.B 166 csBundle(0).fpu.sqrt := false.B 167 csBundle(0).fpu.fcvt := false.B 168 csBundle(0).flushPipe := false.B 169 csBundle(1).fuType := FuType.vsetfwf.U 170 csBundle(1).srcType(0) := SrcType.vp 171 csBundle(1).lsrc(0) := VCONFIG_IDX.U 172 csBundle(1).srcType(1) := SrcType.fp 173 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 174 csBundle(1).ldest := VCONFIG_IDX.U 175 } 176 } 177 } 178 is(UopSplitType.VEC_VVV) { 179 for (i <- 0 until MAX_VLMUL) { 180 csBundle(i).lsrc(0) := src1 + i.U 181 csBundle(i).lsrc(1) := src2 + i.U 182 csBundle(i).lsrc(2) := dest + i.U 183 csBundle(i).ldest := dest + i.U 184 csBundle(i).uopIdx := i.U 185 } 186 } 187 is(UopSplitType.VEC_EXT2) { 188 for (i <- 0 until MAX_VLMUL / 2) { 189 csBundle(2 * i).lsrc(1) := src2 + i.U 190 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 191 csBundle(2 * i).ldest := dest + (2 * i).U 192 csBundle(2 * i).uopIdx := (2 * i).U 193 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 194 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 195 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 196 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 197 } 198 } 199 is(UopSplitType.VEC_EXT4) { 200 for (i <- 0 until MAX_VLMUL / 4) { 201 csBundle(4 * i).lsrc(1) := src2 + i.U 202 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 203 csBundle(4 * i).ldest := dest + (4 * i).U 204 csBundle(4 * i).uopIdx := (4 * i).U 205 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 206 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 207 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 208 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 209 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 210 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 211 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 212 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 213 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 214 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 215 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 216 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 217 } 218 } 219 is(UopSplitType.VEC_EXT8) { 220 for (i <- 0 until MAX_VLMUL) { 221 csBundle(i).lsrc(1) := src2 222 csBundle(i).lsrc(2) := dest + i.U 223 csBundle(i).ldest := dest + i.U 224 csBundle(i).uopIdx := i.U 225 } 226 } 227 is(UopSplitType.VEC_0XV) { 228 /* 229 FMV.D.X 230 */ 231 csBundle(0).srcType(0) := SrcType.reg 232 csBundle(0).srcType(1) := SrcType.imm 233 csBundle(0).lsrc(1) := 0.U 234 csBundle(0).ldest := FP_TMP_REG_MV.U 235 csBundle(0).fuType := FuType.i2f.U 236 csBundle(0).rfWen := false.B 237 csBundle(0).fpWen := true.B 238 csBundle(0).vecWen := false.B 239 csBundle(0).fpu.isAddSub := false.B 240 csBundle(0).fpu.typeTagIn := FPU.D 241 csBundle(0).fpu.typeTagOut := FPU.D 242 csBundle(0).fpu.fromInt := true.B 243 csBundle(0).fpu.wflags := false.B 244 csBundle(0).fpu.fpWen := true.B 245 csBundle(0).fpu.div := false.B 246 csBundle(0).fpu.sqrt := false.B 247 csBundle(0).fpu.fcvt := false.B 248 /* 249 vfmv.s.f 250 */ 251 csBundle(1).srcType(0) := SrcType.fp 252 csBundle(1).srcType(1) := SrcType.vp 253 csBundle(1).srcType(2) := SrcType.vp 254 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 255 csBundle(1).lsrc(1) := 0.U 256 csBundle(1).lsrc(2) := dest 257 csBundle(1).ldest := dest 258 csBundle(1).fuType := FuType.vppu.U 259 csBundle(1).fuOpType := VpermType.dummy 260 csBundle(1).rfWen := false.B 261 csBundle(1).fpWen := false.B 262 csBundle(1).vecWen := true.B 263 } 264 is(UopSplitType.VEC_VXV) { 265 /* 266 FMV.D.X 267 */ 268 csBundle(0).srcType(0) := SrcType.reg 269 csBundle(0).srcType(1) := SrcType.imm 270 csBundle(0).lsrc(1) := 0.U 271 csBundle(0).ldest := FP_TMP_REG_MV.U 272 csBundle(0).fuType := FuType.i2f.U 273 csBundle(0).rfWen := false.B 274 csBundle(0).fpWen := true.B 275 csBundle(0).vecWen := false.B 276 csBundle(0).fpu.isAddSub := false.B 277 csBundle(0).fpu.typeTagIn := FPU.D 278 csBundle(0).fpu.typeTagOut := FPU.D 279 csBundle(0).fpu.fromInt := true.B 280 csBundle(0).fpu.wflags := false.B 281 csBundle(0).fpu.fpWen := true.B 282 csBundle(0).fpu.div := false.B 283 csBundle(0).fpu.sqrt := false.B 284 csBundle(0).fpu.fcvt := false.B 285 /* 286 LMUL 287 */ 288 for (i <- 0 until MAX_VLMUL) { 289 csBundle(i + 1).srcType(0) := SrcType.fp 290 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 291 csBundle(i + 1).lsrc(1) := src2 + i.U 292 csBundle(i + 1).lsrc(2) := dest + i.U 293 csBundle(i + 1).ldest := dest + i.U 294 csBundle(i + 1).uopIdx := i.U 295 } 296 } 297 is(UopSplitType.VEC_VVW) { 298 for (i <- 0 until MAX_VLMUL / 2) { 299 csBundle(2 * i).lsrc(0) := src1 + i.U 300 csBundle(2 * i).lsrc(1) := src2 + i.U 301 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 302 csBundle(2 * i).ldest := dest + (2 * i).U 303 csBundle(2 * i).uopIdx := (2 * i).U 304 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 305 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 306 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 307 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 308 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 309 } 310 } 311 is(UopSplitType.VEC_WVW) { 312 for (i <- 0 until MAX_VLMUL / 2) { 313 csBundle(2 * i).lsrc(0) := src1 + i.U 314 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 315 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 316 csBundle(2 * i).ldest := dest + (2 * i).U 317 csBundle(2 * i).uopIdx := (2 * i).U 318 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 319 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 320 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 321 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 322 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 323 } 324 } 325 is(UopSplitType.VEC_VXW) { 326 /* 327 FMV.D.X 328 */ 329 csBundle(0).srcType(0) := SrcType.reg 330 csBundle(0).srcType(1) := SrcType.imm 331 csBundle(0).lsrc(1) := 0.U 332 csBundle(0).ldest := FP_TMP_REG_MV.U 333 csBundle(0).fuType := FuType.i2f.U 334 csBundle(0).rfWen := false.B 335 csBundle(0).fpWen := true.B 336 csBundle(0).vecWen := false.B 337 csBundle(0).fpu.isAddSub := false.B 338 csBundle(0).fpu.typeTagIn := FPU.D 339 csBundle(0).fpu.typeTagOut := FPU.D 340 csBundle(0).fpu.fromInt := true.B 341 csBundle(0).fpu.wflags := false.B 342 csBundle(0).fpu.fpWen := true.B 343 csBundle(0).fpu.div := false.B 344 csBundle(0).fpu.sqrt := false.B 345 csBundle(0).fpu.fcvt := false.B 346 347 for (i <- 0 until MAX_VLMUL / 2) { 348 csBundle(2 * i + 1).srcType(0) := SrcType.fp 349 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 350 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 351 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 352 csBundle(2 * i + 1).ldest := dest + (2 * i).U 353 csBundle(2 * i + 1).uopIdx := (2 * i).U 354 csBundle(2 * i + 2).srcType(0) := SrcType.fp 355 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 356 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 357 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 358 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 359 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 360 } 361 } 362 is(UopSplitType.VEC_WXW) { 363 /* 364 FMV.D.X 365 */ 366 csBundle(0).srcType(0) := SrcType.reg 367 csBundle(0).srcType(1) := SrcType.imm 368 csBundle(0).lsrc(1) := 0.U 369 csBundle(0).ldest := FP_TMP_REG_MV.U 370 csBundle(0).fuType := FuType.i2f.U 371 csBundle(0).rfWen := false.B 372 csBundle(0).fpWen := true.B 373 csBundle(0).vecWen := false.B 374 csBundle(0).fpu.isAddSub := false.B 375 csBundle(0).fpu.typeTagIn := FPU.D 376 csBundle(0).fpu.typeTagOut := FPU.D 377 csBundle(0).fpu.fromInt := true.B 378 csBundle(0).fpu.wflags := false.B 379 csBundle(0).fpu.fpWen := true.B 380 csBundle(0).fpu.div := false.B 381 csBundle(0).fpu.sqrt := false.B 382 csBundle(0).fpu.fcvt := false.B 383 384 for (i <- 0 until MAX_VLMUL / 2) { 385 csBundle(2 * i + 1).srcType(0) := SrcType.fp 386 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 387 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 388 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 389 csBundle(2 * i + 1).ldest := dest + (2 * i).U 390 csBundle(2 * i + 1).uopIdx := (2 * i).U 391 csBundle(2 * i + 2).srcType(0) := SrcType.fp 392 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 393 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 394 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 395 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 396 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 397 } 398 } 399 is(UopSplitType.VEC_WVV) { 400 for (i <- 0 until MAX_VLMUL / 2) { 401 402 csBundle(2 * i).lsrc(0) := src1 + i.U 403 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 404 csBundle(2 * i).lsrc(2) := dest + i.U 405 csBundle(2 * i).ldest := dest + i.U 406 csBundle(2 * i).uopIdx := (2 * i).U 407 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 408 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 409 csBundle(2 * i + 1).lsrc(2) := dest + i.U 410 csBundle(2 * i + 1).ldest := dest + i.U 411 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 412 } 413 } 414 is(UopSplitType.VEC_WXV) { 415 /* 416 FMV.D.X 417 */ 418 csBundle(0).srcType(0) := SrcType.reg 419 csBundle(0).srcType(1) := SrcType.imm 420 csBundle(0).lsrc(1) := 0.U 421 csBundle(0).ldest := FP_TMP_REG_MV.U 422 csBundle(0).fuType := FuType.i2f.U 423 csBundle(0).rfWen := false.B 424 csBundle(0).fpWen := true.B 425 csBundle(0).vecWen := false.B 426 csBundle(0).fpu.isAddSub := false.B 427 csBundle(0).fpu.typeTagIn := FPU.D 428 csBundle(0).fpu.typeTagOut := FPU.D 429 csBundle(0).fpu.fromInt := true.B 430 csBundle(0).fpu.wflags := false.B 431 csBundle(0).fpu.fpWen := true.B 432 csBundle(0).fpu.div := false.B 433 csBundle(0).fpu.sqrt := false.B 434 csBundle(0).fpu.fcvt := false.B 435 436 for (i <- 0 until MAX_VLMUL / 2) { 437 csBundle(2 * i + 1).srcType(0) := SrcType.fp 438 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 439 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 440 csBundle(2 * i + 1).lsrc(2) := dest + i.U 441 csBundle(2 * i + 1).ldest := dest + i.U 442 csBundle(2 * i + 1).uopIdx := (2 * i).U 443 csBundle(2 * i + 2).srcType(0) := SrcType.fp 444 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 445 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 446 csBundle(2 * i + 2).lsrc(2) := dest + i.U 447 csBundle(2 * i + 2).ldest := dest + i.U 448 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 449 } 450 } 451 is(UopSplitType.VEC_VVM) { 452 csBundle(0).lsrc(2) := dest 453 csBundle(0).ldest := dest 454 csBundle(0).uopIdx := 0.U 455 for (i <- 1 until MAX_VLMUL) { 456 csBundle(i).lsrc(0) := src1 + i.U 457 csBundle(i).lsrc(1) := src2 + i.U 458 csBundle(i).lsrc(2) := dest 459 csBundle(i).ldest := dest 460 csBundle(i).uopIdx := i.U 461 } 462 csBundle(numOfUop - 1.U).ldest := dest 463 } 464 is(UopSplitType.VEC_VXM) { 465 /* 466 FMV.D.X 467 */ 468 csBundle(0).srcType(0) := SrcType.reg 469 csBundle(0).srcType(1) := SrcType.imm 470 csBundle(0).lsrc(1) := 0.U 471 csBundle(0).ldest := FP_TMP_REG_MV.U 472 csBundle(0).fuType := FuType.i2f.U 473 csBundle(0).rfWen := false.B 474 csBundle(0).fpWen := true.B 475 csBundle(0).vecWen := false.B 476 csBundle(0).fpu.isAddSub := false.B 477 csBundle(0).fpu.typeTagIn := FPU.D 478 csBundle(0).fpu.typeTagOut := FPU.D 479 csBundle(0).fpu.fromInt := true.B 480 csBundle(0).fpu.wflags := false.B 481 csBundle(0).fpu.fpWen := true.B 482 csBundle(0).fpu.div := false.B 483 csBundle(0).fpu.sqrt := false.B 484 csBundle(0).fpu.fcvt := false.B 485 //LMUL 486 csBundle(1).srcType(0) := SrcType.fp 487 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 488 csBundle(1).lsrc(2) := dest 489 csBundle(1).ldest := dest 490 csBundle(1).uopIdx := 0.U 491 for (i <- 1 until MAX_VLMUL) { 492 csBundle(i + 1).srcType(0) := SrcType.fp 493 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 494 csBundle(i + 1).lsrc(1) := src2 + i.U 495 csBundle(i + 1).lsrc(2) := dest 496 csBundle(i + 1).ldest := dest 497 csBundle(i + 1).uopIdx := i.U 498 } 499 csBundle(numOfUop - 1.U).ldest := dest 500 } 501 is(UopSplitType.VEC_SLIDE1UP) { 502 /* 503 FMV.D.X 504 */ 505 csBundle(0).srcType(0) := SrcType.reg 506 csBundle(0).srcType(1) := SrcType.imm 507 csBundle(0).lsrc(1) := 0.U 508 csBundle(0).ldest := FP_TMP_REG_MV.U 509 csBundle(0).fuType := FuType.i2f.U 510 csBundle(0).rfWen := false.B 511 csBundle(0).fpWen := true.B 512 csBundle(0).vecWen := false.B 513 csBundle(0).fpu.isAddSub := false.B 514 csBundle(0).fpu.typeTagIn := FPU.D 515 csBundle(0).fpu.typeTagOut := FPU.D 516 csBundle(0).fpu.fromInt := true.B 517 csBundle(0).fpu.wflags := false.B 518 csBundle(0).fpu.fpWen := true.B 519 csBundle(0).fpu.div := false.B 520 csBundle(0).fpu.sqrt := false.B 521 csBundle(0).fpu.fcvt := false.B 522 //LMUL 523 csBundle(1).srcType(0) := SrcType.fp 524 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 525 csBundle(1).lsrc(2) := dest 526 csBundle(1).ldest := dest 527 csBundle(1).uopIdx := 0.U 528 for (i <- 1 until MAX_VLMUL) { 529 csBundle(i + 1).srcType(0) := SrcType.vp 530 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 531 csBundle(i + 1).lsrc(1) := src2 + i.U 532 csBundle(i + 1).lsrc(2) := dest + i.U 533 csBundle(i + 1).ldest := dest + i.U 534 csBundle(i + 1).uopIdx := i.U 535 } 536 } 537 is(UopSplitType.VEC_FSLIDE1UP) { 538 //LMUL 539 csBundle(0).srcType(0) := SrcType.fp 540 csBundle(0).lsrc(0) := src1 541 csBundle(0).lsrc(1) := src2 542 csBundle(0).lsrc(2) := dest 543 csBundle(0).ldest := dest 544 csBundle(0).uopIdx := 0.U 545 for (i <- 1 until MAX_VLMUL) { 546 csBundle(i).srcType(0) := SrcType.vp 547 csBundle(i).lsrc(0) := src2 + (i - 1).U 548 csBundle(i).lsrc(1) := src2 + i.U 549 csBundle(i).lsrc(2) := dest + i.U 550 csBundle(i).ldest := dest + i.U 551 csBundle(i).uopIdx := i.U 552 } 553 } 554 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 555 /* 556 FMV.D.X 557 */ 558 csBundle(0).srcType(0) := SrcType.reg 559 csBundle(0).srcType(1) := SrcType.imm 560 csBundle(0).lsrc(1) := 0.U 561 csBundle(0).ldest := FP_TMP_REG_MV.U 562 csBundle(0).fuType := FuType.i2f.U 563 csBundle(0).rfWen := false.B 564 csBundle(0).fpWen := true.B 565 csBundle(0).vecWen := false.B 566 csBundle(0).fpu.isAddSub := false.B 567 csBundle(0).fpu.typeTagIn := FPU.D 568 csBundle(0).fpu.typeTagOut := FPU.D 569 csBundle(0).fpu.fromInt := true.B 570 csBundle(0).fpu.wflags := false.B 571 csBundle(0).fpu.fpWen := true.B 572 csBundle(0).fpu.div := false.B 573 csBundle(0).fpu.sqrt := false.B 574 csBundle(0).fpu.fcvt := false.B 575 //LMUL 576 for (i <- 0 until MAX_VLMUL) { 577 csBundle(2 * i + 1).srcType(0) := SrcType.vp 578 csBundle(2 * i + 1).srcType(1) := SrcType.vp 579 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 580 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 581 csBundle(2 * i + 1).lsrc(2) := dest + i.U 582 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 583 csBundle(2 * i + 1).uopIdx := (2 * i).U 584 if (2 * i + 2 < MAX_VLMUL * 2) { 585 csBundle(2 * i + 2).srcType(0) := SrcType.fp 586 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 587 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 588 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 589 csBundle(2 * i + 2).ldest := dest + i.U 590 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 591 } 592 } 593 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 594 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 595 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 596 } 597 is(UopSplitType.VEC_FSLIDE1DOWN) { 598 //LMUL 599 for (i <- 0 until MAX_VLMUL) { 600 csBundle(2 * i).srcType(0) := SrcType.vp 601 csBundle(2 * i).srcType(1) := SrcType.vp 602 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 603 csBundle(2 * i).lsrc(1) := src2 + i.U 604 csBundle(2 * i).lsrc(2) := dest + i.U 605 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 606 csBundle(2 * i).uopIdx := (2 * i).U 607 csBundle(2 * i + 1).srcType(0) := SrcType.fp 608 csBundle(2 * i + 1).lsrc(0) := src1 609 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 610 csBundle(2 * i + 1).ldest := dest + i.U 611 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 612 } 613 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 614 csBundle(numOfUop - 1.U).lsrc(0) := src1 615 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 616 } 617 is(UopSplitType.VEC_VRED) { 618 when(simple.io.enq.vtype.vlmul === "b001".U) { 619 csBundle(0).srcType(2) := SrcType.DC 620 csBundle(0).lsrc(0) := src2 + 1.U 621 csBundle(0).lsrc(1) := src2 622 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 623 csBundle(0).uopIdx := 0.U 624 } 625 when(simple.io.enq.vtype.vlmul === "b010".U) { 626 csBundle(0).srcType(2) := SrcType.DC 627 csBundle(0).lsrc(0) := src2 + 1.U 628 csBundle(0).lsrc(1) := src2 629 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 630 csBundle(0).uopIdx := 0.U 631 632 csBundle(1).srcType(2) := SrcType.DC 633 csBundle(1).lsrc(0) := src2 + 3.U 634 csBundle(1).lsrc(1) := src2 + 2.U 635 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 636 csBundle(1).uopIdx := 1.U 637 638 csBundle(2).srcType(2) := SrcType.DC 639 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 640 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 641 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 642 csBundle(2).uopIdx := 2.U 643 } 644 when(simple.io.enq.vtype.vlmul === "b011".U) { 645 for (i <- 0 until MAX_VLMUL) { 646 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 647 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 648 csBundle(i).lsrc(1) := src2 + (i * 2).U 649 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 650 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 651 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 652 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 653 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 654 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 655 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 656 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 657 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 658 } 659 csBundle(i).srcType(2) := SrcType.DC 660 csBundle(i).uopIdx := i.U 661 } 662 } 663 when(simple.io.enq.vtype.vlmul.orR()) { 664 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 665 csBundle(numOfUop - 1.U).lsrc(0) := src1 666 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 667 csBundle(numOfUop - 1.U).lsrc(2) := dest 668 csBundle(numOfUop - 1.U).ldest := dest 669 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 670 } 671 } 672 673 is(UopSplitType.VEC_SLIDEUP) { 674 // FMV.D.X 675 csBundle(0).srcType(0) := SrcType.reg 676 csBundle(0).srcType(1) := SrcType.imm 677 csBundle(0).lsrc(1) := 0.U 678 csBundle(0).ldest := FP_TMP_REG_MV.U 679 csBundle(0).fuType := FuType.i2f.U 680 csBundle(0).rfWen := false.B 681 csBundle(0).fpWen := true.B 682 csBundle(0).vecWen := false.B 683 csBundle(0).fpu.isAddSub := false.B 684 csBundle(0).fpu.typeTagIn := FPU.D 685 csBundle(0).fpu.typeTagOut := FPU.D 686 csBundle(0).fpu.fromInt := true.B 687 csBundle(0).fpu.wflags := false.B 688 csBundle(0).fpu.fpWen := true.B 689 csBundle(0).fpu.div := false.B 690 csBundle(0).fpu.sqrt := false.B 691 csBundle(0).fpu.fcvt := false.B 692 // LMUL 693 for (i <- 0 until MAX_VLMUL) 694 for (j <- 0 to i) { 695 val old_vd = if (j == 0) { 696 dest + i.U 697 } else (VECTOR_TMP_REG_LMUL + j - 1).U 698 val vd = if (j == i) { 699 dest + i.U 700 } else (VECTOR_TMP_REG_LMUL + j).U 701 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.fp 702 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := FP_TMP_REG_MV.U 703 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 704 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 705 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 706 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 707 } 708 } 709 710 is(UopSplitType.VEC_ISLIDEUP) { 711 // LMUL 712 for (i <- 0 until MAX_VLMUL) 713 for (j <- 0 to i) { 714 val old_vd = if (j == 0) { 715 dest + i.U 716 } else (VECTOR_TMP_REG_LMUL + j - 1).U 717 val vd = if (j == i) { 718 dest + i.U 719 } else (VECTOR_TMP_REG_LMUL + j).U 720 csBundle(i * (i + 1) / 2 + j).lsrc(1) := src2 + j.U 721 csBundle(i * (i + 1) / 2 + j).lsrc(2) := old_vd 722 csBundle(i * (i + 1) / 2 + j).ldest := vd 723 csBundle(i * (i + 1) / 2 + j).uopIdx := (i * (i + 1) / 2 + j).U 724 } 725 } 726 727 is(UopSplitType.VEC_SLIDEDOWN) { 728 // FMV.D.X 729 csBundle(0).srcType(0) := SrcType.reg 730 csBundle(0).srcType(1) := SrcType.imm 731 csBundle(0).lsrc(1) := 0.U 732 csBundle(0).ldest := FP_TMP_REG_MV.U 733 csBundle(0).fuType := FuType.i2f.U 734 csBundle(0).rfWen := false.B 735 csBundle(0).fpWen := true.B 736 csBundle(0).vecWen := false.B 737 csBundle(0).fpu.isAddSub := false.B 738 csBundle(0).fpu.typeTagIn := FPU.D 739 csBundle(0).fpu.typeTagOut := FPU.D 740 csBundle(0).fpu.fromInt := true.B 741 csBundle(0).fpu.wflags := false.B 742 csBundle(0).fpu.fpWen := true.B 743 csBundle(0).fpu.div := false.B 744 csBundle(0).fpu.sqrt := false.B 745 csBundle(0).fpu.fcvt := false.B 746 // LMUL 747 for (i <- 0 until MAX_VLMUL) 748 for (j <- (0 to i).reverse) { 749 when(i.U < lmul) { 750 val old_vd = if (j == 0) { 751 dest + lmul - 1.U - i.U 752 } else (VECTOR_TMP_REG_LMUL + j - 1).U 753 val vd = if (j == i) { 754 dest + lmul - 1.U - i.U 755 } else (VECTOR_TMP_REG_LMUL + j).U 756 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.fp 757 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := FP_TMP_REG_MV.U 758 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 759 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 760 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 761 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 762 } 763 } 764 } 765 766 is(UopSplitType.VEC_ISLIDEDOWN) { 767 // LMUL 768 for (i <- 0 until MAX_VLMUL) 769 for (j <- (0 to i).reverse) { 770 when(i.U < lmul) { 771 val old_vd = if (j == 0) { 772 dest + lmul - 1.U - i.U 773 } else (VECTOR_TMP_REG_LMUL + j - 1).U 774 val vd = if (j == i) { 775 dest + lmul - 1.U - i.U 776 } else (VECTOR_TMP_REG_LMUL + j).U 777 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 778 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 779 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 780 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 1).U 781 } 782 } 783 } 784 785 is(UopSplitType.VEC_M0X) { 786 // LMUL 787 for (i <- 0 until MAX_VLMUL) { 788 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 789 val ldest = (VECTOR_TMP_REG_LMUL + i).U 790 csBundle(i).srcType(0) := srcType0 791 csBundle(i).srcType(1) := SrcType.vp 792 csBundle(i).rfWen := false.B 793 csBundle(i).vecWen := true.B 794 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 795 csBundle(i).lsrc(1) := src2 796 // csBundle(i).lsrc(2) := dest + i.U DontCare 797 csBundle(i).ldest := ldest 798 csBundle(i).uopIdx := i.U 799 } 800 csBundle(lmul - 1.U).vecWen := false.B 801 csBundle(lmul - 1.U).fpWen := true.B 802 csBundle(lmul - 1.U).ldest := FP_TMP_REG_MV.U 803 // FMV_X_D 804 csBundle(lmul).srcType(0) := SrcType.fp 805 csBundle(lmul).srcType(1) := SrcType.imm 806 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 807 csBundle(lmul).lsrc(1) := 0.U 808 csBundle(lmul).ldest := dest 809 csBundle(lmul).fuType := FuType.fmisc.U 810 csBundle(lmul).rfWen := true.B 811 csBundle(lmul).fpWen := false.B 812 csBundle(lmul).vecWen := false.B 813 csBundle(lmul).fpu.isAddSub := false.B 814 csBundle(lmul).fpu.typeTagIn := FPU.D 815 csBundle(lmul).fpu.typeTagOut := FPU.D 816 csBundle(lmul).fpu.fromInt := false.B 817 csBundle(lmul).fpu.wflags := false.B 818 csBundle(lmul).fpu.fpWen := false.B 819 csBundle(lmul).fpu.div := false.B 820 csBundle(lmul).fpu.sqrt := false.B 821 csBundle(lmul).fpu.fcvt := false.B 822 } 823 824 is(UopSplitType.VEC_MVV) { 825 // LMUL 826 for (i <- 0 until MAX_VLMUL) { 827 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 828 csBundle(i * 2 + 0).srcType(0) := srcType0 829 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 830 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 831 csBundle(i * 2 + 0).lsrc(1) := src2 832 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 833 csBundle(i * 2 + 0).ldest := dest + i.U 834 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 835 836 csBundle(i * 2 + 1).srcType(0) := srcType0 837 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 838 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 839 csBundle(i * 2 + 1).lsrc(1) := src2 840 // csBundle(i).lsrc(2) := dest + i.U DontCare 841 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 842 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 843 } 844 } 845 846 is(UopSplitType.VEC_M0X_VFIRST) { 847 // LMUL 848 csBundle(0).rfWen := false.B 849 csBundle(0).fpWen := true.B 850 csBundle(0).ldest := FP_TMP_REG_MV.U 851 // FMV_X_D 852 csBundle(1).srcType(0) := SrcType.fp 853 csBundle(1).srcType(1) := SrcType.imm 854 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 855 csBundle(1).lsrc(1) := 0.U 856 csBundle(1).ldest := dest 857 csBundle(1).fuType := FuType.fmisc.U 858 csBundle(1).rfWen := true.B 859 csBundle(1).fpWen := false.B 860 csBundle(1).vecWen := false.B 861 csBundle(1).fpu.isAddSub := false.B 862 csBundle(1).fpu.typeTagIn := FPU.D 863 csBundle(1).fpu.typeTagOut := FPU.D 864 csBundle(1).fpu.fromInt := false.B 865 csBundle(1).fpu.wflags := false.B 866 csBundle(1).fpu.fpWen := false.B 867 csBundle(1).fpu.div := false.B 868 csBundle(1).fpu.sqrt := false.B 869 csBundle(1).fpu.fcvt := false.B 870 } 871 is(UopSplitType.VEC_VWW) { 872 for (i <- 0 until MAX_VLMUL*2) { 873 when(i.U < lmul){ 874 csBundle(i).srcType(2) := SrcType.DC 875 csBundle(i).lsrc(0) := src2 + i.U 876 csBundle(i).lsrc(1) := src2 + i.U 877 // csBundle(i).lsrc(2) := dest + (2 * i).U 878 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 879 csBundle(i).uopIdx := i.U 880 } otherwise { 881 csBundle(i).srcType(2) := SrcType.DC 882 csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 883 csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 884 // csBundle(i).lsrc(2) := dest + (2 * i).U 885 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 886 csBundle(i).uopIdx := i.U 887 } 888 csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 889 csBundle(numOfUop-1.U).lsrc(0) := src1 890 csBundle(numOfUop-1.U).lsrc(2) := dest 891 csBundle(numOfUop-1.U).ldest := dest 892 } 893 } 894 is(UopSplitType.VEC_RGATHER) { 895 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 896 for (i <- 0 until len) 897 for (j <- 0 until len) { 898 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 899 // csBundle(i * len + j).srcType(1) := SrcType.vp 900 // csBundle(i * len + j).srcType(2) := SrcType.vp 901 csBundle(i * len + j).lsrc(0) := src1 + i.U 902 csBundle(i * len + j).lsrc(1) := src2 + j.U 903 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 904 csBundle(i * len + j).lsrc(2) := vd_old 905 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 906 csBundle(i * len + j).ldest := vd 907 csBundle(i * len + j).uopIdx := (i * len + j).U 908 } 909 } 910 switch(simple.io.enq.vtype.vlmul) { 911 is("b001".U ){ 912 genCsBundle_VEC_RGATHER(2) 913 } 914 is("b010".U ){ 915 genCsBundle_VEC_RGATHER(4) 916 } 917 is("b011".U ){ 918 genCsBundle_VEC_RGATHER(8) 919 } 920 } 921 } 922 is(UopSplitType.VEC_RGATHER_VX) { 923 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 924 for (i <- 0 until len) 925 for (j <- 0 until len) { 926 csBundle(i * len + j + 1).srcType(0) := SrcType.fp 927 // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 928 // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 929 csBundle(i * len + j + 1).lsrc(0) := FP_TMP_REG_MV.U 930 csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 931 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 932 csBundle(i * len + j + 1).lsrc(2) := vd_old 933 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 934 csBundle(i * len + j + 1).ldest := vd 935 csBundle(i * len + j + 1).uopIdx := (i * len + j).U 936 } 937 } 938 // FMV.D.X 939 csBundle(0).srcType(0) := SrcType.reg 940 csBundle(0).srcType(1) := SrcType.imm 941 csBundle(0).lsrc(1) := 0.U 942 csBundle(0).ldest := FP_TMP_REG_MV.U 943 csBundle(0).fuType := FuType.i2f.U 944 csBundle(0).rfWen := false.B 945 csBundle(0).fpWen := true.B 946 csBundle(0).vecWen := false.B 947 csBundle(0).fpu.isAddSub := false.B 948 csBundle(0).fpu.typeTagIn := FPU.D 949 csBundle(0).fpu.typeTagOut := FPU.D 950 csBundle(0).fpu.fromInt := true.B 951 csBundle(0).fpu.wflags := false.B 952 csBundle(0).fpu.fpWen := true.B 953 csBundle(0).fpu.div := false.B 954 csBundle(0).fpu.sqrt := false.B 955 csBundle(0).fpu.fcvt := false.B 956 switch(simple.io.enq.vtype.vlmul) { 957 is("b000".U ){ 958 genCsBundle_RGATHER_VX(1) 959 } 960 is("b001".U ){ 961 genCsBundle_RGATHER_VX(2) 962 } 963 is("b010".U ){ 964 genCsBundle_RGATHER_VX(4) 965 } 966 is("b011".U ){ 967 genCsBundle_RGATHER_VX(8) 968 } 969 } 970 } 971 is(UopSplitType.VEC_RGATHEREI16) { 972 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 973 for (i <- 0 until len) 974 for (j <- 0 until len) { 975 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 976 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 977 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 978 // csBundle(i * len + j).srcType(1) := SrcType.vp 979 // csBundle(i * len + j).srcType(2) := SrcType.vp 980 csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 981 csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 982 csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 983 csBundle((i * len + j)*2+0).ldest := vd0 984 csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 985 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 986 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 987 csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 988 csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 989 csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 990 csBundle((i * len + j)*2+1).ldest := vd1 991 csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 992 } 993 } 994 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 995 for (i <- 0 until len) 996 for (j <- 0 until len) { 997 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 998 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 999 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1000 // csBundle(i * len + j).srcType(1) := SrcType.vp 1001 // csBundle(i * len + j).srcType(2) := SrcType.vp 1002 csBundle(i * len + j).lsrc(0) := src1 + i.U 1003 csBundle(i * len + j).lsrc(1) := src2 + j.U 1004 csBundle(i * len + j).lsrc(2) := vd_old 1005 csBundle(i * len + j).ldest := vd 1006 csBundle(i * len + j).uopIdx := (i * len + j).U 1007 } 1008 } 1009 switch(simple.io.enq.vtype.vlmul) { 1010 is("b000".U ){ 1011 when(!simple.io.enq.vtype.vsew.orR){ 1012 genCsBundle_VEC_RGATHEREI16_SEW8(1) 1013 } .otherwise{ 1014 genCsBundle_VEC_RGATHEREI16(1) 1015 } 1016 } 1017 is("b001".U) { 1018 when(!simple.io.enq.vtype.vsew.orR) { 1019 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1020 }.otherwise { 1021 genCsBundle_VEC_RGATHEREI16(2) 1022 } 1023 } 1024 is("b010".U) { 1025 when(!simple.io.enq.vtype.vsew.orR) { 1026 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1027 }.otherwise { 1028 genCsBundle_VEC_RGATHEREI16(4) 1029 } 1030 } 1031 is("b011".U) { 1032 genCsBundle_VEC_RGATHEREI16(8) 1033 } 1034 } 1035 } 1036 is(UopSplitType.VEC_COMPRESS) { 1037 def genCsBundle_VEC_COMPRESS(len:Int): Unit ={ 1038 for (i <- 0 until len){ 1039 val jlen = if (i == len-1) i+1 else i+2 1040 for (j <- 0 until jlen) { 1041 val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1042 val vd = if(i==len-1) (dest + j.U) else{ 1043 if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1044 } 1045 val src23Type = if (j == i+1) DontCare else SrcType.vp 1046 csBundle(i*(i+3)/2 + j).srcType(0) := SrcType.vp 1047 csBundle(i*(i+3)/2 + j).srcType(1) := src23Type 1048 csBundle(i*(i+3)/2 + j).srcType(2) := src23Type 1049 csBundle(i*(i+3)/2 + j).lsrc(0) := src1 1050 csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1051 csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1052 // csBundle(i*(i+3)/2 + j).lsrc(3) := VECTOR_TMP_REG_LMUL.U 1053 csBundle(i*(i+3)/2 + j).ldest := vd 1054 csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1055 } 1056 } 1057 } 1058 switch(simple.io.enq.vtype.vlmul) { 1059 is("b001".U ){ 1060 genCsBundle_VEC_COMPRESS(2) 1061 } 1062 is("b010".U ){ 1063 genCsBundle_VEC_COMPRESS(4) 1064 } 1065 is("b011".U ){ 1066 genCsBundle_VEC_COMPRESS(8) 1067 } 1068 } 1069 } 1070 is(UopSplitType.VEC_US_LD) { 1071 /* 1072 FMV.D.X 1073 */ 1074 csBundle(0).srcType(0) := SrcType.reg 1075 csBundle(0).srcType(1) := SrcType.imm 1076 csBundle(0).lsrc(1) := 0.U 1077 csBundle(0).ldest := FP_TMP_REG_MV.U 1078 csBundle(0).fuType := FuType.i2f.U 1079 csBundle(0).rfWen := false.B 1080 csBundle(0).fpWen := true.B 1081 csBundle(0).vecWen := false.B 1082 csBundle(0).fpu.isAddSub := false.B 1083 csBundle(0).fpu.typeTagIn := FPU.D 1084 csBundle(0).fpu.typeTagOut := FPU.D 1085 csBundle(0).fpu.fromInt := true.B 1086 csBundle(0).fpu.wflags := false.B 1087 csBundle(0).fpu.fpWen := true.B 1088 csBundle(0).fpu.div := false.B 1089 csBundle(0).fpu.sqrt := false.B 1090 csBundle(0).fpu.fcvt := false.B 1091 //LMUL 1092 for (i <- 0 until MAX_VLMUL) { 1093 csBundle(i + 1).srcType(0) := SrcType.fp 1094 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1095 csBundle(i + 1).ldest := dest + i.U 1096 csBundle(i + 1).uopIdx := i.U 1097 } 1098 } 1099 } 1100 1101 //uops dispatch 1102 val s_normal :: s_ext :: Nil = Enum(2) 1103 val state = RegInit(s_normal) 1104 val state_next = WireDefault(state) 1105 val uopRes = RegInit(0.U) 1106 1107 //readyFromRename Counter 1108 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 1109 1110 switch(state) { 1111 is(s_normal) { 1112 state_next := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), s_ext, s_normal) 1113 } 1114 is(s_ext) { 1115 state_next := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), s_ext, s_normal) 1116 } 1117 } 1118 1119 state := state_next 1120 1121 val uopRes0 = Mux(state === s_normal, numOfUop, uopRes) 1122 val uopResJudge = Mux(state === s_normal, 1123 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 1124 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 1125 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 1126 1127 for(i <- 0 until RenameWidth) { 1128 decodedInsts(i) := MuxCase(csBundle(i), Seq( 1129 (state === s_normal) -> csBundle(i), 1130 (state === s_ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 1131 )) 1132 } 1133 1134 1135 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 1136 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1137 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 1138 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1139 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1140 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1141 notInfVec(0) := true.B 1142 1143 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1144 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1145 1.U) 1146 validToRename.zipWithIndex.foreach{ 1147 case(dst, i) => 1148 dst := MuxCase(false.B, Seq( 1149 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 1150 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1151 )) 1152 } 1153 1154 readyToIBuf.zipWithIndex.foreach { 1155 case (dst, i) => 1156 dst := MuxCase(true.B, Seq( 1157 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 1158 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 1159 )) 1160 } 1161 1162 io.deq.decodedInsts := decodedInsts 1163 io.deq.isVset := isVsetSimple 1164 io.deq.complexNum := complexNum 1165 io.deq.validToRename := validToRename 1166 io.deq.readyToIBuf := readyToIBuf 1167 1168} 1169