1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VpermType 31import scala.collection.Seq 32 33trait VectorConstants { 34 val MAX_VLMUL = 8 35 val INT_VCONFIG = 32 36 val FP_TMP_REG_MV = 32 37 val VECTOR_TMP_REG_LMUL = 32 // 32~38 -> 7 38} 39 40class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 41 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 42 val vconfig = Input(new VConfig) 43 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 44 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 45 val readyFromRename = Input(Vec(RenameWidth, Bool())) 46 val deq = new Bundle { 47 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 48 val isVset = Output(Bool()) 49 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 50 val validToRename = Output(Vec(RenameWidth, Bool())) 51 val complexNum = Output(UInt(3.W)) 52 } 53 val csrCtrl = Input(new CustomCSRCtrlIO) 54} 55 56class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 57 val io = IO(new DecodeUnitCompIO) 58 //input bits 59 val ctrl_flow = Wire(new CtrlFlow) 60 ctrl_flow := io.enq.ctrl_flow 61 //output bits 62 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 63 val validToRename = Wire(Vec(RenameWidth, Bool())) 64 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 65 val complexNum = Wire(UInt(3.W)) 66 67 //output of DecodeUnit 68 val cf_ctrl_u = Wire(new CfCtrl) 69 val isVset_u = Wire(Bool()) 70 71 //pre decode 72 val simple = Module(new DecodeUnit) 73 simple.io.enq.ctrl_flow := ctrl_flow 74 simple.io.vconfig := io.vconfig 75 simple.io.csrCtrl := io.csrCtrl 76 cf_ctrl_u := simple.io.deq.cf_ctrl 77 isVset_u := simple.io.deq.isVset 78 79 //Type of uop Div 80 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 81 82 //LMUL 83 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(4.W), Array( 84 "b001".U -> 2.U, 85 "b010".U -> 4.U, 86 "b011".U -> 8.U 87 )) 88 val numOfUopVslide = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(log2Up(maxNumOfUop+1).W), Array( 89 "b001".U -> 3.U, 90 "b010".U -> 10.U, 91 "b011".U -> 36.U 92 )) 93 //number of uop 94 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxNumOfUop+1).W), Array( 95 UopDivType.VEC_0XV -> 2.U, 96 UopDivType.DIR -> 2.U, 97 UopDivType.VEC_VVV -> lmul, 98 UopDivType.VEC_EXT2 -> lmul, 99 UopDivType.VEC_EXT4 -> lmul, 100 UopDivType.VEC_EXT8 -> lmul, 101 UopDivType.VEC_VVM -> lmul, 102 UopDivType.VEC_VXM -> (lmul +& 1.U), 103 UopDivType.VEC_VXV -> (lmul +& 1.U), 104 UopDivType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 105 UopDivType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 106 UopDivType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 107 UopDivType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 108 UopDivType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 109 UopDivType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 110 UopDivType.VEC_SLIDE1UP -> (lmul +& 1.U), 111 UopDivType.VEC_FSLIDE1UP -> lmul, 112 UopDivType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 113 UopDivType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 114 UopDivType.VEC_VRED -> lmul, 115 UopDivType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 116 UopDivType.VEC_ISLIDEUP -> numOfUopVslide, 117 UopDivType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 118 UopDivType.VEC_ISLIDEDOWN -> numOfUopVslide, 119 UopDivType.VEC_0MX -> (lmul +& 1.U), 120 UopDivType.VEC_VMV -> (Cat(lmul, 0.U(1.W)) -1.U), 121 )) 122 123 val src1 = Cat(0.U(1.W), ctrl_flow.instr(19, 15)) 124 val src2 = Cat(0.U(1.W), ctrl_flow.instr(24, 20)) 125 val dest = Cat(0.U(1.W), ctrl_flow.instr(11, 7 )) 126 127 //uop div up to maxNumOfUop 128 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 129 csBundle.map { case dst => 130 dst := cf_ctrl_u 131 dst.ctrl.firstUop := false.B 132 dst.ctrl.lastUop := false.B 133 } 134 135 csBundle(0).ctrl.firstUop := true.B 136 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 137 138 switch(typeOfDiv) { 139 is(UopDivType.DIR) { 140 when(isVset_u) { 141 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR || ALUOpType.isVsetvl(cf_ctrl_u.ctrl.fuOpType) 142 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 143 csBundle(1).ctrl.ldest := INT_VCONFIG.U 144 csBundle(1).ctrl.flushPipe := false.B 145 } 146 } 147 is(UopDivType.VEC_VVV) { 148 for (i <- 0 until MAX_VLMUL) { 149 csBundle(i).ctrl.lsrc(0) := src1 + i.U 150 csBundle(i).ctrl.lsrc(1) := src2 + i.U 151 csBundle(i).ctrl.lsrc(2) := dest + i.U 152 csBundle(i).ctrl.ldest := dest + i.U 153 csBundle(i).ctrl.uopIdx := i.U 154 } 155 } 156 is(UopDivType.VEC_EXT2) { 157 for (i <- 0 until MAX_VLMUL / 2) { 158 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 159 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 160 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 161 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 162 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 163 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 164 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 165 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 166 } 167 } 168 is(UopDivType.VEC_EXT4) { 169 for (i <- 0 until MAX_VLMUL / 4) { 170 csBundle(4 * i).ctrl.lsrc(1) := src2 + i.U 171 csBundle(4 * i).ctrl.lsrc(2) := dest + (4 * i).U 172 csBundle(4 * i).ctrl.ldest := dest + (4 * i).U 173 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 174 csBundle(4 * i + 1).ctrl.lsrc(1) := src2 + i.U 175 csBundle(4 * i + 1).ctrl.lsrc(2) := dest + (4 * i + 1).U 176 csBundle(4 * i + 1).ctrl.ldest := dest + (4 * i + 1).U 177 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 178 csBundle(4 * i + 2).ctrl.lsrc(1) := src2 + i.U 179 csBundle(4 * i + 2).ctrl.lsrc(2) := dest + (4 * i + 2).U 180 csBundle(4 * i + 2).ctrl.ldest := dest + (4 * i + 2).U 181 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 182 csBundle(4 * i + 3).ctrl.lsrc(1) := src2 + i.U 183 csBundle(4 * i + 3).ctrl.lsrc(2) := dest + (4 * i + 3).U 184 csBundle(4 * i + 3).ctrl.ldest := dest + (4 * i + 3).U 185 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 186 } 187 } 188 is(UopDivType.VEC_EXT8) { 189 for (i <- 0 until MAX_VLMUL) { 190 csBundle(i).ctrl.lsrc(1) := src2 191 csBundle(i).ctrl.lsrc(2) := dest + i.U 192 csBundle(i).ctrl.ldest := dest + i.U 193 csBundle(i).ctrl.uopIdx := i.U 194 } 195 } 196 is(UopDivType.VEC_0XV) { 197 /* 198 FMV.D.X 199 */ 200 csBundle(0).ctrl.srcType(0) := SrcType.reg 201 csBundle(0).ctrl.srcType(1) := SrcType.imm 202 csBundle(0).ctrl.lsrc(1) := 0.U 203 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 204 csBundle(0).ctrl.fuType := FuType.i2f 205 csBundle(0).ctrl.rfWen := false.B 206 csBundle(0).ctrl.fpWen := true.B 207 csBundle(0).ctrl.vecWen := false.B 208 csBundle(0).ctrl.fpu.isAddSub := false.B 209 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 210 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 211 csBundle(0).ctrl.fpu.fromInt := true.B 212 csBundle(0).ctrl.fpu.wflags := false.B 213 csBundle(0).ctrl.fpu.fpWen := true.B 214 csBundle(0).ctrl.fpu.div := false.B 215 csBundle(0).ctrl.fpu.sqrt := false.B 216 csBundle(0).ctrl.fpu.fcvt := false.B 217 /* 218 vfmv.s.f 219 */ 220 csBundle(1).ctrl.srcType(0) := SrcType.fp 221 csBundle(1).ctrl.srcType(1) := SrcType.vp 222 csBundle(1).ctrl.srcType(2) := SrcType.vp 223 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 224 csBundle(1).ctrl.lsrc(1) := 0.U 225 csBundle(1).ctrl.lsrc(2) := dest 226 csBundle(1).ctrl.ldest := dest 227 csBundle(1).ctrl.fuType := FuType.vppu 228 csBundle(1).ctrl.fuOpType := VpermType.vfmv_s_f 229 csBundle(1).ctrl.rfWen := false.B 230 csBundle(1).ctrl.fpWen := false.B 231 csBundle(1).ctrl.vecWen := true.B 232 } 233 is(UopDivType.VEC_VXV) { 234 /* 235 FMV.D.X 236 */ 237 csBundle(0).ctrl.srcType(0) := SrcType.reg 238 csBundle(0).ctrl.srcType(1) := SrcType.imm 239 csBundle(0).ctrl.lsrc(1) := 0.U 240 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 241 csBundle(0).ctrl.fuType := FuType.i2f 242 csBundle(0).ctrl.rfWen := false.B 243 csBundle(0).ctrl.fpWen := true.B 244 csBundle(0).ctrl.vecWen := false.B 245 csBundle(0).ctrl.fpu.isAddSub := false.B 246 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 247 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 248 csBundle(0).ctrl.fpu.fromInt := true.B 249 csBundle(0).ctrl.fpu.wflags := false.B 250 csBundle(0).ctrl.fpu.fpWen := true.B 251 csBundle(0).ctrl.fpu.div := false.B 252 csBundle(0).ctrl.fpu.sqrt := false.B 253 csBundle(0).ctrl.fpu.fcvt := false.B 254 /* 255 LMUL 256 */ 257 for (i <- 0 until MAX_VLMUL) { 258 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 259 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 260 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 261 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 262 csBundle(i + 1).ctrl.ldest := dest + i.U 263 csBundle(i + 1).ctrl.uopIdx := i.U 264 } 265 } 266 is(UopDivType.VEC_VVW) { 267 for (i <- 0 until MAX_VLMUL / 2) { 268 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 269 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 270 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 271 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 272 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 273 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 274 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 275 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 276 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 277 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 278 } 279 } 280 is(UopDivType.VEC_WVW) { 281 for (i <- 0 until MAX_VLMUL / 2) { 282 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 283 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 284 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 285 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 286 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 287 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 288 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 289 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 290 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 291 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 292 } 293 } 294 is(UopDivType.VEC_VXW) { 295 /* 296 FMV.D.X 297 */ 298 csBundle(0).ctrl.srcType(0) := SrcType.reg 299 csBundle(0).ctrl.srcType(1) := SrcType.imm 300 csBundle(0).ctrl.lsrc(1) := 0.U 301 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 302 csBundle(0).ctrl.fuType := FuType.i2f 303 csBundle(0).ctrl.rfWen := false.B 304 csBundle(0).ctrl.fpWen := true.B 305 csBundle(0).ctrl.vecWen := false.B 306 csBundle(0).ctrl.fpu.isAddSub := false.B 307 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 308 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 309 csBundle(0).ctrl.fpu.fromInt := true.B 310 csBundle(0).ctrl.fpu.wflags := false.B 311 csBundle(0).ctrl.fpu.fpWen := true.B 312 csBundle(0).ctrl.fpu.div := false.B 313 csBundle(0).ctrl.fpu.sqrt := false.B 314 csBundle(0).ctrl.fpu.fcvt := false.B 315 316 for (i <- 0 until MAX_VLMUL / 2) { 317 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 318 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 319 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 320 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 321 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 322 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 323 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 324 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 325 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U 326 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 327 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 328 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 329 } 330 } 331 is(UopDivType.VEC_WXW) { 332 /* 333 FMV.D.X 334 */ 335 csBundle(0).ctrl.srcType(0) := SrcType.reg 336 csBundle(0).ctrl.srcType(1) := SrcType.imm 337 csBundle(0).ctrl.lsrc(1) := 0.U 338 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 339 csBundle(0).ctrl.fuType := FuType.i2f 340 csBundle(0).ctrl.rfWen := false.B 341 csBundle(0).ctrl.fpWen := true.B 342 csBundle(0).ctrl.vecWen := false.B 343 csBundle(0).ctrl.fpu.isAddSub := false.B 344 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 345 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 346 csBundle(0).ctrl.fpu.fromInt := true.B 347 csBundle(0).ctrl.fpu.wflags := false.B 348 csBundle(0).ctrl.fpu.fpWen := true.B 349 csBundle(0).ctrl.fpu.div := false.B 350 csBundle(0).ctrl.fpu.sqrt := false.B 351 csBundle(0).ctrl.fpu.fcvt := false.B 352 353 for (i <- 0 until MAX_VLMUL / 2) { 354 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 355 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 356 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 357 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 358 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 359 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 360 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 361 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 362 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 363 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 364 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 365 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 366 } 367 } 368 is(UopDivType.VEC_WVV) { 369 for (i <- 0 until MAX_VLMUL / 2) { 370 371 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 372 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 373 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 374 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 375 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 376 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 377 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 378 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 379 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 380 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 381 } 382 } 383 is(UopDivType.VEC_WXV) { 384 /* 385 FMV.D.X 386 */ 387 csBundle(0).ctrl.srcType(0) := SrcType.reg 388 csBundle(0).ctrl.srcType(1) := SrcType.imm 389 csBundle(0).ctrl.lsrc(1) := 0.U 390 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 391 csBundle(0).ctrl.fuType := FuType.i2f 392 csBundle(0).ctrl.rfWen := false.B 393 csBundle(0).ctrl.fpWen := true.B 394 csBundle(0).ctrl.vecWen := false.B 395 csBundle(0).ctrl.fpu.isAddSub := false.B 396 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 397 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 398 csBundle(0).ctrl.fpu.fromInt := true.B 399 csBundle(0).ctrl.fpu.wflags := false.B 400 csBundle(0).ctrl.fpu.fpWen := true.B 401 csBundle(0).ctrl.fpu.div := false.B 402 csBundle(0).ctrl.fpu.sqrt := false.B 403 csBundle(0).ctrl.fpu.fcvt := false.B 404 405 for (i <- 0 until MAX_VLMUL / 2) { 406 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 407 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 408 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 409 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 410 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 411 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 412 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 413 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 414 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 415 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 416 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 417 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 418 } 419 } 420 is(UopDivType.VEC_VVM) { 421 csBundle(0).ctrl.lsrc(2) := dest 422 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 423 csBundle(0).ctrl.uopIdx := 0.U 424 for(i <- 1 until MAX_VLMUL) { 425 csBundle(i).ctrl.lsrc(0) := src1 + i.U 426 csBundle(i).ctrl.lsrc(1) := src2 + i.U 427 csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 428 csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 429 csBundle(i).ctrl.uopIdx := i.U 430 } 431 csBundle(numOfUop - 1.U).ctrl.ldest := dest 432 } 433 is(UopDivType.VEC_VXM) { 434 /* 435 FMV.D.X 436 */ 437 csBundle(0).ctrl.srcType(0) := SrcType.reg 438 csBundle(0).ctrl.srcType(1) := SrcType.imm 439 csBundle(0).ctrl.lsrc(1) := 0.U 440 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 441 csBundle(0).ctrl.fuType := FuType.i2f 442 csBundle(0).ctrl.rfWen := false.B 443 csBundle(0).ctrl.fpWen := true.B 444 csBundle(0).ctrl.vecWen := false.B 445 csBundle(0).ctrl.fpu.isAddSub := false.B 446 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 447 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 448 csBundle(0).ctrl.fpu.fromInt := true.B 449 csBundle(0).ctrl.fpu.wflags := false.B 450 csBundle(0).ctrl.fpu.fpWen := true.B 451 csBundle(0).ctrl.fpu.div := false.B 452 csBundle(0).ctrl.fpu.sqrt := false.B 453 csBundle(0).ctrl.fpu.fcvt := false.B 454 //LMUL 455 csBundle(1).ctrl.srcType(0) := SrcType.fp 456 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 457 csBundle(1).ctrl.lsrc(2) := dest 458 csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 459 csBundle(1).ctrl.uopIdx := 0.U 460 for (i <- 1 until MAX_VLMUL) { 461 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 462 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 463 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 464 csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 465 csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 466 csBundle(i + 1).ctrl.uopIdx := i.U 467 } 468 csBundle(numOfUop - 1.U).ctrl.ldest := dest 469 } 470 is(UopDivType.VEC_SLIDE1UP) { 471 /* 472 FMV.D.X 473 */ 474 csBundle(0).ctrl.srcType(0) := SrcType.reg 475 csBundle(0).ctrl.srcType(1) := SrcType.imm 476 csBundle(0).ctrl.lsrc(1) := 0.U 477 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 478 csBundle(0).ctrl.fuType := FuType.i2f 479 csBundle(0).ctrl.rfWen := false.B 480 csBundle(0).ctrl.fpWen := true.B 481 csBundle(0).ctrl.vecWen := false.B 482 csBundle(0).ctrl.fpu.isAddSub := false.B 483 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 484 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 485 csBundle(0).ctrl.fpu.fromInt := true.B 486 csBundle(0).ctrl.fpu.wflags := false.B 487 csBundle(0).ctrl.fpu.fpWen := true.B 488 csBundle(0).ctrl.fpu.div := false.B 489 csBundle(0).ctrl.fpu.sqrt := false.B 490 csBundle(0).ctrl.fpu.fcvt := false.B 491 //LMUL 492 csBundle(1).ctrl.srcType(0) := SrcType.fp 493 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 494 csBundle(1).ctrl.lsrc(2) := dest 495 csBundle(1).ctrl.ldest := dest 496 csBundle(1).ctrl.uopIdx := 0.U 497 for (i <- 1 until MAX_VLMUL) { 498 csBundle(i + 1).ctrl.srcType(0) := SrcType.vp 499 csBundle(i + 1).ctrl.lsrc(0) := src2 + (i - 1).U 500 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 501 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 502 csBundle(i + 1).ctrl.ldest := dest + i.U 503 csBundle(i + 1).ctrl.uopIdx := i.U 504 } 505 } 506 is(UopDivType.VEC_FSLIDE1UP) { 507 //LMUL 508 csBundle(0).ctrl.srcType(0) := SrcType.fp 509 csBundle(0).ctrl.lsrc(0) := src1 510 csBundle(0).ctrl.lsrc(1) := src2 511 csBundle(0).ctrl.lsrc(2) := dest 512 csBundle(0).ctrl.ldest := dest 513 csBundle(0).ctrl.uopIdx := 0.U 514 for (i <- 1 until MAX_VLMUL) { 515 csBundle(i).ctrl.srcType(0) := SrcType.vp 516 csBundle(i).ctrl.lsrc(0) := src2 + (i - 1).U 517 csBundle(i).ctrl.lsrc(1) := src2 + i.U 518 csBundle(i).ctrl.lsrc(2) := dest + i.U 519 csBundle(i).ctrl.ldest := dest + i.U 520 csBundle(i).ctrl.uopIdx := i.U 521 } 522 } 523 is(UopDivType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 524 /* 525 FMV.D.X 526 */ 527 csBundle(0).ctrl.srcType(0) := SrcType.reg 528 csBundle(0).ctrl.srcType(1) := SrcType.imm 529 csBundle(0).ctrl.lsrc(1) := 0.U 530 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 531 csBundle(0).ctrl.fuType := FuType.i2f 532 csBundle(0).ctrl.rfWen := false.B 533 csBundle(0).ctrl.fpWen := true.B 534 csBundle(0).ctrl.vecWen := false.B 535 csBundle(0).ctrl.fpu.isAddSub := false.B 536 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 537 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 538 csBundle(0).ctrl.fpu.fromInt := true.B 539 csBundle(0).ctrl.fpu.wflags := false.B 540 csBundle(0).ctrl.fpu.fpWen := true.B 541 csBundle(0).ctrl.fpu.div := false.B 542 csBundle(0).ctrl.fpu.sqrt := false.B 543 csBundle(0).ctrl.fpu.fcvt := false.B 544 //LMUL 545 for (i <- 0 until MAX_VLMUL) { 546 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp 547 csBundle(2 * i + 1).ctrl.srcType(1) := SrcType.vp 548 csBundle(2 * i + 1).ctrl.lsrc(0) := src2 + (i+1).U 549 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 550 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 551 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 552 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 553 if (2 * i + 2 < MAX_VLMUL * 2 ){ 554 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 555 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 556 // csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U // DontCare 557 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 558 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 559 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 560 } 561 } 562 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 563 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := FP_TMP_REG_MV.U 564 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 565 } 566 is(UopDivType.VEC_FSLIDE1DOWN) { 567 //LMUL 568 for (i <- 0 until MAX_VLMUL) { 569 csBundle(2 * i).ctrl.srcType(0) := SrcType.vp 570 csBundle(2 * i).ctrl.srcType(1) := SrcType.vp 571 csBundle(2 * i).ctrl.lsrc(0) := src2 + (i+1).U 572 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 573 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 574 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 575 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 576 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 577 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 578 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 579 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 580 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 581 } 582 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 583 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1 584 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 585 } 586 is(UopDivType.VEC_VRED) { 587 when(simple.io.vconfig.vtype.vlmul === "b001".U){ 588 csBundle(0).ctrl.srcType(2) := SrcType.DC 589 csBundle(0).ctrl.lsrc(0) := src2 + 1.U 590 csBundle(0).ctrl.lsrc(1) := src2 591 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 592 csBundle(0).ctrl.uopIdx := 0.U 593 } 594 when(simple.io.vconfig.vtype.vlmul === "b010".U) { 595 csBundle(0).ctrl.srcType(2) := SrcType.DC 596 csBundle(0).ctrl.lsrc(0) := src2 + 1.U 597 csBundle(0).ctrl.lsrc(1) := src2 598 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 599 csBundle(0).ctrl.uopIdx := 0.U 600 601 csBundle(1).ctrl.srcType(2) := SrcType.DC 602 csBundle(1).ctrl.lsrc(0) := src2 + 3.U 603 csBundle(1).ctrl.lsrc(1) := src2 + 2.U 604 csBundle(1).ctrl.ldest := (VECTOR_TMP_REG_LMUL+1).U 605 csBundle(1).ctrl.uopIdx := 1.U 606 607 csBundle(2).ctrl.srcType(2) := SrcType.DC 608 csBundle(2).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL+1).U 609 csBundle(2).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U 610 csBundle(2).ctrl.ldest := (VECTOR_TMP_REG_LMUL+2).U 611 csBundle(2).ctrl.uopIdx := 2.U 612 } 613 when(simple.io.vconfig.vtype.vlmul === "b011".U) { 614 for(i <- 0 until MAX_VLMUL){ 615 if(i < MAX_VLMUL - MAX_VLMUL/2){ 616 csBundle(i).ctrl.lsrc(0) := src2 + (i * 2 + 1).U 617 csBundle(i).ctrl.lsrc(1) := src2 + (i * 2).U 618 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 619 } else if (i < MAX_VLMUL - MAX_VLMUL/4) { 620 csBundle(i).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2 + 1).U 621 csBundle(i).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2).U 622 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 623 }else if (i < MAX_VLMUL - MAX_VLMUL/8) { 624 csBundle(6).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 625 csBundle(6).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 626 csBundle(6).ctrl.ldest := (VECTOR_TMP_REG_LMUL + 6).U 627 } 628 csBundle(i).ctrl.srcType(2) := SrcType.DC 629 csBundle(i).ctrl.uopIdx := i.U 630 } 631 } 632 when (simple.io.vconfig.vtype.vlmul.orR()){ 633 csBundle(numOfUop - 1.U).ctrl.srcType(2) := SrcType.vp 634 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1 635 csBundle(numOfUop - 1.U).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 636 csBundle(numOfUop - 1.U).ctrl.lsrc(2) := dest 637 csBundle(numOfUop - 1.U).ctrl.ldest := dest 638 csBundle(numOfUop - 1.U).ctrl.uopIdx := numOfUop - 1.U 639 } 640 } 641 642 is(UopDivType.VEC_SLIDEUP) { 643 // FMV.D.X 644 csBundle(0).ctrl.srcType(0) := SrcType.reg 645 csBundle(0).ctrl.srcType(1) := SrcType.imm 646 csBundle(0).ctrl.lsrc(1) := 0.U 647 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 648 csBundle(0).ctrl.fuType := FuType.i2f 649 csBundle(0).ctrl.rfWen := false.B 650 csBundle(0).ctrl.fpWen := true.B 651 csBundle(0).ctrl.vecWen := false.B 652 csBundle(0).ctrl.fpu.isAddSub := false.B 653 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 654 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 655 csBundle(0).ctrl.fpu.fromInt := true.B 656 csBundle(0).ctrl.fpu.wflags := false.B 657 csBundle(0).ctrl.fpu.fpWen := true.B 658 csBundle(0).ctrl.fpu.div := false.B 659 csBundle(0).ctrl.fpu.sqrt := false.B 660 csBundle(0).ctrl.fpu.fcvt := false.B 661 // LMUL 662 for(i <- 0 until MAX_VLMUL) 663 for(j <- 0 to i){ 664 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 665 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 666 csBundle(i*(i+1)/2+j+1).ctrl.srcType(0) := SrcType.fp 667 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 668 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(1) := src2 + j.U 669 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(2) := old_vd 670 csBundle(i*(i+1)/2+j+1).ctrl.ldest := vd 671 csBundle(i*(i+1)/2+j+1).ctrl.uopIdx := (i*(i+1)/2+j).U 672 } 673 } 674 675 is(UopDivType.VEC_ISLIDEUP) { 676 // LMUL 677 for(i <- 0 until MAX_VLMUL) 678 for(j <- 0 to i){ 679 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 680 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 681 csBundle(i*(i+1)/2+j).ctrl.lsrc(1) := src2 + j.U 682 csBundle(i*(i+1)/2+j).ctrl.lsrc(2) := old_vd 683 csBundle(i*(i+1)/2+j).ctrl.ldest := vd 684 csBundle(i*(i+1)/2+j).ctrl.uopIdx := (i*(i+1)/2+j).U 685 } 686 } 687 688 is(UopDivType.VEC_SLIDEDOWN) { 689 // FMV.D.X 690 csBundle(0).ctrl.srcType(0) := SrcType.reg 691 csBundle(0).ctrl.srcType(1) := SrcType.imm 692 csBundle(0).ctrl.lsrc(1) := 0.U 693 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 694 csBundle(0).ctrl.fuType := FuType.i2f 695 csBundle(0).ctrl.rfWen := false.B 696 csBundle(0).ctrl.fpWen := true.B 697 csBundle(0).ctrl.vecWen := false.B 698 csBundle(0).ctrl.fpu.isAddSub := false.B 699 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 700 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 701 csBundle(0).ctrl.fpu.fromInt := true.B 702 csBundle(0).ctrl.fpu.wflags := false.B 703 csBundle(0).ctrl.fpu.fpWen := true.B 704 csBundle(0).ctrl.fpu.div := false.B 705 csBundle(0).ctrl.fpu.sqrt := false.B 706 csBundle(0).ctrl.fpu.fcvt := false.B 707 // LMUL 708 for(i <- 0 until MAX_VLMUL) 709 for(j <- (0 to i).reverse){ 710 when(i.U < lmul){ 711 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 712 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 713 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.srcType(0) := SrcType.fp 714 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(0) := FP_TMP_REG_MV.U 715 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(1) := src2 + lmul - 1.U - j.U 716 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(2) := old_vd 717 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.ldest := vd 718 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.uopIdx := numOfUop-(i*(i+1)/2+i-j+2).U 719 } 720 } 721 } 722 723 is(UopDivType.VEC_ISLIDEDOWN) { 724 // LMUL 725 for(i <- 0 until MAX_VLMUL) 726 for(j <- (0 to i).reverse){ 727 when(i.U < lmul){ 728 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 729 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 730 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(1) := src2 + lmul - 1.U - j.U 731 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(2) := old_vd 732 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.ldest := vd 733 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.uopIdx := numOfUop-(i*(i+1)/2+i-j+1).U 734 } 735 } 736 } 737 738 is(UopDivType.VEC_0MX) { 739 // LMUL 740 for (i <- 0 until MAX_VLMUL) { 741 val lsrc0 = if (i==0) 0.U else (VECTOR_TMP_REG_LMUL + i - 1).U 742 val ldest = (VECTOR_TMP_REG_LMUL + i).U 743 csBundle(i).ctrl.srcType(0) := SrcType.vp 744 csBundle(i).ctrl.srcType(1) := SrcType.vp 745 csBundle(i).ctrl.rfWen := false.B 746 csBundle(i).ctrl.vecWen := true.B 747 csBundle(i).ctrl.lsrc(0) := lsrc0 748 csBundle(i).ctrl.lsrc(1) := src2 749 // csBundle(i).ctrl.lsrc(2) := dest + i.U DontCare 750 csBundle(i).ctrl.ldest := ldest 751 csBundle(i).ctrl.uopIdx := i.U 752 } 753 csBundle(lmul-1.U).ctrl.vecWen := false.B 754 csBundle(lmul-1.U).ctrl.fpWen := true.B 755 csBundle(lmul-1.U).ctrl.ldest := FP_TMP_REG_MV.U 756 // FMV_X_D 757 csBundle(lmul).ctrl.srcType(0) := SrcType.fp 758 csBundle(lmul).ctrl.srcType(1) := SrcType.imm 759 csBundle(lmul).ctrl.lsrc(0) := FP_TMP_REG_MV.U 760 csBundle(lmul).ctrl.lsrc(1) := 0.U 761 csBundle(lmul).ctrl.ldest := dest 762 csBundle(lmul).ctrl.fuType := FuType.fmisc 763 csBundle(lmul).ctrl.rfWen := true.B 764 csBundle(lmul).ctrl.fpWen := false.B 765 csBundle(lmul).ctrl.vecWen := false.B 766 csBundle(lmul).ctrl.fpu.isAddSub := false.B 767 csBundle(lmul).ctrl.fpu.typeTagIn := FPU.D 768 csBundle(lmul).ctrl.fpu.typeTagOut := FPU.D 769 csBundle(lmul).ctrl.fpu.fromInt := false.B 770 csBundle(lmul).ctrl.fpu.wflags := false.B 771 csBundle(lmul).ctrl.fpu.fpWen := false.B 772 csBundle(lmul).ctrl.fpu.div := false.B 773 csBundle(lmul).ctrl.fpu.sqrt := false.B 774 csBundle(lmul).ctrl.fpu.fcvt := false.B 775 } 776 777 is(UopDivType.VEC_VMV) { 778 // LMUL 779 for (i <- 0 until MAX_VLMUL) { 780 val lsrc0 = if (i==0) 0.U else (VECTOR_TMP_REG_LMUL + i - 1).U 781 csBundle(i*2+0).ctrl.srcType(0) := SrcType.vp 782 csBundle(i*2+0).ctrl.srcType(1) := SrcType.vp 783 csBundle(i*2+0).ctrl.lsrc(0) := lsrc0 784 csBundle(i*2+0).ctrl.lsrc(1) := src2 785 csBundle(i).ctrl.lsrc(2) := dest + i.U 786 csBundle(i*2+0).ctrl.ldest := dest + i.U 787 csBundle(i*2+0).ctrl.uopIdx := (i*2+0).U 788 789 csBundle(i*2+1).ctrl.srcType(0) := SrcType.vp 790 csBundle(i*2+1).ctrl.srcType(1) := SrcType.vp 791 csBundle(i*2+1).ctrl.lsrc(0) := lsrc0 792 csBundle(i*2+1).ctrl.lsrc(1) := src2 793 // csBundle(i).ctrl.lsrc(2) := dest + i.U DontCare 794 csBundle(i*2+1).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 795 csBundle(i*2+1).ctrl.uopIdx := (i*2+1).U 796 } 797 } 798 } 799 800 //uops dispatch 801 val normal :: ext :: Nil = Enum(2) 802 val stateReg = RegInit(normal) 803 val uopRes = RegInit(0.U) 804 805 //readyFromRename Counter 806 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 807 808 switch(stateReg) { 809 is(normal) { 810 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 811 } 812 is(ext) { 813 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 814 } 815 } 816 817 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 818 val uopResJudge = Mux(stateReg === normal, 819 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 820 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 821 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 822 823 for(i <- 0 until RenameWidth) { 824 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 825 (stateReg === normal) -> csBundle(i), 826 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 827 )) 828 } 829 830 831 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 832 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 833 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 834 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 835 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 836 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 837 notInfVec(0) := true.B 838 839 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 840 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 841 1.U) 842 validToRename.zipWithIndex.foreach{ 843 case(dst, i) => 844 dst := MuxCase(false.B, Seq( 845 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 846 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 847 )) 848 } 849 850 readyToIBuf.zipWithIndex.foreach { 851 case (dst, i) => 852 dst := MuxCase(true.B, Seq( 853 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 854 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 855 )) 856 } 857 858 io.deq.cf_ctrl := cf_ctrl 859 io.deq.isVset := isVset_u 860 io.deq.complexNum := complexNum 861 io.deq.validToRename := validToRename 862 io.deq.readyToIBuf := readyToIBuf 863 864} 865 866