1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.VType 34import yunsuan.VpermType 35 36import scala.collection.Seq 37 38trait VectorConstants { 39 val MAX_VLMUL = 8 40 val FP_TMP_REG_MV = 32 41 val VECTOR_TMP_REG_LMUL = 33 // 33~47 -> 15 42} 43 44class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 45 val enq = new Bundle { val staticInst = Input(new StaticInst) } 46 val vtype = Input(new VType) 47 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 48 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 49 val readyFromRename = Input(Vec(RenameWidth, Bool())) 50 val deq = new Bundle { 51 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 52 val isVset = Output(Bool()) 53 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 54 val validToRename = Output(Vec(RenameWidth, Bool())) 55 val complexNum = Output(UInt(3.W)) 56 } 57 val csrCtrl = Input(new CustomCSRCtrlIO) 58} 59 60/** 61 * @author zly 62 */ 63class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 64 val io = IO(new DecodeUnitCompIO) 65 66 val maxUopSize = MaxUopSize 67 //input bits 68 val staticInst = Wire(new StaticInst) 69 70 71 staticInst := io.enq.staticInst 72 private val inst: XSInstBitFields = staticInst.instr.asTypeOf(new XSInstBitFields) 73 74 val src1 = Cat(0.U(1.W), inst.RS1) 75 val src2 = Cat(0.U(1.W), inst.RS2) 76 val dest = Cat(0.U(1.W), inst.RD) 77 78 79 //output bits 80 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 81 val validToRename = Wire(Vec(RenameWidth, Bool())) 82 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 83 val complexNum = Wire(UInt(3.W)) 84 85 //output of DecodeUnit 86 val decodedInstsSimple = Wire(new DecodedInst) 87 val numOfUop = Wire(UInt(log2Up(maxUopSize+1).W)) 88 val lmul = Wire(UInt(4.W)) 89 val isVsetSimple = Wire(Bool()) 90 91 //pre decode 92 val simple = Module(new DecodeUnit) 93 simple.io.enq.ctrlFlow := staticInst 94 simple.io.enq.vtype := io.vtype 95 simple.io.csrCtrl := io.csrCtrl 96 decodedInstsSimple := simple.io.deq.decodedInst 97 lmul := simple.io.deq.uopInfo.lmul 98 isVsetSimple := simple.io.deq.decodedInst.isVset 99 when(isVsetSimple) { 100 when(dest === 0.U && src1 === 0.U) { 101 decodedInstsSimple.fuOpType := VSETOpType.keepVl(simple.io.deq.decodedInst.fuOpType) 102 }.elsewhen(src1 === 0.U) { 103 decodedInstsSimple.fuOpType := VSETOpType.setVlmax(simple.io.deq.decodedInst.fuOpType) 104 } 105 when(io.vtype.illegal){ 106 decodedInstsSimple.flushPipe := true.B 107 } 108 } 109 //Type of uop Div 110 val typeOfSplit = decodedInstsSimple.uopSplitType 111 112 when(typeOfSplit === UopSplitType.DIR) { 113 numOfUop := Mux(dest =/= 0.U, 2.U, 114 Mux(src1 =/= 0.U, 1.U, 115 Mux(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType), 2.U, 1.U))) 116 } .otherwise { 117 numOfUop := simple.io.deq.uopInfo.numOfUop 118 } 119 120 121 //uop div up to maxUopSize 122 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 123 csBundle.map { case dst => 124 dst := decodedInstsSimple 125 dst.firstUop := false.B 126 dst.lastUop := false.B 127 } 128 129 csBundle(0).numUops := numOfUop 130 csBundle(0).firstUop := true.B 131 csBundle(numOfUop - 1.U).lastUop := true.B 132 133 switch(typeOfSplit) { 134 is(UopSplitType.DIR) { 135 when(isVsetSimple) { 136 when(dest =/= 0.U) { 137 csBundle(0).fuType := FuType.vsetiwi.U 138 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInstsSimple.fuOpType) 139 csBundle(0).flushPipe := false.B 140 csBundle(0).rfWen := true.B 141 csBundle(0).vecWen := false.B 142 csBundle(1).ldest := VCONFIG_IDX.U 143 csBundle(1).rfWen := false.B 144 csBundle(1).vecWen := true.B 145 }.elsewhen(src1 =/= 0.U) { 146 csBundle(0).ldest := VCONFIG_IDX.U 147 }.elsewhen(VSETOpType.isVsetvli(decodedInstsSimple.fuOpType)) { 148 csBundle(0).fuType := FuType.vsetfwf.U 149 csBundle(0).srcType(0) := SrcType.vp 150 csBundle(0).lsrc(0) := VCONFIG_IDX.U 151 }.elsewhen(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType)) { 152 csBundle(0).srcType(0) := SrcType.reg 153 csBundle(0).srcType(1) := SrcType.imm 154 csBundle(0).lsrc(1) := 0.U 155 csBundle(0).ldest := FP_TMP_REG_MV.U 156 csBundle(0).fuType := FuType.i2f.U 157 csBundle(0).rfWen := false.B 158 csBundle(0).fpWen := true.B 159 csBundle(0).vecWen := false.B 160 csBundle(0).fpu.isAddSub := false.B 161 csBundle(0).fpu.typeTagIn := FPU.D 162 csBundle(0).fpu.typeTagOut := FPU.D 163 csBundle(0).fpu.fromInt := true.B 164 csBundle(0).fpu.wflags := false.B 165 csBundle(0).fpu.fpWen := true.B 166 csBundle(0).fpu.div := false.B 167 csBundle(0).fpu.sqrt := false.B 168 csBundle(0).fpu.fcvt := false.B 169 csBundle(0).flushPipe := false.B 170 csBundle(1).fuType := FuType.vsetfwf.U 171 csBundle(1).srcType(0) := SrcType.vp 172 csBundle(1).lsrc(0) := VCONFIG_IDX.U 173 csBundle(1).srcType(1) := SrcType.fp 174 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 175 csBundle(1).ldest := VCONFIG_IDX.U 176 } 177 } 178 } 179 is(UopSplitType.VEC_VVV) { 180 for (i <- 0 until MAX_VLMUL) { 181 csBundle(i).lsrc(0) := src1 + i.U 182 csBundle(i).lsrc(1) := src2 + i.U 183 csBundle(i).lsrc(2) := dest + i.U 184 csBundle(i).ldest := dest + i.U 185 csBundle(i).uopIdx := i.U 186 } 187 } 188 is(UopSplitType.VEC_VFV) { 189 for (i <- 0 until MAX_VLMUL) { 190 csBundle(i).lsrc(1) := src2 + i.U 191 csBundle(i).lsrc(2) := dest + i.U 192 csBundle(i).ldest := dest + i.U 193 csBundle(i).uopIdx := i.U 194 } 195 } 196 is(UopSplitType.VEC_EXT2) { 197 for (i <- 0 until MAX_VLMUL / 2) { 198 csBundle(2 * i).lsrc(1) := src2 + i.U 199 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 200 csBundle(2 * i).ldest := dest + (2 * i).U 201 csBundle(2 * i).uopIdx := (2 * i).U 202 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 203 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 204 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 205 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 206 } 207 } 208 is(UopSplitType.VEC_EXT4) { 209 for (i <- 0 until MAX_VLMUL / 4) { 210 csBundle(4 * i).lsrc(1) := src2 + i.U 211 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 212 csBundle(4 * i).ldest := dest + (4 * i).U 213 csBundle(4 * i).uopIdx := (4 * i).U 214 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 215 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 216 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 217 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 218 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 219 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 220 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 221 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 222 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 223 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 224 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 225 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 226 } 227 } 228 is(UopSplitType.VEC_EXT8) { 229 for (i <- 0 until MAX_VLMUL) { 230 csBundle(i).lsrc(1) := src2 231 csBundle(i).lsrc(2) := dest + i.U 232 csBundle(i).ldest := dest + i.U 233 csBundle(i).uopIdx := i.U 234 } 235 } 236 is(UopSplitType.VEC_0XV) { 237 /* 238 FMV.D.X 239 */ 240 csBundle(0).srcType(0) := SrcType.reg 241 csBundle(0).srcType(1) := SrcType.imm 242 csBundle(0).lsrc(1) := 0.U 243 csBundle(0).ldest := FP_TMP_REG_MV.U 244 csBundle(0).fuType := FuType.i2f.U 245 csBundle(0).rfWen := false.B 246 csBundle(0).fpWen := true.B 247 csBundle(0).vecWen := false.B 248 csBundle(0).fpu.isAddSub := false.B 249 csBundle(0).fpu.typeTagIn := FPU.D 250 csBundle(0).fpu.typeTagOut := FPU.D 251 csBundle(0).fpu.fromInt := true.B 252 csBundle(0).fpu.wflags := false.B 253 csBundle(0).fpu.fpWen := true.B 254 csBundle(0).fpu.div := false.B 255 csBundle(0).fpu.sqrt := false.B 256 csBundle(0).fpu.fcvt := false.B 257 /* 258 vfmv.s.f 259 */ 260 csBundle(1).srcType(0) := SrcType.fp 261 csBundle(1).srcType(1) := SrcType.vp 262 csBundle(1).srcType(2) := SrcType.vp 263 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 264 csBundle(1).lsrc(1) := 0.U 265 csBundle(1).lsrc(2) := dest 266 csBundle(1).ldest := dest 267 csBundle(1).fuType := FuType.vppu.U 268 csBundle(1).fuOpType := VpermType.dummy 269 csBundle(1).rfWen := false.B 270 csBundle(1).fpWen := false.B 271 csBundle(1).vecWen := true.B 272 } 273 is(UopSplitType.VEC_VXV) { 274 /* 275 FMV.D.X 276 */ 277 csBundle(0).srcType(0) := SrcType.reg 278 csBundle(0).srcType(1) := SrcType.imm 279 csBundle(0).lsrc(1) := 0.U 280 csBundle(0).ldest := FP_TMP_REG_MV.U 281 csBundle(0).fuType := FuType.i2f.U 282 csBundle(0).rfWen := false.B 283 csBundle(0).fpWen := true.B 284 csBundle(0).vecWen := false.B 285 csBundle(0).fpu.isAddSub := false.B 286 csBundle(0).fpu.typeTagIn := FPU.D 287 csBundle(0).fpu.typeTagOut := FPU.D 288 csBundle(0).fpu.fromInt := true.B 289 csBundle(0).fpu.wflags := false.B 290 csBundle(0).fpu.fpWen := true.B 291 csBundle(0).fpu.div := false.B 292 csBundle(0).fpu.sqrt := false.B 293 csBundle(0).fpu.fcvt := false.B 294 /* 295 LMUL 296 */ 297 for (i <- 0 until MAX_VLMUL) { 298 csBundle(i + 1).srcType(0) := SrcType.fp 299 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 300 csBundle(i + 1).lsrc(1) := src2 + i.U 301 csBundle(i + 1).lsrc(2) := dest + i.U 302 csBundle(i + 1).ldest := dest + i.U 303 csBundle(i + 1).uopIdx := i.U 304 } 305 } 306 is(UopSplitType.VEC_VVW) { 307 for (i <- 0 until MAX_VLMUL / 2) { 308 csBundle(2 * i).lsrc(0) := src1 + i.U 309 csBundle(2 * i).lsrc(1) := src2 + i.U 310 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 311 csBundle(2 * i).ldest := dest + (2 * i).U 312 csBundle(2 * i).uopIdx := (2 * i).U 313 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 314 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 315 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 316 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 317 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 318 } 319 } 320 is(UopSplitType.VEC_WVW) { 321 for (i <- 0 until MAX_VLMUL / 2) { 322 csBundle(2 * i).lsrc(0) := src1 + i.U 323 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 324 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 325 csBundle(2 * i).ldest := dest + (2 * i).U 326 csBundle(2 * i).uopIdx := (2 * i).U 327 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 328 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 329 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 330 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 331 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 332 } 333 } 334 is(UopSplitType.VEC_VXW) { 335 /* 336 FMV.D.X 337 */ 338 csBundle(0).srcType(0) := SrcType.reg 339 csBundle(0).srcType(1) := SrcType.imm 340 csBundle(0).lsrc(1) := 0.U 341 csBundle(0).ldest := FP_TMP_REG_MV.U 342 csBundle(0).fuType := FuType.i2f.U 343 csBundle(0).rfWen := false.B 344 csBundle(0).fpWen := true.B 345 csBundle(0).vecWen := false.B 346 csBundle(0).fpu.isAddSub := false.B 347 csBundle(0).fpu.typeTagIn := FPU.D 348 csBundle(0).fpu.typeTagOut := FPU.D 349 csBundle(0).fpu.fromInt := true.B 350 csBundle(0).fpu.wflags := false.B 351 csBundle(0).fpu.fpWen := true.B 352 csBundle(0).fpu.div := false.B 353 csBundle(0).fpu.sqrt := false.B 354 csBundle(0).fpu.fcvt := false.B 355 356 for (i <- 0 until MAX_VLMUL / 2) { 357 csBundle(2 * i + 1).srcType(0) := SrcType.fp 358 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 359 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 360 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 361 csBundle(2 * i + 1).ldest := dest + (2 * i).U 362 csBundle(2 * i + 1).uopIdx := (2 * i).U 363 csBundle(2 * i + 2).srcType(0) := SrcType.fp 364 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 365 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 366 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 367 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 368 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 369 } 370 } 371 is(UopSplitType.VEC_WXW) { 372 /* 373 FMV.D.X 374 */ 375 csBundle(0).srcType(0) := SrcType.reg 376 csBundle(0).srcType(1) := SrcType.imm 377 csBundle(0).lsrc(1) := 0.U 378 csBundle(0).ldest := FP_TMP_REG_MV.U 379 csBundle(0).fuType := FuType.i2f.U 380 csBundle(0).rfWen := false.B 381 csBundle(0).fpWen := true.B 382 csBundle(0).vecWen := false.B 383 csBundle(0).fpu.isAddSub := false.B 384 csBundle(0).fpu.typeTagIn := FPU.D 385 csBundle(0).fpu.typeTagOut := FPU.D 386 csBundle(0).fpu.fromInt := true.B 387 csBundle(0).fpu.wflags := false.B 388 csBundle(0).fpu.fpWen := true.B 389 csBundle(0).fpu.div := false.B 390 csBundle(0).fpu.sqrt := false.B 391 csBundle(0).fpu.fcvt := false.B 392 393 for (i <- 0 until MAX_VLMUL / 2) { 394 csBundle(2 * i + 1).srcType(0) := SrcType.fp 395 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 396 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 397 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 398 csBundle(2 * i + 1).ldest := dest + (2 * i).U 399 csBundle(2 * i + 1).uopIdx := (2 * i).U 400 csBundle(2 * i + 2).srcType(0) := SrcType.fp 401 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 402 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 403 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 404 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 405 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 406 } 407 } 408 is(UopSplitType.VEC_WVV) { 409 for (i <- 0 until MAX_VLMUL / 2) { 410 411 csBundle(2 * i).lsrc(0) := src1 + i.U 412 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 413 csBundle(2 * i).lsrc(2) := dest + i.U 414 csBundle(2 * i).ldest := dest + i.U 415 csBundle(2 * i).uopIdx := (2 * i).U 416 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 417 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 418 csBundle(2 * i + 1).lsrc(2) := dest + i.U 419 csBundle(2 * i + 1).ldest := dest + i.U 420 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 421 } 422 } 423 is(UopSplitType.VEC_WXV) { 424 /* 425 FMV.D.X 426 */ 427 csBundle(0).srcType(0) := SrcType.reg 428 csBundle(0).srcType(1) := SrcType.imm 429 csBundle(0).lsrc(1) := 0.U 430 csBundle(0).ldest := FP_TMP_REG_MV.U 431 csBundle(0).fuType := FuType.i2f.U 432 csBundle(0).rfWen := false.B 433 csBundle(0).fpWen := true.B 434 csBundle(0).vecWen := false.B 435 csBundle(0).fpu.isAddSub := false.B 436 csBundle(0).fpu.typeTagIn := FPU.D 437 csBundle(0).fpu.typeTagOut := FPU.D 438 csBundle(0).fpu.fromInt := true.B 439 csBundle(0).fpu.wflags := false.B 440 csBundle(0).fpu.fpWen := true.B 441 csBundle(0).fpu.div := false.B 442 csBundle(0).fpu.sqrt := false.B 443 csBundle(0).fpu.fcvt := false.B 444 445 for (i <- 0 until MAX_VLMUL / 2) { 446 csBundle(2 * i + 1).srcType(0) := SrcType.fp 447 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 448 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 449 csBundle(2 * i + 1).lsrc(2) := dest + i.U 450 csBundle(2 * i + 1).ldest := dest + i.U 451 csBundle(2 * i + 1).uopIdx := (2 * i).U 452 csBundle(2 * i + 2).srcType(0) := SrcType.fp 453 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 454 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 455 csBundle(2 * i + 2).lsrc(2) := dest + i.U 456 csBundle(2 * i + 2).ldest := dest + i.U 457 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 458 } 459 } 460 is(UopSplitType.VEC_VVM) { 461 csBundle(0).lsrc(2) := dest 462 csBundle(0).ldest := dest 463 csBundle(0).uopIdx := 0.U 464 for (i <- 1 until MAX_VLMUL) { 465 csBundle(i).lsrc(0) := src1 + i.U 466 csBundle(i).lsrc(1) := src2 + i.U 467 csBundle(i).lsrc(2) := dest 468 csBundle(i).ldest := dest 469 csBundle(i).uopIdx := i.U 470 } 471 csBundle(numOfUop - 1.U).ldest := dest 472 } 473 is(UopSplitType.VEC_VXM) { 474 /* 475 FMV.D.X 476 */ 477 csBundle(0).srcType(0) := SrcType.reg 478 csBundle(0).srcType(1) := SrcType.imm 479 csBundle(0).lsrc(1) := 0.U 480 csBundle(0).ldest := FP_TMP_REG_MV.U 481 csBundle(0).fuType := FuType.i2f.U 482 csBundle(0).rfWen := false.B 483 csBundle(0).fpWen := true.B 484 csBundle(0).vecWen := false.B 485 csBundle(0).fpu.isAddSub := false.B 486 csBundle(0).fpu.typeTagIn := FPU.D 487 csBundle(0).fpu.typeTagOut := FPU.D 488 csBundle(0).fpu.fromInt := true.B 489 csBundle(0).fpu.wflags := false.B 490 csBundle(0).fpu.fpWen := true.B 491 csBundle(0).fpu.div := false.B 492 csBundle(0).fpu.sqrt := false.B 493 csBundle(0).fpu.fcvt := false.B 494 //LMUL 495 csBundle(1).srcType(0) := SrcType.fp 496 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 497 csBundle(1).lsrc(2) := dest 498 csBundle(1).ldest := dest 499 csBundle(1).uopIdx := 0.U 500 for (i <- 1 until MAX_VLMUL) { 501 csBundle(i + 1).srcType(0) := SrcType.fp 502 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 503 csBundle(i + 1).lsrc(1) := src2 + i.U 504 csBundle(i + 1).lsrc(2) := dest 505 csBundle(i + 1).ldest := dest 506 csBundle(i + 1).uopIdx := i.U 507 } 508 csBundle(numOfUop - 1.U).ldest := dest 509 } 510 is(UopSplitType.VEC_SLIDE1UP) { 511 /* 512 FMV.D.X 513 */ 514 csBundle(0).srcType(0) := SrcType.reg 515 csBundle(0).srcType(1) := SrcType.imm 516 csBundle(0).lsrc(1) := 0.U 517 csBundle(0).ldest := FP_TMP_REG_MV.U 518 csBundle(0).fuType := FuType.i2f.U 519 csBundle(0).rfWen := false.B 520 csBundle(0).fpWen := true.B 521 csBundle(0).vecWen := false.B 522 csBundle(0).fpu.isAddSub := false.B 523 csBundle(0).fpu.typeTagIn := FPU.D 524 csBundle(0).fpu.typeTagOut := FPU.D 525 csBundle(0).fpu.fromInt := true.B 526 csBundle(0).fpu.wflags := false.B 527 csBundle(0).fpu.fpWen := true.B 528 csBundle(0).fpu.div := false.B 529 csBundle(0).fpu.sqrt := false.B 530 csBundle(0).fpu.fcvt := false.B 531 //LMUL 532 csBundle(1).srcType(0) := SrcType.fp 533 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 534 csBundle(1).lsrc(2) := dest 535 csBundle(1).ldest := dest 536 csBundle(1).uopIdx := 0.U 537 for (i <- 1 until MAX_VLMUL) { 538 csBundle(i + 1).srcType(0) := SrcType.vp 539 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 540 csBundle(i + 1).lsrc(1) := src2 + i.U 541 csBundle(i + 1).lsrc(2) := dest + i.U 542 csBundle(i + 1).ldest := dest + i.U 543 csBundle(i + 1).uopIdx := i.U 544 } 545 } 546 is(UopSplitType.VEC_FSLIDE1UP) { 547 //LMUL 548 csBundle(0).srcType(0) := SrcType.fp 549 csBundle(0).lsrc(0) := src1 550 csBundle(0).lsrc(1) := src2 551 csBundle(0).lsrc(2) := dest 552 csBundle(0).ldest := dest 553 csBundle(0).uopIdx := 0.U 554 for (i <- 1 until MAX_VLMUL) { 555 csBundle(i).srcType(0) := SrcType.vp 556 csBundle(i).lsrc(0) := src2 + (i - 1).U 557 csBundle(i).lsrc(1) := src2 + i.U 558 csBundle(i).lsrc(2) := dest + i.U 559 csBundle(i).ldest := dest + i.U 560 csBundle(i).uopIdx := i.U 561 } 562 } 563 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 564 /* 565 FMV.D.X 566 */ 567 csBundle(0).srcType(0) := SrcType.reg 568 csBundle(0).srcType(1) := SrcType.imm 569 csBundle(0).lsrc(1) := 0.U 570 csBundle(0).ldest := FP_TMP_REG_MV.U 571 csBundle(0).fuType := FuType.i2f.U 572 csBundle(0).rfWen := false.B 573 csBundle(0).fpWen := true.B 574 csBundle(0).vecWen := false.B 575 csBundle(0).fpu.isAddSub := false.B 576 csBundle(0).fpu.typeTagIn := FPU.D 577 csBundle(0).fpu.typeTagOut := FPU.D 578 csBundle(0).fpu.fromInt := true.B 579 csBundle(0).fpu.wflags := false.B 580 csBundle(0).fpu.fpWen := true.B 581 csBundle(0).fpu.div := false.B 582 csBundle(0).fpu.sqrt := false.B 583 csBundle(0).fpu.fcvt := false.B 584 //LMUL 585 for (i <- 0 until MAX_VLMUL) { 586 csBundle(2 * i + 1).srcType(0) := SrcType.vp 587 csBundle(2 * i + 1).srcType(1) := SrcType.vp 588 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 589 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 590 csBundle(2 * i + 1).lsrc(2) := dest + i.U 591 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 592 csBundle(2 * i + 1).uopIdx := (2 * i).U 593 if (2 * i + 2 < MAX_VLMUL * 2) { 594 csBundle(2 * i + 2).srcType(0) := SrcType.fp 595 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 596 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 597 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 598 csBundle(2 * i + 2).ldest := dest + i.U 599 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 600 } 601 } 602 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 603 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 604 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 605 } 606 is(UopSplitType.VEC_FSLIDE1DOWN) { 607 //LMUL 608 for (i <- 0 until MAX_VLMUL) { 609 csBundle(2 * i).srcType(0) := SrcType.vp 610 csBundle(2 * i).srcType(1) := SrcType.vp 611 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 612 csBundle(2 * i).lsrc(1) := src2 + i.U 613 csBundle(2 * i).lsrc(2) := dest + i.U 614 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 615 csBundle(2 * i).uopIdx := (2 * i).U 616 csBundle(2 * i + 1).srcType(0) := SrcType.fp 617 csBundle(2 * i + 1).lsrc(0) := src1 618 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 619 csBundle(2 * i + 1).ldest := dest + i.U 620 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 621 } 622 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 623 csBundle(numOfUop - 1.U).lsrc(0) := src1 624 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 625 } 626 is(UopSplitType.VEC_VRED) { 627 when(simple.io.enq.vtype.vlmul === "b001".U) { 628 csBundle(0).srcType(2) := SrcType.DC 629 csBundle(0).lsrc(0) := src2 + 1.U 630 csBundle(0).lsrc(1) := src2 631 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 632 csBundle(0).uopIdx := 0.U 633 } 634 when(simple.io.enq.vtype.vlmul === "b010".U) { 635 csBundle(0).srcType(2) := SrcType.DC 636 csBundle(0).lsrc(0) := src2 + 1.U 637 csBundle(0).lsrc(1) := src2 638 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 639 csBundle(0).uopIdx := 0.U 640 641 csBundle(1).srcType(2) := SrcType.DC 642 csBundle(1).lsrc(0) := src2 + 3.U 643 csBundle(1).lsrc(1) := src2 + 2.U 644 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 645 csBundle(1).uopIdx := 1.U 646 647 csBundle(2).srcType(2) := SrcType.DC 648 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 649 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 650 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 651 csBundle(2).uopIdx := 2.U 652 } 653 when(simple.io.enq.vtype.vlmul === "b011".U) { 654 for (i <- 0 until MAX_VLMUL) { 655 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 656 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 657 csBundle(i).lsrc(1) := src2 + (i * 2).U 658 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 659 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 660 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 661 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 662 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 663 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 664 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 665 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 666 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 667 } 668 csBundle(i).srcType(2) := SrcType.DC 669 csBundle(i).uopIdx := i.U 670 } 671 } 672 when(simple.io.enq.vtype.vlmul.orR()) { 673 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 674 csBundle(numOfUop - 1.U).lsrc(0) := src1 675 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 676 csBundle(numOfUop - 1.U).lsrc(2) := dest 677 csBundle(numOfUop - 1.U).ldest := dest 678 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 679 } 680 } 681 682 is(UopSplitType.VEC_SLIDEUP) { 683 // FMV.D.X 684 csBundle(0).srcType(0) := SrcType.reg 685 csBundle(0).srcType(1) := SrcType.imm 686 csBundle(0).lsrc(1) := 0.U 687 csBundle(0).ldest := FP_TMP_REG_MV.U 688 csBundle(0).fuType := FuType.i2f.U 689 csBundle(0).rfWen := false.B 690 csBundle(0).fpWen := true.B 691 csBundle(0).vecWen := false.B 692 csBundle(0).fpu.isAddSub := false.B 693 csBundle(0).fpu.typeTagIn := FPU.D 694 csBundle(0).fpu.typeTagOut := FPU.D 695 csBundle(0).fpu.fromInt := true.B 696 csBundle(0).fpu.wflags := false.B 697 csBundle(0).fpu.fpWen := true.B 698 csBundle(0).fpu.div := false.B 699 csBundle(0).fpu.sqrt := false.B 700 csBundle(0).fpu.fcvt := false.B 701 // LMUL 702 for (i <- 0 until MAX_VLMUL) 703 for (j <- 0 to i) { 704 val old_vd = if (j == 0) { 705 dest + i.U 706 } else (VECTOR_TMP_REG_LMUL + j - 1).U 707 val vd = if (j == i) { 708 dest + i.U 709 } else (VECTOR_TMP_REG_LMUL + j).U 710 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.fp 711 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := FP_TMP_REG_MV.U 712 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 713 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 714 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 715 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 716 } 717 } 718 719 is(UopSplitType.VEC_ISLIDEUP) { 720 // LMUL 721 for (i <- 0 until MAX_VLMUL) 722 for (j <- 0 to i) { 723 val old_vd = if (j == 0) { 724 dest + i.U 725 } else (VECTOR_TMP_REG_LMUL + j - 1).U 726 val vd = if (j == i) { 727 dest + i.U 728 } else (VECTOR_TMP_REG_LMUL + j).U 729 csBundle(i * (i + 1) / 2 + j).lsrc(1) := src2 + j.U 730 csBundle(i * (i + 1) / 2 + j).lsrc(2) := old_vd 731 csBundle(i * (i + 1) / 2 + j).ldest := vd 732 csBundle(i * (i + 1) / 2 + j).uopIdx := (i * (i + 1) / 2 + j).U 733 } 734 } 735 736 is(UopSplitType.VEC_SLIDEDOWN) { 737 // FMV.D.X 738 csBundle(0).srcType(0) := SrcType.reg 739 csBundle(0).srcType(1) := SrcType.imm 740 csBundle(0).lsrc(1) := 0.U 741 csBundle(0).ldest := FP_TMP_REG_MV.U 742 csBundle(0).fuType := FuType.i2f.U 743 csBundle(0).rfWen := false.B 744 csBundle(0).fpWen := true.B 745 csBundle(0).vecWen := false.B 746 csBundle(0).fpu.isAddSub := false.B 747 csBundle(0).fpu.typeTagIn := FPU.D 748 csBundle(0).fpu.typeTagOut := FPU.D 749 csBundle(0).fpu.fromInt := true.B 750 csBundle(0).fpu.wflags := false.B 751 csBundle(0).fpu.fpWen := true.B 752 csBundle(0).fpu.div := false.B 753 csBundle(0).fpu.sqrt := false.B 754 csBundle(0).fpu.fcvt := false.B 755 // LMUL 756 for (i <- 0 until MAX_VLMUL) 757 for (j <- (0 to i).reverse) { 758 when(i.U < lmul) { 759 val old_vd = if (j == 0) { 760 dest + lmul - 1.U - i.U 761 } else (VECTOR_TMP_REG_LMUL + j - 1).U 762 val vd = if (j == i) { 763 dest + lmul - 1.U - i.U 764 } else (VECTOR_TMP_REG_LMUL + j).U 765 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.fp 766 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := FP_TMP_REG_MV.U 767 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 768 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 769 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 770 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 771 } 772 } 773 } 774 775 is(UopSplitType.VEC_ISLIDEDOWN) { 776 // LMUL 777 for (i <- 0 until MAX_VLMUL) 778 for (j <- (0 to i).reverse) { 779 when(i.U < lmul) { 780 val old_vd = if (j == 0) { 781 dest + lmul - 1.U - i.U 782 } else (VECTOR_TMP_REG_LMUL + j - 1).U 783 val vd = if (j == i) { 784 dest + lmul - 1.U - i.U 785 } else (VECTOR_TMP_REG_LMUL + j).U 786 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 787 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 788 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 789 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 1).U 790 } 791 } 792 } 793 794 is(UopSplitType.VEC_M0X) { 795 // LMUL 796 for (i <- 0 until MAX_VLMUL) { 797 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 798 val ldest = (VECTOR_TMP_REG_LMUL + i).U 799 csBundle(i).srcType(0) := srcType0 800 csBundle(i).srcType(1) := SrcType.vp 801 csBundle(i).rfWen := false.B 802 csBundle(i).vecWen := true.B 803 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 804 csBundle(i).lsrc(1) := src2 805 // csBundle(i).lsrc(2) := dest + i.U DontCare 806 csBundle(i).ldest := ldest 807 csBundle(i).uopIdx := i.U 808 } 809 csBundle(lmul - 1.U).vecWen := false.B 810 csBundle(lmul - 1.U).fpWen := true.B 811 csBundle(lmul - 1.U).ldest := FP_TMP_REG_MV.U 812 // FMV_X_D 813 csBundle(lmul).srcType(0) := SrcType.fp 814 csBundle(lmul).srcType(1) := SrcType.imm 815 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 816 csBundle(lmul).lsrc(1) := 0.U 817 csBundle(lmul).ldest := dest 818 csBundle(lmul).fuType := FuType.fmisc.U 819 csBundle(lmul).rfWen := true.B 820 csBundle(lmul).fpWen := false.B 821 csBundle(lmul).vecWen := false.B 822 csBundle(lmul).fpu.isAddSub := false.B 823 csBundle(lmul).fpu.typeTagIn := FPU.D 824 csBundle(lmul).fpu.typeTagOut := FPU.D 825 csBundle(lmul).fpu.fromInt := false.B 826 csBundle(lmul).fpu.wflags := false.B 827 csBundle(lmul).fpu.fpWen := false.B 828 csBundle(lmul).fpu.div := false.B 829 csBundle(lmul).fpu.sqrt := false.B 830 csBundle(lmul).fpu.fcvt := false.B 831 } 832 833 is(UopSplitType.VEC_MVV) { 834 // LMUL 835 for (i <- 0 until MAX_VLMUL) { 836 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 837 csBundle(i * 2 + 0).srcType(0) := srcType0 838 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 839 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 840 csBundle(i * 2 + 0).lsrc(1) := src2 841 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 842 csBundle(i * 2 + 0).ldest := dest + i.U 843 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 844 845 csBundle(i * 2 + 1).srcType(0) := srcType0 846 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 847 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 848 csBundle(i * 2 + 1).lsrc(1) := src2 849 // csBundle(i).lsrc(2) := dest + i.U DontCare 850 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 851 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 852 } 853 } 854 855 is(UopSplitType.VEC_M0X_VFIRST) { 856 // LMUL 857 csBundle(0).rfWen := false.B 858 csBundle(0).fpWen := true.B 859 csBundle(0).ldest := FP_TMP_REG_MV.U 860 // FMV_X_D 861 csBundle(1).srcType(0) := SrcType.fp 862 csBundle(1).srcType(1) := SrcType.imm 863 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 864 csBundle(1).lsrc(1) := 0.U 865 csBundle(1).ldest := dest 866 csBundle(1).fuType := FuType.fmisc.U 867 csBundle(1).rfWen := true.B 868 csBundle(1).fpWen := false.B 869 csBundle(1).vecWen := false.B 870 csBundle(1).fpu.isAddSub := false.B 871 csBundle(1).fpu.typeTagIn := FPU.D 872 csBundle(1).fpu.typeTagOut := FPU.D 873 csBundle(1).fpu.fromInt := false.B 874 csBundle(1).fpu.wflags := false.B 875 csBundle(1).fpu.fpWen := false.B 876 csBundle(1).fpu.div := false.B 877 csBundle(1).fpu.sqrt := false.B 878 csBundle(1).fpu.fcvt := false.B 879 } 880 is(UopSplitType.VEC_VWW) { 881 for (i <- 0 until MAX_VLMUL*2) { 882 when(i.U < lmul){ 883 csBundle(i).srcType(2) := SrcType.DC 884 csBundle(i).lsrc(0) := src2 + i.U 885 csBundle(i).lsrc(1) := src2 + i.U 886 // csBundle(i).lsrc(2) := dest + (2 * i).U 887 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 888 csBundle(i).uopIdx := i.U 889 } otherwise { 890 csBundle(i).srcType(2) := SrcType.DC 891 csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 892 csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 893 // csBundle(i).lsrc(2) := dest + (2 * i).U 894 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 895 csBundle(i).uopIdx := i.U 896 } 897 csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 898 csBundle(numOfUop-1.U).lsrc(0) := src1 899 csBundle(numOfUop-1.U).lsrc(2) := dest 900 csBundle(numOfUop-1.U).ldest := dest 901 } 902 } 903 is(UopSplitType.VEC_RGATHER) { 904 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 905 for (i <- 0 until len) 906 for (j <- 0 until len) { 907 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 908 // csBundle(i * len + j).srcType(1) := SrcType.vp 909 // csBundle(i * len + j).srcType(2) := SrcType.vp 910 csBundle(i * len + j).lsrc(0) := src1 + i.U 911 csBundle(i * len + j).lsrc(1) := src2 + j.U 912 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 913 csBundle(i * len + j).lsrc(2) := vd_old 914 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 915 csBundle(i * len + j).ldest := vd 916 csBundle(i * len + j).uopIdx := (i * len + j).U 917 } 918 } 919 switch(simple.io.enq.vtype.vlmul) { 920 is("b001".U ){ 921 genCsBundle_VEC_RGATHER(2) 922 } 923 is("b010".U ){ 924 genCsBundle_VEC_RGATHER(4) 925 } 926 is("b011".U ){ 927 genCsBundle_VEC_RGATHER(8) 928 } 929 } 930 } 931 is(UopSplitType.VEC_RGATHER_VX) { 932 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 933 for (i <- 0 until len) 934 for (j <- 0 until len) { 935 csBundle(i * len + j + 1).srcType(0) := SrcType.fp 936 // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 937 // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 938 csBundle(i * len + j + 1).lsrc(0) := FP_TMP_REG_MV.U 939 csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 940 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 941 csBundle(i * len + j + 1).lsrc(2) := vd_old 942 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 943 csBundle(i * len + j + 1).ldest := vd 944 csBundle(i * len + j + 1).uopIdx := (i * len + j).U 945 } 946 } 947 // FMV.D.X 948 csBundle(0).srcType(0) := SrcType.reg 949 csBundle(0).srcType(1) := SrcType.imm 950 csBundle(0).lsrc(1) := 0.U 951 csBundle(0).ldest := FP_TMP_REG_MV.U 952 csBundle(0).fuType := FuType.i2f.U 953 csBundle(0).rfWen := false.B 954 csBundle(0).fpWen := true.B 955 csBundle(0).vecWen := false.B 956 csBundle(0).fpu.isAddSub := false.B 957 csBundle(0).fpu.typeTagIn := FPU.D 958 csBundle(0).fpu.typeTagOut := FPU.D 959 csBundle(0).fpu.fromInt := true.B 960 csBundle(0).fpu.wflags := false.B 961 csBundle(0).fpu.fpWen := true.B 962 csBundle(0).fpu.div := false.B 963 csBundle(0).fpu.sqrt := false.B 964 csBundle(0).fpu.fcvt := false.B 965 switch(simple.io.enq.vtype.vlmul) { 966 is("b000".U ){ 967 genCsBundle_RGATHER_VX(1) 968 } 969 is("b001".U ){ 970 genCsBundle_RGATHER_VX(2) 971 } 972 is("b010".U ){ 973 genCsBundle_RGATHER_VX(4) 974 } 975 is("b011".U ){ 976 genCsBundle_RGATHER_VX(8) 977 } 978 } 979 } 980 is(UopSplitType.VEC_RGATHEREI16) { 981 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 982 for (i <- 0 until len) 983 for (j <- 0 until len) { 984 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 985 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 986 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 987 // csBundle(i * len + j).srcType(1) := SrcType.vp 988 // csBundle(i * len + j).srcType(2) := SrcType.vp 989 csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 990 csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 991 csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 992 csBundle((i * len + j)*2+0).ldest := vd0 993 csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 994 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 995 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 996 csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 997 csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 998 csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 999 csBundle((i * len + j)*2+1).ldest := vd1 1000 csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 1001 } 1002 } 1003 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 1004 for (i <- 0 until len) 1005 for (j <- 0 until len) { 1006 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 1007 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1008 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1009 // csBundle(i * len + j).srcType(1) := SrcType.vp 1010 // csBundle(i * len + j).srcType(2) := SrcType.vp 1011 csBundle(i * len + j).lsrc(0) := src1 + i.U 1012 csBundle(i * len + j).lsrc(1) := src2 + j.U 1013 csBundle(i * len + j).lsrc(2) := vd_old 1014 csBundle(i * len + j).ldest := vd 1015 csBundle(i * len + j).uopIdx := (i * len + j).U 1016 } 1017 } 1018 switch(simple.io.enq.vtype.vlmul) { 1019 is("b000".U ){ 1020 when(!simple.io.enq.vtype.vsew.orR){ 1021 genCsBundle_VEC_RGATHEREI16_SEW8(1) 1022 } .otherwise{ 1023 genCsBundle_VEC_RGATHEREI16(1) 1024 } 1025 } 1026 is("b001".U) { 1027 when(!simple.io.enq.vtype.vsew.orR) { 1028 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1029 }.otherwise { 1030 genCsBundle_VEC_RGATHEREI16(2) 1031 } 1032 } 1033 is("b010".U) { 1034 when(!simple.io.enq.vtype.vsew.orR) { 1035 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1036 }.otherwise { 1037 genCsBundle_VEC_RGATHEREI16(4) 1038 } 1039 } 1040 is("b011".U) { 1041 genCsBundle_VEC_RGATHEREI16(8) 1042 } 1043 } 1044 } 1045 is(UopSplitType.VEC_COMPRESS) { 1046 def genCsBundle_VEC_COMPRESS(len:Int): Unit ={ 1047 for (i <- 0 until len){ 1048 val jlen = if (i == len-1) i+1 else i+2 1049 for (j <- 0 until jlen) { 1050 val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1051 val vd = if(i==len-1) (dest + j.U) else{ 1052 if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1053 } 1054 val src23Type = if (j == i+1) DontCare else SrcType.vp 1055 csBundle(i*(i+3)/2 + j).srcType(0) := SrcType.vp 1056 csBundle(i*(i+3)/2 + j).srcType(1) := src23Type 1057 csBundle(i*(i+3)/2 + j).srcType(2) := src23Type 1058 csBundle(i*(i+3)/2 + j).lsrc(0) := src1 1059 csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1060 csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1061 // csBundle(i*(i+3)/2 + j).lsrc(3) := VECTOR_TMP_REG_LMUL.U 1062 csBundle(i*(i+3)/2 + j).ldest := vd 1063 csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1064 } 1065 } 1066 } 1067 switch(simple.io.enq.vtype.vlmul) { 1068 is("b001".U ){ 1069 genCsBundle_VEC_COMPRESS(2) 1070 } 1071 is("b010".U ){ 1072 genCsBundle_VEC_COMPRESS(4) 1073 } 1074 is("b011".U ){ 1075 genCsBundle_VEC_COMPRESS(8) 1076 } 1077 } 1078 } 1079 is(UopSplitType.VEC_US_LD) { 1080 /* 1081 FMV.D.X 1082 */ 1083 csBundle(0).srcType(0) := SrcType.reg 1084 csBundle(0).srcType(1) := SrcType.imm 1085 csBundle(0).lsrc(1) := 0.U 1086 csBundle(0).ldest := FP_TMP_REG_MV.U 1087 csBundle(0).fuType := FuType.i2f.U 1088 csBundle(0).rfWen := false.B 1089 csBundle(0).fpWen := true.B 1090 csBundle(0).vecWen := false.B 1091 csBundle(0).fpu.isAddSub := false.B 1092 csBundle(0).fpu.typeTagIn := FPU.D 1093 csBundle(0).fpu.typeTagOut := FPU.D 1094 csBundle(0).fpu.fromInt := true.B 1095 csBundle(0).fpu.wflags := false.B 1096 csBundle(0).fpu.fpWen := true.B 1097 csBundle(0).fpu.div := false.B 1098 csBundle(0).fpu.sqrt := false.B 1099 csBundle(0).fpu.fcvt := false.B 1100 //LMUL 1101 for (i <- 0 until MAX_VLMUL) { 1102 csBundle(i + 1).srcType(0) := SrcType.fp 1103 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1104 csBundle(i + 1).ldest := dest + i.U 1105 csBundle(i + 1).uopIdx := i.U 1106 } 1107 } 1108 } 1109 1110 //uops dispatch 1111 val s_normal :: s_ext :: Nil = Enum(2) 1112 val state = RegInit(s_normal) 1113 val state_next = WireDefault(state) 1114 val uopRes = RegInit(0.U) 1115 1116 //readyFromRename Counter 1117 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 1118 1119 switch(state) { 1120 is(s_normal) { 1121 state_next := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), s_ext, s_normal) 1122 } 1123 is(s_ext) { 1124 state_next := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), s_ext, s_normal) 1125 } 1126 } 1127 1128 state := state_next 1129 1130 val uopRes0 = Mux(state === s_normal, numOfUop, uopRes) 1131 val uopResJudge = Mux(state === s_normal, 1132 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 1133 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 1134 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 1135 1136 for(i <- 0 until RenameWidth) { 1137 decodedInsts(i) := MuxCase(csBundle(i), Seq( 1138 (state === s_normal) -> csBundle(i), 1139 (state === s_ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 1140 )) 1141 } 1142 1143 1144 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 1145 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1146 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 1147 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1148 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1149 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1150 notInfVec(0) := true.B 1151 1152 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1153 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1154 1.U) 1155 validToRename.zipWithIndex.foreach{ 1156 case(dst, i) => 1157 dst := MuxCase(false.B, Seq( 1158 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 1159 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1160 )) 1161 } 1162 1163 readyToIBuf.zipWithIndex.foreach { 1164 case (dst, i) => 1165 dst := MuxCase(true.B, Seq( 1166 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 1167 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 1168 )) 1169 } 1170 1171 io.deq.decodedInsts := decodedInsts 1172 io.deq.isVset := isVsetSimple 1173 io.deq.complexNum := complexNum 1174 io.deq.validToRename := validToRename 1175 io.deq.readyToIBuf := readyToIBuf 1176 1177} 1178