1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VpermType 31import scala.collection.Seq 32 33trait VectorConstants { 34 val MAX_VLMUL = 8 35 val INT_VCONFIG = 32 36 val FP_TMP_REG_MV = 32 37 val VECTOR_TMP_REG_LMUL = 32 // 32~46 -> 15 38} 39 40class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 41 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 42 val vconfig = Input(new VConfig) 43 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 44 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 45 val readyFromRename = Input(Vec(RenameWidth, Bool())) 46 val deq = new Bundle { 47 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 48 val isVset = Output(Bool()) 49 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 50 val validToRename = Output(Vec(RenameWidth, Bool())) 51 val complexNum = Output(UInt(3.W)) 52 } 53 val csrCtrl = Input(new CustomCSRCtrlIO) 54} 55 56class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 57 val io = IO(new DecodeUnitCompIO) 58 //input bits 59 val ctrl_flow = Wire(new CtrlFlow) 60 ctrl_flow := io.enq.ctrl_flow 61 //output bits 62 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 63 val validToRename = Wire(Vec(RenameWidth, Bool())) 64 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 65 val complexNum = Wire(UInt(3.W)) 66 67 //output of DecodeUnit 68 val cf_ctrl_u = Wire(new CfCtrl) 69 val isVset_u = Wire(Bool()) 70 71 //pre decode 72 val simple = Module(new DecodeUnit) 73 simple.io.enq.ctrl_flow := ctrl_flow 74 simple.io.vconfig := io.vconfig 75 simple.io.csrCtrl := io.csrCtrl 76 cf_ctrl_u := simple.io.deq.cf_ctrl 77 isVset_u := simple.io.deq.isVset 78 79 //Type of uop Div 80 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 81 82 //LMUL 83 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(4.W), Array( 84 "b001".U -> 2.U, 85 "b010".U -> 4.U, 86 "b011".U -> 8.U 87 )) 88 val numOfUopVslide = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(log2Up(maxNumOfUop+1).W), Array( 89 "b001".U -> 3.U, 90 "b010".U -> 10.U, 91 "b011".U -> 36.U 92 )) 93 val numOfUopVrgather = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(log2Up(maxNumOfUop+1).W), Array( 94 "b001".U -> 4.U, 95 "b010".U -> 16.U, 96 "b011".U -> 64.U 97 )) 98 val numOfUopVrgatherei16 = Mux((!simple.io.vconfig.vtype.vsew.orR()) && (simple.io.vconfig.vtype.vlmul =/= "b011".U), 99 Cat(numOfUopVrgather, 0.U(1.W)), 100 numOfUopVrgather 101 ) 102 //number of uop 103 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxNumOfUop+1).W), Array( 104 UopDivType.VEC_0XV -> 2.U, 105 UopDivType.DIR -> 2.U, 106 UopDivType.VEC_VVV -> lmul, 107 UopDivType.VEC_EXT2 -> lmul, 108 UopDivType.VEC_EXT4 -> lmul, 109 UopDivType.VEC_EXT8 -> lmul, 110 UopDivType.VEC_VVM -> lmul, 111 UopDivType.VEC_VXM -> (lmul +& 1.U), 112 UopDivType.VEC_VXV -> (lmul +& 1.U), 113 UopDivType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 114 UopDivType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 115 UopDivType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 116 UopDivType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 117 UopDivType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 118 UopDivType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 119 UopDivType.VEC_SLIDE1UP -> (lmul +& 1.U), 120 UopDivType.VEC_FSLIDE1UP -> lmul, 121 UopDivType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 122 UopDivType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 123 UopDivType.VEC_VRED -> lmul, 124 UopDivType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 125 UopDivType.VEC_ISLIDEUP -> numOfUopVslide, 126 UopDivType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 127 UopDivType.VEC_ISLIDEDOWN -> numOfUopVslide, 128 UopDivType.VEC_M0X -> (lmul +& 1.U), 129 UopDivType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) -1.U), 130 UopDivType.VEC_M0X_VFIRST -> 2.U, 131 UopDivType.VEC_VWW -> Cat(lmul, 0.U(1.W)), 132 UopDivType.VEC_RGATHER -> numOfUopVrgather, 133 UopDivType.VEC_RGATHER_VX -> (numOfUopVrgather +& 1.U), 134 UopDivType.VEC_RGATHEREI16 -> numOfUopVrgatherei16, 135 )) 136 137 val src1 = Cat(0.U(1.W), ctrl_flow.instr(19, 15)) 138 val src2 = Cat(0.U(1.W), ctrl_flow.instr(24, 20)) 139 val dest = Cat(0.U(1.W), ctrl_flow.instr(11, 7 )) 140 141 //uop div up to maxNumOfUop 142 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 143 csBundle.map { case dst => 144 dst := cf_ctrl_u 145 dst.ctrl.firstUop := false.B 146 dst.ctrl.lastUop := false.B 147 } 148 149 csBundle(0).ctrl.firstUop := true.B 150 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 151 152 switch(typeOfDiv) { 153 is(UopDivType.DIR) { 154 when(isVset_u) { 155 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR || ALUOpType.isVsetvl(cf_ctrl_u.ctrl.fuOpType) 156 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 157 csBundle(1).ctrl.ldest := INT_VCONFIG.U 158 csBundle(1).ctrl.flushPipe := false.B 159 } 160 } 161 is(UopDivType.VEC_VVV) { 162 for (i <- 0 until MAX_VLMUL) { 163 csBundle(i).ctrl.lsrc(0) := src1 + i.U 164 csBundle(i).ctrl.lsrc(1) := src2 + i.U 165 csBundle(i).ctrl.lsrc(2) := dest + i.U 166 csBundle(i).ctrl.ldest := dest + i.U 167 csBundle(i).ctrl.uopIdx := i.U 168 } 169 } 170 is(UopDivType.VEC_EXT2) { 171 for (i <- 0 until MAX_VLMUL / 2) { 172 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 173 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 174 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 175 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 176 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 177 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 178 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 179 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 180 } 181 } 182 is(UopDivType.VEC_EXT4) { 183 for (i <- 0 until MAX_VLMUL / 4) { 184 csBundle(4 * i).ctrl.lsrc(1) := src2 + i.U 185 csBundle(4 * i).ctrl.lsrc(2) := dest + (4 * i).U 186 csBundle(4 * i).ctrl.ldest := dest + (4 * i).U 187 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 188 csBundle(4 * i + 1).ctrl.lsrc(1) := src2 + i.U 189 csBundle(4 * i + 1).ctrl.lsrc(2) := dest + (4 * i + 1).U 190 csBundle(4 * i + 1).ctrl.ldest := dest + (4 * i + 1).U 191 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 192 csBundle(4 * i + 2).ctrl.lsrc(1) := src2 + i.U 193 csBundle(4 * i + 2).ctrl.lsrc(2) := dest + (4 * i + 2).U 194 csBundle(4 * i + 2).ctrl.ldest := dest + (4 * i + 2).U 195 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 196 csBundle(4 * i + 3).ctrl.lsrc(1) := src2 + i.U 197 csBundle(4 * i + 3).ctrl.lsrc(2) := dest + (4 * i + 3).U 198 csBundle(4 * i + 3).ctrl.ldest := dest + (4 * i + 3).U 199 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 200 } 201 } 202 is(UopDivType.VEC_EXT8) { 203 for (i <- 0 until MAX_VLMUL) { 204 csBundle(i).ctrl.lsrc(1) := src2 205 csBundle(i).ctrl.lsrc(2) := dest + i.U 206 csBundle(i).ctrl.ldest := dest + i.U 207 csBundle(i).ctrl.uopIdx := i.U 208 } 209 } 210 is(UopDivType.VEC_0XV) { 211 /* 212 FMV.D.X 213 */ 214 csBundle(0).ctrl.srcType(0) := SrcType.reg 215 csBundle(0).ctrl.srcType(1) := SrcType.imm 216 csBundle(0).ctrl.lsrc(1) := 0.U 217 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 218 csBundle(0).ctrl.fuType := FuType.i2f 219 csBundle(0).ctrl.rfWen := false.B 220 csBundle(0).ctrl.fpWen := true.B 221 csBundle(0).ctrl.vecWen := false.B 222 csBundle(0).ctrl.fpu.isAddSub := false.B 223 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 224 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 225 csBundle(0).ctrl.fpu.fromInt := true.B 226 csBundle(0).ctrl.fpu.wflags := false.B 227 csBundle(0).ctrl.fpu.fpWen := true.B 228 csBundle(0).ctrl.fpu.div := false.B 229 csBundle(0).ctrl.fpu.sqrt := false.B 230 csBundle(0).ctrl.fpu.fcvt := false.B 231 /* 232 vfmv.s.f 233 */ 234 csBundle(1).ctrl.srcType(0) := SrcType.fp 235 csBundle(1).ctrl.srcType(1) := SrcType.vp 236 csBundle(1).ctrl.srcType(2) := SrcType.vp 237 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 238 csBundle(1).ctrl.lsrc(1) := 0.U 239 csBundle(1).ctrl.lsrc(2) := dest 240 csBundle(1).ctrl.ldest := dest 241 csBundle(1).ctrl.fuType := FuType.vppu 242 csBundle(1).ctrl.fuOpType := VpermType.vfmv_s_f 243 csBundle(1).ctrl.rfWen := false.B 244 csBundle(1).ctrl.fpWen := false.B 245 csBundle(1).ctrl.vecWen := true.B 246 } 247 is(UopDivType.VEC_VXV) { 248 /* 249 FMV.D.X 250 */ 251 csBundle(0).ctrl.srcType(0) := SrcType.reg 252 csBundle(0).ctrl.srcType(1) := SrcType.imm 253 csBundle(0).ctrl.lsrc(1) := 0.U 254 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 255 csBundle(0).ctrl.fuType := FuType.i2f 256 csBundle(0).ctrl.rfWen := false.B 257 csBundle(0).ctrl.fpWen := true.B 258 csBundle(0).ctrl.vecWen := false.B 259 csBundle(0).ctrl.fpu.isAddSub := false.B 260 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 261 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 262 csBundle(0).ctrl.fpu.fromInt := true.B 263 csBundle(0).ctrl.fpu.wflags := false.B 264 csBundle(0).ctrl.fpu.fpWen := true.B 265 csBundle(0).ctrl.fpu.div := false.B 266 csBundle(0).ctrl.fpu.sqrt := false.B 267 csBundle(0).ctrl.fpu.fcvt := false.B 268 /* 269 LMUL 270 */ 271 for (i <- 0 until MAX_VLMUL) { 272 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 273 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 274 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 275 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 276 csBundle(i + 1).ctrl.ldest := dest + i.U 277 csBundle(i + 1).ctrl.uopIdx := i.U 278 } 279 } 280 is(UopDivType.VEC_VVW) { 281 for (i <- 0 until MAX_VLMUL / 2) { 282 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 283 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 284 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 285 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 286 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 287 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 288 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 289 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 290 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 291 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 292 } 293 } 294 is(UopDivType.VEC_WVW) { 295 for (i <- 0 until MAX_VLMUL / 2) { 296 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 297 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 298 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 299 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 300 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 301 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 302 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 303 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 304 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 305 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 306 } 307 } 308 is(UopDivType.VEC_VXW) { 309 /* 310 FMV.D.X 311 */ 312 csBundle(0).ctrl.srcType(0) := SrcType.reg 313 csBundle(0).ctrl.srcType(1) := SrcType.imm 314 csBundle(0).ctrl.lsrc(1) := 0.U 315 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 316 csBundle(0).ctrl.fuType := FuType.i2f 317 csBundle(0).ctrl.rfWen := false.B 318 csBundle(0).ctrl.fpWen := true.B 319 csBundle(0).ctrl.vecWen := false.B 320 csBundle(0).ctrl.fpu.isAddSub := false.B 321 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 322 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 323 csBundle(0).ctrl.fpu.fromInt := true.B 324 csBundle(0).ctrl.fpu.wflags := false.B 325 csBundle(0).ctrl.fpu.fpWen := true.B 326 csBundle(0).ctrl.fpu.div := false.B 327 csBundle(0).ctrl.fpu.sqrt := false.B 328 csBundle(0).ctrl.fpu.fcvt := false.B 329 330 for (i <- 0 until MAX_VLMUL / 2) { 331 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 332 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 333 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 334 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 335 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 336 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 337 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 338 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 339 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U 340 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 341 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 342 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 343 } 344 } 345 is(UopDivType.VEC_WXW) { 346 /* 347 FMV.D.X 348 */ 349 csBundle(0).ctrl.srcType(0) := SrcType.reg 350 csBundle(0).ctrl.srcType(1) := SrcType.imm 351 csBundle(0).ctrl.lsrc(1) := 0.U 352 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 353 csBundle(0).ctrl.fuType := FuType.i2f 354 csBundle(0).ctrl.rfWen := false.B 355 csBundle(0).ctrl.fpWen := true.B 356 csBundle(0).ctrl.vecWen := false.B 357 csBundle(0).ctrl.fpu.isAddSub := false.B 358 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 359 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 360 csBundle(0).ctrl.fpu.fromInt := true.B 361 csBundle(0).ctrl.fpu.wflags := false.B 362 csBundle(0).ctrl.fpu.fpWen := true.B 363 csBundle(0).ctrl.fpu.div := false.B 364 csBundle(0).ctrl.fpu.sqrt := false.B 365 csBundle(0).ctrl.fpu.fcvt := false.B 366 367 for (i <- 0 until MAX_VLMUL / 2) { 368 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 369 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 370 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 371 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 372 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 373 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 374 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 375 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 376 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 377 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 378 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 379 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 380 } 381 } 382 is(UopDivType.VEC_WVV) { 383 for (i <- 0 until MAX_VLMUL / 2) { 384 385 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 386 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 387 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 388 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 389 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 390 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 391 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 392 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 393 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 394 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 395 } 396 } 397 is(UopDivType.VEC_WXV) { 398 /* 399 FMV.D.X 400 */ 401 csBundle(0).ctrl.srcType(0) := SrcType.reg 402 csBundle(0).ctrl.srcType(1) := SrcType.imm 403 csBundle(0).ctrl.lsrc(1) := 0.U 404 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 405 csBundle(0).ctrl.fuType := FuType.i2f 406 csBundle(0).ctrl.rfWen := false.B 407 csBundle(0).ctrl.fpWen := true.B 408 csBundle(0).ctrl.vecWen := false.B 409 csBundle(0).ctrl.fpu.isAddSub := false.B 410 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 411 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 412 csBundle(0).ctrl.fpu.fromInt := true.B 413 csBundle(0).ctrl.fpu.wflags := false.B 414 csBundle(0).ctrl.fpu.fpWen := true.B 415 csBundle(0).ctrl.fpu.div := false.B 416 csBundle(0).ctrl.fpu.sqrt := false.B 417 csBundle(0).ctrl.fpu.fcvt := false.B 418 419 for (i <- 0 until MAX_VLMUL / 2) { 420 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 421 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 422 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 423 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 424 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 425 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 426 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 427 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 428 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 429 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 430 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 431 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 432 } 433 } 434 is(UopDivType.VEC_VVM) { 435 csBundle(0).ctrl.lsrc(2) := dest 436 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 437 csBundle(0).ctrl.uopIdx := 0.U 438 for(i <- 1 until MAX_VLMUL) { 439 csBundle(i).ctrl.lsrc(0) := src1 + i.U 440 csBundle(i).ctrl.lsrc(1) := src2 + i.U 441 csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 442 csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 443 csBundle(i).ctrl.uopIdx := i.U 444 } 445 csBundle(numOfUop - 1.U).ctrl.ldest := dest 446 } 447 is(UopDivType.VEC_VXM) { 448 /* 449 FMV.D.X 450 */ 451 csBundle(0).ctrl.srcType(0) := SrcType.reg 452 csBundle(0).ctrl.srcType(1) := SrcType.imm 453 csBundle(0).ctrl.lsrc(1) := 0.U 454 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 455 csBundle(0).ctrl.fuType := FuType.i2f 456 csBundle(0).ctrl.rfWen := false.B 457 csBundle(0).ctrl.fpWen := true.B 458 csBundle(0).ctrl.vecWen := false.B 459 csBundle(0).ctrl.fpu.isAddSub := false.B 460 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 461 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 462 csBundle(0).ctrl.fpu.fromInt := true.B 463 csBundle(0).ctrl.fpu.wflags := false.B 464 csBundle(0).ctrl.fpu.fpWen := true.B 465 csBundle(0).ctrl.fpu.div := false.B 466 csBundle(0).ctrl.fpu.sqrt := false.B 467 csBundle(0).ctrl.fpu.fcvt := false.B 468 //LMUL 469 csBundle(1).ctrl.srcType(0) := SrcType.fp 470 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 471 csBundle(1).ctrl.lsrc(2) := dest 472 csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 473 csBundle(1).ctrl.uopIdx := 0.U 474 for (i <- 1 until MAX_VLMUL) { 475 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 476 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 477 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 478 csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 479 csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 480 csBundle(i + 1).ctrl.uopIdx := i.U 481 } 482 csBundle(numOfUop - 1.U).ctrl.ldest := dest 483 } 484 is(UopDivType.VEC_SLIDE1UP) { 485 /* 486 FMV.D.X 487 */ 488 csBundle(0).ctrl.srcType(0) := SrcType.reg 489 csBundle(0).ctrl.srcType(1) := SrcType.imm 490 csBundle(0).ctrl.lsrc(1) := 0.U 491 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 492 csBundle(0).ctrl.fuType := FuType.i2f 493 csBundle(0).ctrl.rfWen := false.B 494 csBundle(0).ctrl.fpWen := true.B 495 csBundle(0).ctrl.vecWen := false.B 496 csBundle(0).ctrl.fpu.isAddSub := false.B 497 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 498 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 499 csBundle(0).ctrl.fpu.fromInt := true.B 500 csBundle(0).ctrl.fpu.wflags := false.B 501 csBundle(0).ctrl.fpu.fpWen := true.B 502 csBundle(0).ctrl.fpu.div := false.B 503 csBundle(0).ctrl.fpu.sqrt := false.B 504 csBundle(0).ctrl.fpu.fcvt := false.B 505 //LMUL 506 csBundle(1).ctrl.srcType(0) := SrcType.fp 507 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 508 csBundle(1).ctrl.lsrc(2) := dest 509 csBundle(1).ctrl.ldest := dest 510 csBundle(1).ctrl.uopIdx := 0.U 511 for (i <- 1 until MAX_VLMUL) { 512 csBundle(i + 1).ctrl.srcType(0) := SrcType.vp 513 csBundle(i + 1).ctrl.lsrc(0) := src2 + (i - 1).U 514 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 515 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 516 csBundle(i + 1).ctrl.ldest := dest + i.U 517 csBundle(i + 1).ctrl.uopIdx := i.U 518 } 519 } 520 is(UopDivType.VEC_FSLIDE1UP) { 521 //LMUL 522 csBundle(0).ctrl.srcType(0) := SrcType.fp 523 csBundle(0).ctrl.lsrc(0) := src1 524 csBundle(0).ctrl.lsrc(1) := src2 525 csBundle(0).ctrl.lsrc(2) := dest 526 csBundle(0).ctrl.ldest := dest 527 csBundle(0).ctrl.uopIdx := 0.U 528 for (i <- 1 until MAX_VLMUL) { 529 csBundle(i).ctrl.srcType(0) := SrcType.vp 530 csBundle(i).ctrl.lsrc(0) := src2 + (i - 1).U 531 csBundle(i).ctrl.lsrc(1) := src2 + i.U 532 csBundle(i).ctrl.lsrc(2) := dest + i.U 533 csBundle(i).ctrl.ldest := dest + i.U 534 csBundle(i).ctrl.uopIdx := i.U 535 } 536 } 537 is(UopDivType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 538 /* 539 FMV.D.X 540 */ 541 csBundle(0).ctrl.srcType(0) := SrcType.reg 542 csBundle(0).ctrl.srcType(1) := SrcType.imm 543 csBundle(0).ctrl.lsrc(1) := 0.U 544 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 545 csBundle(0).ctrl.fuType := FuType.i2f 546 csBundle(0).ctrl.rfWen := false.B 547 csBundle(0).ctrl.fpWen := true.B 548 csBundle(0).ctrl.vecWen := false.B 549 csBundle(0).ctrl.fpu.isAddSub := false.B 550 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 551 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 552 csBundle(0).ctrl.fpu.fromInt := true.B 553 csBundle(0).ctrl.fpu.wflags := false.B 554 csBundle(0).ctrl.fpu.fpWen := true.B 555 csBundle(0).ctrl.fpu.div := false.B 556 csBundle(0).ctrl.fpu.sqrt := false.B 557 csBundle(0).ctrl.fpu.fcvt := false.B 558 //LMUL 559 for (i <- 0 until MAX_VLMUL) { 560 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp 561 csBundle(2 * i + 1).ctrl.srcType(1) := SrcType.vp 562 csBundle(2 * i + 1).ctrl.lsrc(0) := src2 + (i+1).U 563 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 564 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 565 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 566 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 567 if (2 * i + 2 < MAX_VLMUL * 2 ){ 568 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 569 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 570 // csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U // DontCare 571 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 572 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 573 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 574 } 575 } 576 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 577 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := FP_TMP_REG_MV.U 578 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 579 } 580 is(UopDivType.VEC_FSLIDE1DOWN) { 581 //LMUL 582 for (i <- 0 until MAX_VLMUL) { 583 csBundle(2 * i).ctrl.srcType(0) := SrcType.vp 584 csBundle(2 * i).ctrl.srcType(1) := SrcType.vp 585 csBundle(2 * i).ctrl.lsrc(0) := src2 + (i+1).U 586 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 587 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 588 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 589 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 590 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 591 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 592 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 593 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 594 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 595 } 596 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 597 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1 598 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 599 } 600 is(UopDivType.VEC_VRED) { 601 when(simple.io.vconfig.vtype.vlmul === "b001".U){ 602 csBundle(0).ctrl.srcType(2) := SrcType.DC 603 csBundle(0).ctrl.lsrc(0) := src2 + 1.U 604 csBundle(0).ctrl.lsrc(1) := src2 605 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 606 csBundle(0).ctrl.uopIdx := 0.U 607 } 608 when(simple.io.vconfig.vtype.vlmul === "b010".U) { 609 csBundle(0).ctrl.srcType(2) := SrcType.DC 610 csBundle(0).ctrl.lsrc(0) := src2 + 1.U 611 csBundle(0).ctrl.lsrc(1) := src2 612 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 613 csBundle(0).ctrl.uopIdx := 0.U 614 615 csBundle(1).ctrl.srcType(2) := SrcType.DC 616 csBundle(1).ctrl.lsrc(0) := src2 + 3.U 617 csBundle(1).ctrl.lsrc(1) := src2 + 2.U 618 csBundle(1).ctrl.ldest := (VECTOR_TMP_REG_LMUL+1).U 619 csBundle(1).ctrl.uopIdx := 1.U 620 621 csBundle(2).ctrl.srcType(2) := SrcType.DC 622 csBundle(2).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL+1).U 623 csBundle(2).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U 624 csBundle(2).ctrl.ldest := (VECTOR_TMP_REG_LMUL+2).U 625 csBundle(2).ctrl.uopIdx := 2.U 626 } 627 when(simple.io.vconfig.vtype.vlmul === "b011".U) { 628 for(i <- 0 until MAX_VLMUL){ 629 if(i < MAX_VLMUL - MAX_VLMUL/2){ 630 csBundle(i).ctrl.lsrc(0) := src2 + (i * 2 + 1).U 631 csBundle(i).ctrl.lsrc(1) := src2 + (i * 2).U 632 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 633 } else if (i < MAX_VLMUL - MAX_VLMUL/4) { 634 csBundle(i).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2 + 1).U 635 csBundle(i).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2).U 636 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 637 }else if (i < MAX_VLMUL - MAX_VLMUL/8) { 638 csBundle(6).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 639 csBundle(6).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 640 csBundle(6).ctrl.ldest := (VECTOR_TMP_REG_LMUL + 6).U 641 } 642 csBundle(i).ctrl.srcType(2) := SrcType.DC 643 csBundle(i).ctrl.uopIdx := i.U 644 } 645 } 646 when (simple.io.vconfig.vtype.vlmul.orR()){ 647 csBundle(numOfUop - 1.U).ctrl.srcType(2) := SrcType.vp 648 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1 649 csBundle(numOfUop - 1.U).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 650 csBundle(numOfUop - 1.U).ctrl.lsrc(2) := dest 651 csBundle(numOfUop - 1.U).ctrl.ldest := dest 652 csBundle(numOfUop - 1.U).ctrl.uopIdx := numOfUop - 1.U 653 } 654 } 655 656 is(UopDivType.VEC_SLIDEUP) { 657 // FMV.D.X 658 csBundle(0).ctrl.srcType(0) := SrcType.reg 659 csBundle(0).ctrl.srcType(1) := SrcType.imm 660 csBundle(0).ctrl.lsrc(1) := 0.U 661 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 662 csBundle(0).ctrl.fuType := FuType.i2f 663 csBundle(0).ctrl.rfWen := false.B 664 csBundle(0).ctrl.fpWen := true.B 665 csBundle(0).ctrl.vecWen := false.B 666 csBundle(0).ctrl.fpu.isAddSub := false.B 667 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 668 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 669 csBundle(0).ctrl.fpu.fromInt := true.B 670 csBundle(0).ctrl.fpu.wflags := false.B 671 csBundle(0).ctrl.fpu.fpWen := true.B 672 csBundle(0).ctrl.fpu.div := false.B 673 csBundle(0).ctrl.fpu.sqrt := false.B 674 csBundle(0).ctrl.fpu.fcvt := false.B 675 // LMUL 676 for(i <- 0 until MAX_VLMUL) 677 for(j <- 0 to i){ 678 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 679 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 680 csBundle(i*(i+1)/2+j+1).ctrl.srcType(0) := SrcType.fp 681 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 682 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(1) := src2 + j.U 683 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(2) := old_vd 684 csBundle(i*(i+1)/2+j+1).ctrl.ldest := vd 685 csBundle(i*(i+1)/2+j+1).ctrl.uopIdx := (i*(i+1)/2+j).U 686 } 687 } 688 689 is(UopDivType.VEC_ISLIDEUP) { 690 // LMUL 691 for(i <- 0 until MAX_VLMUL) 692 for(j <- 0 to i){ 693 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 694 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 695 csBundle(i*(i+1)/2+j).ctrl.lsrc(1) := src2 + j.U 696 csBundle(i*(i+1)/2+j).ctrl.lsrc(2) := old_vd 697 csBundle(i*(i+1)/2+j).ctrl.ldest := vd 698 csBundle(i*(i+1)/2+j).ctrl.uopIdx := (i*(i+1)/2+j).U 699 } 700 } 701 702 is(UopDivType.VEC_SLIDEDOWN) { 703 // FMV.D.X 704 csBundle(0).ctrl.srcType(0) := SrcType.reg 705 csBundle(0).ctrl.srcType(1) := SrcType.imm 706 csBundle(0).ctrl.lsrc(1) := 0.U 707 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 708 csBundle(0).ctrl.fuType := FuType.i2f 709 csBundle(0).ctrl.rfWen := false.B 710 csBundle(0).ctrl.fpWen := true.B 711 csBundle(0).ctrl.vecWen := false.B 712 csBundle(0).ctrl.fpu.isAddSub := false.B 713 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 714 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 715 csBundle(0).ctrl.fpu.fromInt := true.B 716 csBundle(0).ctrl.fpu.wflags := false.B 717 csBundle(0).ctrl.fpu.fpWen := true.B 718 csBundle(0).ctrl.fpu.div := false.B 719 csBundle(0).ctrl.fpu.sqrt := false.B 720 csBundle(0).ctrl.fpu.fcvt := false.B 721 // LMUL 722 for(i <- 0 until MAX_VLMUL) 723 for(j <- (0 to i).reverse){ 724 when(i.U < lmul){ 725 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 726 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 727 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.srcType(0) := SrcType.fp 728 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(0) := FP_TMP_REG_MV.U 729 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(1) := src2 + lmul - 1.U - j.U 730 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(2) := old_vd 731 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.ldest := vd 732 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.uopIdx := numOfUop-(i*(i+1)/2+i-j+2).U 733 } 734 } 735 } 736 737 is(UopDivType.VEC_ISLIDEDOWN) { 738 // LMUL 739 for(i <- 0 until MAX_VLMUL) 740 for(j <- (0 to i).reverse){ 741 when(i.U < lmul){ 742 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 743 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 744 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(1) := src2 + lmul - 1.U - j.U 745 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(2) := old_vd 746 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.ldest := vd 747 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.uopIdx := numOfUop-(i*(i+1)/2+i-j+1).U 748 } 749 } 750 } 751 752 is(UopDivType.VEC_M0X) { 753 // LMUL 754 for (i <- 0 until MAX_VLMUL) { 755 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 756 val ldest = (VECTOR_TMP_REG_LMUL + i).U 757 csBundle(i).ctrl.srcType(0) := srcType0 758 csBundle(i).ctrl.srcType(1) := SrcType.vp 759 csBundle(i).ctrl.rfWen := false.B 760 csBundle(i).ctrl.vecWen := true.B 761 csBundle(i).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 762 csBundle(i).ctrl.lsrc(1) := src2 763 // csBundle(i).ctrl.lsrc(2) := dest + i.U DontCare 764 csBundle(i).ctrl.ldest := ldest 765 csBundle(i).ctrl.uopIdx := i.U 766 } 767 csBundle(lmul-1.U).ctrl.vecWen := false.B 768 csBundle(lmul-1.U).ctrl.fpWen := true.B 769 csBundle(lmul-1.U).ctrl.ldest := FP_TMP_REG_MV.U 770 // FMV_X_D 771 csBundle(lmul).ctrl.srcType(0) := SrcType.fp 772 csBundle(lmul).ctrl.srcType(1) := SrcType.imm 773 csBundle(lmul).ctrl.lsrc(0) := FP_TMP_REG_MV.U 774 csBundle(lmul).ctrl.lsrc(1) := 0.U 775 csBundle(lmul).ctrl.ldest := dest 776 csBundle(lmul).ctrl.fuType := FuType.fmisc 777 csBundle(lmul).ctrl.rfWen := true.B 778 csBundle(lmul).ctrl.fpWen := false.B 779 csBundle(lmul).ctrl.vecWen := false.B 780 csBundle(lmul).ctrl.fpu.isAddSub := false.B 781 csBundle(lmul).ctrl.fpu.typeTagIn := FPU.D 782 csBundle(lmul).ctrl.fpu.typeTagOut := FPU.D 783 csBundle(lmul).ctrl.fpu.fromInt := false.B 784 csBundle(lmul).ctrl.fpu.wflags := false.B 785 csBundle(lmul).ctrl.fpu.fpWen := false.B 786 csBundle(lmul).ctrl.fpu.div := false.B 787 csBundle(lmul).ctrl.fpu.sqrt := false.B 788 csBundle(lmul).ctrl.fpu.fcvt := false.B 789 } 790 791 is(UopDivType.VEC_MVV) { 792 // LMUL 793 for (i <- 0 until MAX_VLMUL) { 794 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 795 csBundle(i*2+0).ctrl.srcType(0) := srcType0 796 csBundle(i*2+0).ctrl.srcType(1) := SrcType.vp 797 csBundle(i*2+0).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 798 csBundle(i*2+0).ctrl.lsrc(1) := src2 799 csBundle(i*2+0).ctrl.lsrc(2) := dest + i.U 800 csBundle(i*2+0).ctrl.ldest := dest + i.U 801 csBundle(i*2+0).ctrl.uopIdx := (i*2+0).U 802 803 csBundle(i*2+1).ctrl.srcType(0) := srcType0 804 csBundle(i*2+1).ctrl.srcType(1) := SrcType.vp 805 csBundle(i*2+1).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 806 csBundle(i*2+1).ctrl.lsrc(1) := src2 807 // csBundle(i).ctrl.lsrc(2) := dest + i.U DontCare 808 csBundle(i*2+1).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 809 csBundle(i*2+1).ctrl.uopIdx := (i*2+1).U 810 } 811 } 812 813 is(UopDivType.VEC_M0X_VFIRST) { 814 // LMUL 815 csBundle(0).ctrl.rfWen := false.B 816 csBundle(0).ctrl.fpWen := true.B 817 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 818 // FMV_X_D 819 csBundle(1).ctrl.srcType(0) := SrcType.fp 820 csBundle(1).ctrl.srcType(1) := SrcType.imm 821 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 822 csBundle(1).ctrl.lsrc(1) := 0.U 823 csBundle(1).ctrl.ldest := dest 824 csBundle(1).ctrl.fuType := FuType.fmisc 825 csBundle(1).ctrl.rfWen := true.B 826 csBundle(1).ctrl.fpWen := false.B 827 csBundle(1).ctrl.vecWen := false.B 828 csBundle(1).ctrl.fpu.isAddSub := false.B 829 csBundle(1).ctrl.fpu.typeTagIn := FPU.D 830 csBundle(1).ctrl.fpu.typeTagOut := FPU.D 831 csBundle(1).ctrl.fpu.fromInt := false.B 832 csBundle(1).ctrl.fpu.wflags := false.B 833 csBundle(1).ctrl.fpu.fpWen := false.B 834 csBundle(1).ctrl.fpu.div := false.B 835 csBundle(1).ctrl.fpu.sqrt := false.B 836 csBundle(1).ctrl.fpu.fcvt := false.B 837 } 838 839 is(UopDivType.VEC_VWW) { 840 for (i <- 0 until MAX_VLMUL*2) { 841 when(i.U < lmul){ 842 csBundle(i).ctrl.srcType(2) := SrcType.DC 843 csBundle(i).ctrl.lsrc(0) := src2 + i.U 844 csBundle(i).ctrl.lsrc(1) := src2 + i.U 845 // csBundle(i).ctrl.lsrc(2) := dest + (2 * i).U 846 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 847 csBundle(i).ctrl.uopIdx := i.U 848 } otherwise { 849 csBundle(i).ctrl.srcType(2) := SrcType.DC 850 csBundle(i).ctrl.lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 851 csBundle(i).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 852 // csBundle(i).ctrl.lsrc(2) := dest + (2 * i).U 853 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 854 csBundle(i).ctrl.uopIdx := i.U 855 } 856 csBundle(numOfUop-1.U).ctrl.srcType(2) := SrcType.vp 857 csBundle(numOfUop-1.U).ctrl.lsrc(0) := src1 858 csBundle(numOfUop-1.U).ctrl.lsrc(2) := dest 859 csBundle(numOfUop-1.U).ctrl.ldest := dest 860 } 861 } 862 863 is(UopDivType.VEC_RGATHER) { 864 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 865 for (i <- 0 until len) 866 for (j <- 0 until len) { 867 // csBundle(i * len + j).ctrl.srcType(0) := SrcType.vp // SrcType.imm 868 // csBundle(i * len + j).ctrl.srcType(1) := SrcType.vp 869 // csBundle(i * len + j).ctrl.srcType(2) := SrcType.vp 870 csBundle(i * len + j).ctrl.lsrc(0) := src1 + i.U 871 csBundle(i * len + j).ctrl.lsrc(1) := src2 + j.U 872 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 873 csBundle(i * len + j).ctrl.lsrc(2) := vd_old 874 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 875 csBundle(i * len + j).ctrl.ldest := vd 876 csBundle(i * len + j).ctrl.uopIdx := (i * len + j).U 877 } 878 } 879 switch(simple.io.vconfig.vtype.vlmul) { 880 is("b001".U ){ 881 genCsBundle_VEC_RGATHER(2) 882 } 883 884 is("b010".U ){ 885 genCsBundle_VEC_RGATHER(4) 886 } 887 888 is("b011".U ){ 889 genCsBundle_VEC_RGATHER(8) 890 } 891 } 892 } 893 894 is(UopDivType.VEC_RGATHER_VX) { 895 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 896 for (i <- 0 until len) 897 for (j <- 0 until len) { 898 csBundle(i * len + j + 1).ctrl.srcType(0) := SrcType.fp 899 // csBundle(i * len + j + 1).ctrl.srcType(1) := SrcType.vp 900 // csBundle(i * len + j + 1).ctrl.srcType(2) := SrcType.vp 901 csBundle(i * len + j + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 902 csBundle(i * len + j + 1).ctrl.lsrc(1) := src2 + j.U 903 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 904 csBundle(i * len + j + 1).ctrl.lsrc(2) := vd_old 905 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 906 csBundle(i * len + j + 1).ctrl.ldest := vd 907 csBundle(i * len + j + 1).ctrl.uopIdx := (i * len + j).U 908 } 909 } 910 911 // FMV.D.X 912 csBundle(0).ctrl.srcType(0) := SrcType.reg 913 csBundle(0).ctrl.srcType(1) := SrcType.imm 914 csBundle(0).ctrl.lsrc(1) := 0.U 915 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 916 csBundle(0).ctrl.fuType := FuType.i2f 917 csBundle(0).ctrl.rfWen := false.B 918 csBundle(0).ctrl.fpWen := true.B 919 csBundle(0).ctrl.vecWen := false.B 920 csBundle(0).ctrl.fpu.isAddSub := false.B 921 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 922 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 923 csBundle(0).ctrl.fpu.fromInt := true.B 924 csBundle(0).ctrl.fpu.wflags := false.B 925 csBundle(0).ctrl.fpu.fpWen := true.B 926 csBundle(0).ctrl.fpu.div := false.B 927 csBundle(0).ctrl.fpu.sqrt := false.B 928 csBundle(0).ctrl.fpu.fcvt := false.B 929 930 switch(simple.io.vconfig.vtype.vlmul) { 931 is("b000".U ){ 932 genCsBundle_RGATHER_VX(1) 933 } 934 935 is("b001".U ){ 936 genCsBundle_RGATHER_VX(2) 937 } 938 939 is("b010".U ){ 940 genCsBundle_RGATHER_VX(4) 941 } 942 943 is("b011".U ){ 944 genCsBundle_RGATHER_VX(8) 945 } 946 } 947 } 948 949 is(UopDivType.VEC_RGATHEREI16) { 950 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 951 for (i <- 0 until len) 952 for (j <- 0 until len) { 953 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 954 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 955 // csBundle(i * len + j).ctrl.srcType(0) := SrcType.vp // SrcType.imm 956 // csBundle(i * len + j).ctrl.srcType(1) := SrcType.vp 957 // csBundle(i * len + j).ctrl.srcType(2) := SrcType.vp 958 csBundle((i * len + j)*2+0).ctrl.lsrc(0) := src1 + (i*2+0).U 959 csBundle((i * len + j)*2+0).ctrl.lsrc(1) := src2 + j.U 960 csBundle((i * len + j)*2+0).ctrl.lsrc(2) := vd_old0 961 csBundle((i * len + j)*2+0).ctrl.ldest := vd0 962 csBundle((i * len + j)*2+0).ctrl.uopIdx := ((i * len + j)*2+0).U 963 964 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 965 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 966 csBundle((i * len + j)*2+1).ctrl.lsrc(0) := src1 + (i*2+1).U 967 csBundle((i * len + j)*2+1).ctrl.lsrc(1) := src2 + j.U 968 csBundle((i * len + j)*2+1).ctrl.lsrc(2) := vd_old1 969 csBundle((i * len + j)*2+1).ctrl.ldest := vd1 970 csBundle((i * len + j)*2+1).ctrl.uopIdx := ((i * len + j)*2+1).U 971 } 972 } 973 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 974 for (i <- 0 until len) 975 for (j <- 0 until len) { 976 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 977 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 978 // csBundle(i * len + j).ctrl.srcType(0) := SrcType.vp // SrcType.imm 979 // csBundle(i * len + j).ctrl.srcType(1) := SrcType.vp 980 // csBundle(i * len + j).ctrl.srcType(2) := SrcType.vp 981 csBundle(i * len + j).ctrl.lsrc(0) := src1 + i.U 982 csBundle(i * len + j).ctrl.lsrc(1) := src2 + j.U 983 csBundle(i * len + j).ctrl.lsrc(2) := vd_old 984 csBundle(i * len + j).ctrl.ldest := vd 985 csBundle(i * len + j).ctrl.uopIdx := (i * len + j).U 986 } 987 } 988 switch(simple.io.vconfig.vtype.vlmul) { 989 is("b000".U ){ 990 when(!simple.io.vconfig.vtype.vsew.orR()){ 991 genCsBundle_VEC_RGATHEREI16_SEW8(1) 992 } .otherwise{ 993 genCsBundle_VEC_RGATHEREI16(1) 994 } 995 } 996 997 is("b001".U) { 998 when(!simple.io.vconfig.vtype.vsew.orR()) { 999 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1000 }.otherwise { 1001 genCsBundle_VEC_RGATHEREI16(2) 1002 } 1003 } 1004 1005 is("b010".U) { 1006 when(!simple.io.vconfig.vtype.vsew.orR()) { 1007 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1008 }.otherwise { 1009 genCsBundle_VEC_RGATHEREI16(4) 1010 } 1011 } 1012 1013 is("b011".U) { 1014 genCsBundle_VEC_RGATHEREI16(8) 1015 } 1016 } 1017 } 1018 } 1019 1020 //uops dispatch 1021 val normal :: ext :: Nil = Enum(2) 1022 val stateReg = RegInit(normal) 1023 val uopRes = RegInit(0.U) 1024 1025 //readyFromRename Counter 1026 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 1027 1028 switch(stateReg) { 1029 is(normal) { 1030 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 1031 } 1032 is(ext) { 1033 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 1034 } 1035 } 1036 1037 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 1038 val uopResJudge = Mux(stateReg === normal, 1039 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 1040 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 1041 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 1042 1043 for(i <- 0 until RenameWidth) { 1044 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 1045 (stateReg === normal) -> csBundle(i), 1046 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 1047 )) 1048 } 1049 1050 1051 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 1052 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1053 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 1054 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1055 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1056 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1057 notInfVec(0) := true.B 1058 1059 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1060 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1061 1.U) 1062 validToRename.zipWithIndex.foreach{ 1063 case(dst, i) => 1064 dst := MuxCase(false.B, Seq( 1065 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 1066 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1067 )) 1068 } 1069 1070 readyToIBuf.zipWithIndex.foreach { 1071 case (dst, i) => 1072 dst := MuxCase(true.B, Seq( 1073 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 1074 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 1075 )) 1076 } 1077 1078 io.deq.cf_ctrl := cf_ctrl 1079 io.deq.isVset := isVset_u 1080 io.deq.complexNum := complexNum 1081 io.deq.validToRename := validToRename 1082 io.deq.readyToIBuf := readyToIBuf 1083 1084} 1085 1086