1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VppuType 31import scala.collection.Seq 32 33class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 34 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 35 val vconfig = Input(new VConfig) 36 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 37 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 38 val readyFromRename = Input(Vec(RenameWidth, Bool())) 39 val deq = new Bundle { 40 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 41 val isVset = Output(Bool()) 42 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 43 val validToRename = Output(Vec(RenameWidth, Bool())) 44 val complexNum = Output(UInt(3.W)) 45 } 46 val csrCtrl = Input(new CustomCSRCtrlIO) 47} 48 49class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants { 50 val io = IO(new DecodeUnitCompIO) 51 //input bits 52 val ctrl_flow = Wire(new CtrlFlow) 53 ctrl_flow := io.enq.ctrl_flow 54 //output bits 55 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 56 val validToRename = Wire(Vec(RenameWidth, Bool())) 57 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 58 val complexNum = Wire(UInt(3.W)) 59 60 //output of DecodeUnit 61 val cf_ctrl_u = Wire(new CfCtrl) 62 val isVset_u = Wire(Bool()) 63 val isComplex_u = Wire(Bool()) 64 65 //pre decode 66 val simple = Module(new DecodeUnit) 67 simple.io.enq.ctrl_flow := ctrl_flow 68 simple.io.vconfig := io.vconfig 69 simple.io.csrCtrl := io.csrCtrl 70 cf_ctrl_u := simple.io.deq.cf_ctrl 71 isVset_u := simple.io.deq.isVset 72 isComplex_u := simple.io.deq.isComplex 73 74 //Type of uop Div 75 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 76 77 //LMUL 78 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U, Array( 79 "b001".U -> 2.U, 80 "b010".U -> 4.U, 81 "b011".U -> 8.U 82 )) 83 //number of uop 84 val numOfUop = MuxLookup(typeOfDiv, 1.U, Array( 85 UopDivType.VEC_MV -> 2.U, 86 UopDivType.DIR -> 2.U, 87 UopDivType.VEC_LMUL -> lmul, 88 UopDivType.VEC_EXT2 -> lmul, 89 UopDivType.VEC_EXT4 -> lmul, 90 UopDivType.VEC_EXT8 -> lmul, 91 UopDivType.VEC_MV_LMUL -> (lmul + 1.U), 92 UopDivType.VEC_WIDE -> (lmul + lmul), //lmul <= 4 93 UopDivType.VEC_WIDE0 -> (lmul + lmul), //lmul <= 4 94 UopDivType.VEC_MV_WIDE -> (lmul + lmul + 1.U), //lmul <= 4 95 UopDivType.VEC_MV_WIDE0 -> (lmul + lmul + 1.U), //lmul <= 4 96 UopDivType.VEC_NARROW -> (lmul + lmul), //lmul <= 4 97 UopDivType.VEC_MV_NARROW -> (lmul + lmul + 1.U) //lmul <= 4 98 )) 99 100 //uop div up to maxNumOfUop 101 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 102 csBundle.map { case dst => 103 dst := cf_ctrl_u 104 dst.ctrl.firstUop := false.B 105 dst.ctrl.lastUop := false.B 106 } 107 108 csBundle(0).ctrl.firstUop := true.B 109 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 110 111 switch(typeOfDiv) { 112 is(UopDivType.DIR) { 113 when(isVset_u) { 114 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR 115 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 116 csBundle(1).ctrl.ldest := 32.U 117 csBundle(1).ctrl.flushPipe := false.B 118 } 119 } 120 is(UopDivType.VEC_LMUL) { 121 for (i <- 0 until 8) { 122 csBundle(i).ctrl.srcType(3) := 0.U 123 csBundle(i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 124 csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 125 csBundle(i).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 126 csBundle(i).ctrl.uopIdx := i.U 127 } 128 } 129 is(UopDivType.VEC_EXT2) { 130 for (i <- 0 until 4) { 131 csBundle(2 * i).ctrl.srcType(3) := 0.U 132 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 133 csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 134 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 135 csBundle(2 * i + 1).ctrl.srcType(3) := 0.U 136 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 137 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 138 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 139 } 140 } 141 is(UopDivType.VEC_EXT4) { 142 for (i <- 0 until 2) { 143 csBundle(4 * i).ctrl.srcType(3) := 0.U 144 csBundle(4 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 145 csBundle(4 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i).U 146 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 147 csBundle(4 * i + 1).ctrl.srcType(3) := 0.U 148 csBundle(4 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 149 csBundle(4 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 1).U 150 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 151 csBundle(4 * i + 2).ctrl.srcType(3) := 0.U 152 csBundle(4 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 153 csBundle(4 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 2).U 154 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 155 csBundle(4 * i + 3).ctrl.srcType(3) := 0.U 156 csBundle(4 * i + 3).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 157 csBundle(4 * i + 3).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 3).U 158 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 159 } 160 } 161 is(UopDivType.VEC_EXT8) { 162 for (i <- 0 until 8) { 163 csBundle(i).ctrl.srcType(3) := 0.U 164 csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) 165 csBundle(i).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 166 csBundle(i).ctrl.uopIdx := i.U 167 } 168 } 169 is(UopDivType.VEC_MV) { 170 /* 171 FMV.D.X 172 */ 173 csBundle(0).ctrl.srcType(0) := SrcType.reg 174 csBundle(0).ctrl.srcType(1) := SrcType.imm 175 csBundle(0).ctrl.lsrc(1) := 0.U 176 csBundle(0).ctrl.ldest := 33.U 177 csBundle(0).ctrl.fuType := FuType.i2f 178 csBundle(0).ctrl.rfWen := false.B 179 csBundle(0).ctrl.fpWen := true.B 180 csBundle(0).ctrl.vecWen := false.B 181 csBundle(0).ctrl.fpu.isAddSub := false.B 182 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 183 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 184 csBundle(0).ctrl.fpu.fromInt := true.B 185 csBundle(0).ctrl.fpu.wflags := false.B 186 csBundle(0).ctrl.fpu.fpWen := true.B 187 csBundle(0).ctrl.fpu.div := false.B 188 csBundle(0).ctrl.fpu.sqrt := false.B 189 csBundle(0).ctrl.fpu.fcvt := false.B 190 /* 191 vfmv.s.f 192 */ 193 csBundle(1).ctrl.srcType(0) := SrcType.fp 194 csBundle(1).ctrl.srcType(1) := SrcType.vp 195 csBundle(1).ctrl.srcType(2) := SrcType.vp 196 csBundle(1).ctrl.lsrc(0) := 33.U 197 csBundle(1).ctrl.lsrc(1) := 0.U 198 csBundle(1).ctrl.lsrc(2) := ctrl_flow.instr(11, 7) 199 csBundle(1).ctrl.ldest := ctrl_flow.instr(11, 7) 200 csBundle(1).ctrl.fuType := FuType.vppu 201 csBundle(1).ctrl.fuOpType := VppuType.f2s 202 csBundle(1).ctrl.rfWen := false.B 203 csBundle(1).ctrl.fpWen := false.B 204 csBundle(1).ctrl.vecWen := true.B 205 } 206 is(UopDivType.VEC_MV_LMUL) { 207 /* 208 FMV.D.X 209 */ 210 csBundle(0).ctrl.srcType(0) := SrcType.reg 211 csBundle(0).ctrl.srcType(1) := SrcType.imm 212 csBundle(0).ctrl.lsrc(1) := 0.U 213 csBundle(0).ctrl.ldest := 33.U 214 csBundle(0).ctrl.fuType := FuType.i2f 215 csBundle(0).ctrl.rfWen := false.B 216 csBundle(0).ctrl.fpWen := false.B 217 csBundle(0).ctrl.vecWen := true.B 218 csBundle(0).ctrl.fpu.isAddSub := false.B 219 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 220 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 221 csBundle(0).ctrl.fpu.fromInt := true.B 222 csBundle(0).ctrl.fpu.wflags := false.B 223 csBundle(0).ctrl.fpu.fpWen := false.B 224 csBundle(0).ctrl.fpu.div := false.B 225 csBundle(0).ctrl.fpu.sqrt := false.B 226 csBundle(0).ctrl.fpu.fcvt := false.B 227 /* 228 LMUL 229 */ 230 for (i <- 0 until 8) { 231 csBundle(i + 1).ctrl.srcType(0) := SrcType.vp 232 csBundle(i + 1).ctrl.srcType(3) := 0.U 233 csBundle(i + 1).ctrl.lsrc(0) := 33.U 234 csBundle(i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 235 csBundle(i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 236 csBundle(i + 1).ctrl.uopIdx := i.U 237 } 238 } 239 is(UopDivType.VEC_WIDE) { 240 for (i <- 0 until 4) { 241 csBundle(2 * i).ctrl.srcType(3) := 0.U 242 csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 243 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 244 csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 245 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 246 csBundle(2 * i + 1).ctrl.srcType(3) := 0.U 247 csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 248 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 249 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 250 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 251 } 252 } 253 is(UopDivType.VEC_WIDE0) { 254 for (i <- 0 until 4) { 255 csBundle(2 * i).ctrl.srcType(3) := 0.U 256 csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 257 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 258 csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 259 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 260 csBundle(2 * i + 1).ctrl.srcType(3) := 0.U 261 csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 262 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 263 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 264 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 265 } 266 } 267 is(UopDivType.VEC_MV_WIDE) { 268 /* 269 FMV.D.X 270 */ 271 csBundle(0).ctrl.srcType(0) := SrcType.reg 272 csBundle(0).ctrl.srcType(1) := SrcType.imm 273 csBundle(0).ctrl.lsrc(1) := 0.U 274 csBundle(0).ctrl.ldest := 33.U 275 csBundle(0).ctrl.fuType := FuType.i2f 276 csBundle(0).ctrl.rfWen := false.B 277 csBundle(0).ctrl.fpWen := false.B 278 csBundle(0).ctrl.vecWen := true.B 279 csBundle(0).ctrl.fpu.isAddSub := false.B 280 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 281 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 282 csBundle(0).ctrl.fpu.fromInt := true.B 283 csBundle(0).ctrl.fpu.wflags := false.B 284 csBundle(0).ctrl.fpu.fpWen := false.B 285 csBundle(0).ctrl.fpu.div := false.B 286 csBundle(0).ctrl.fpu.sqrt := false.B 287 csBundle(0).ctrl.fpu.fcvt := false.B 288 289 for (i <- 0 until 4) { 290 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp 291 csBundle(2 * i + 1).ctrl.srcType(3) := 0.U 292 csBundle(2 * i + 1).ctrl.lsrc(0) := 33.U 293 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 294 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 295 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 296 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.vp 297 csBundle(2 * i + 2).ctrl.srcType(3) := 0.U 298 csBundle(2 * i + 2).ctrl.lsrc(0) := 33.U 299 csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 300 csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 301 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 302 } 303 } 304 is(UopDivType.VEC_MV_WIDE0) { 305 /* 306 FMV.D.X 307 */ 308 csBundle(0).ctrl.srcType(0) := SrcType.reg 309 csBundle(0).ctrl.srcType(1) := SrcType.imm 310 csBundle(0).ctrl.lsrc(1) := 0.U 311 csBundle(0).ctrl.ldest := 33.U 312 csBundle(0).ctrl.fuType := FuType.i2f 313 csBundle(0).ctrl.rfWen := false.B 314 csBundle(0).ctrl.fpWen := false.B 315 csBundle(0).ctrl.vecWen := true.B 316 csBundle(0).ctrl.fpu.isAddSub := false.B 317 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 318 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 319 csBundle(0).ctrl.fpu.fromInt := true.B 320 csBundle(0).ctrl.fpu.wflags := false.B 321 csBundle(0).ctrl.fpu.fpWen := false.B 322 csBundle(0).ctrl.fpu.div := false.B 323 csBundle(0).ctrl.fpu.sqrt := false.B 324 csBundle(0).ctrl.fpu.fcvt := false.B 325 326 for (i <- 0 until 4) { 327 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp 328 csBundle(2 * i + 1).ctrl.srcType(3) := 0.U 329 csBundle(2 * i + 1).ctrl.lsrc(0) := 33.U 330 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 331 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 332 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 333 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.vp 334 csBundle(2 * i + 2).ctrl.srcType(3) := 0.U 335 csBundle(2 * i + 2).ctrl.lsrc(0) := 33.U 336 csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 337 csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 338 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 339 } 340 } 341 is(UopDivType.VEC_NARROW) { 342 for (i <- 0 until 4) { 343 csBundle(2 * i).ctrl.srcType(3) := 0.U 344 csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 345 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 346 csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 347 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 348 csBundle(2 * i + 1).ctrl.srcType(3) := 0.U 349 csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 350 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 351 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 352 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 353 } 354 } 355 is(UopDivType.VEC_MV_NARROW) { 356 /* 357 FMV.D.X 358 */ 359 csBundle(0).ctrl.srcType(0) := SrcType.reg 360 csBundle(0).ctrl.srcType(1) := SrcType.imm 361 csBundle(0).ctrl.lsrc(1) := 0.U 362 csBundle(0).ctrl.ldest := 33.U 363 csBundle(0).ctrl.fuType := FuType.i2f 364 csBundle(0).ctrl.rfWen := false.B 365 csBundle(0).ctrl.fpWen := false.B 366 csBundle(0).ctrl.vecWen := true.B 367 csBundle(0).ctrl.fpu.isAddSub := false.B 368 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 369 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 370 csBundle(0).ctrl.fpu.fromInt := true.B 371 csBundle(0).ctrl.fpu.wflags := false.B 372 csBundle(0).ctrl.fpu.fpWen := false.B 373 csBundle(0).ctrl.fpu.div := false.B 374 csBundle(0).ctrl.fpu.sqrt := false.B 375 csBundle(0).ctrl.fpu.fcvt := false.B 376 377 for (i <- 0 until 4) { 378 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp 379 csBundle(2 * i + 1).ctrl.srcType(3) := 0.U 380 csBundle(2 * i + 1).ctrl.lsrc(0) := 33.U 381 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 382 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 383 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 384 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.vp 385 csBundle(2 * i + 2).ctrl.srcType(3) := 0.U 386 csBundle(2 * i + 2).ctrl.lsrc(0) := 33.U 387 csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 388 csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 389 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 390 } 391 } 392 } 393 394 //uops dispatch 395 val normal :: ext :: Nil = Enum(2) 396 val stateReg = RegInit(normal) 397 val uopRes = RegInit(0.U) 398 399 //readyFromRename Counter 400 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 401 402 switch(stateReg) { 403 is(normal) { 404 when(!io.validFromIBuf(0)) { 405 stateReg := normal 406 uopRes := 0.U 407 }.elsewhen((numOfUop > readyCounter) && (readyCounter =/= 0.U)){ 408 stateReg := ext 409 uopRes := numOfUop - readyCounter 410 }.otherwise { 411 stateReg := normal 412 uopRes := 0.U 413 } 414 } 415 is(ext) { 416 when(!io.validFromIBuf(0)) { 417 stateReg := normal 418 uopRes := 0.U 419 }.elsewhen(uopRes > readyCounter) { 420 stateReg := ext 421 uopRes := uopRes - readyCounter 422 }.otherwise { 423 stateReg := normal 424 uopRes := 0.U 425 } 426 } 427 } 428 429 for(i <- 0 until RenameWidth) { 430 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 431 (stateReg === normal) -> csBundle(i), 432 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 433 )) 434 } 435 436 437 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 438 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 439 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 440 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 441 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 442 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 443 notInfVec(0) := true.B 444 445 complexNum := 1.U 446 validToRename.map{ case dst => dst := false.B } 447 readyToIBuf .map{ case dst => dst := false.B } 448 switch(stateReg) { 449 is(normal) { 450 when(!io.validFromIBuf(0)) { 451 complexNum := 1.U 452 validToRename(0) := false.B 453 for (i <- 1 until RenameWidth) { 454 validToRename(i) := notInfVec(i - 1) && validSimple(i - 1) 455 } 456 readyToIBuf(0) := io.readyFromRename(0) 457 for(i <- 1 until DecodeWidth) { 458 readyToIBuf(i) := notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i) 459 } 460 }.elsewhen(numOfUop > readyCounter) { 461 complexNum := Mux(readyCounter === 0.U, 1.U, readyCounter) 462 for (i <- 0 until RenameWidth) { 463 validToRename(i) := Mux(readyCounter > i.U, true.B, false.B) 464 } 465 readyToIBuf.map{ case dst => dst := false.B } 466 }.otherwise { 467 complexNum := numOfUop 468 for (i <- 0 until RenameWidth) { 469 validToRename(i) := Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)) 470 } 471 readyToIBuf(0) := true.B 472 for (i <- 1 until DecodeWidth) { 473 readyToIBuf(i) := Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B) 474 } 475 } 476 } 477 is(ext) { 478 when(!io.validFromIBuf(0)) { 479 complexNum := 1.U 480 validToRename.map{ case dst => dst := false.B } 481 readyToIBuf.map{ case dst => dst := true.B } 482 }.elsewhen(uopRes > readyCounter) { 483 complexNum := Mux(readyCounter === 0.U, 1.U, readyCounter) 484 for (i <- 0 until RenameWidth) { 485 validToRename(i) := Mux(readyCounter > i.U, true.B, false.B) 486 } 487 readyToIBuf.map{ case dst => dst := false.B } 488 }.otherwise { 489 complexNum := uopRes 490 for (i <- 0 until RenameWidth) { 491 validToRename(i) := Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)) 492 } 493 readyToIBuf(0) := true.B 494 for (i <- 1 until DecodeWidth) { 495 readyToIBuf(i) := Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B) 496 } 497 } 498 } 499 } 500 501 io.deq.cf_ctrl := cf_ctrl 502 io.deq.isVset := isVset_u 503 io.deq.complexNum := complexNum 504 io.deq.validToRename := validToRename 505 io.deq.readyToIBuf := readyToIBuf 506 507} 508 509