1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VppuType 31import scala.collection.Seq 32 33trait VectorConstants { 34 val MAX_VLMUL = 8 35 val INT_VCONFIG = 32 36 val FP_TMP_REG_MV = 32 37 val VECTOR_TMP_REG_LMUL = 32 38} 39 40class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 41 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 42 val vconfig = Input(new VConfig) 43 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 44 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 45 val readyFromRename = Input(Vec(RenameWidth, Bool())) 46 val deq = new Bundle { 47 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 48 val isVset = Output(Bool()) 49 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 50 val validToRename = Output(Vec(RenameWidth, Bool())) 51 val complexNum = Output(UInt(3.W)) 52 } 53 val csrCtrl = Input(new CustomCSRCtrlIO) 54} 55 56class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 57 val io = IO(new DecodeUnitCompIO) 58 //input bits 59 val ctrl_flow = Wire(new CtrlFlow) 60 ctrl_flow := io.enq.ctrl_flow 61 //output bits 62 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 63 val validToRename = Wire(Vec(RenameWidth, Bool())) 64 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 65 val complexNum = Wire(UInt(3.W)) 66 67 //output of DecodeUnit 68 val cf_ctrl_u = Wire(new CfCtrl) 69 val isVset_u = Wire(Bool()) 70 71 //pre decode 72 val simple = Module(new DecodeUnit) 73 simple.io.enq.ctrl_flow := ctrl_flow 74 simple.io.vconfig := io.vconfig 75 simple.io.csrCtrl := io.csrCtrl 76 cf_ctrl_u := simple.io.deq.cf_ctrl 77 isVset_u := simple.io.deq.isVset 78 79 //Type of uop Div 80 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 81 82 //LMUL 83 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U, Array( 84 "b001".U -> 2.U, 85 "b010".U -> 4.U, 86 "b011".U -> 8.U 87 )) 88 //number of uop 89 val numOfUop = MuxLookup(typeOfDiv, 1.U, Array( 90 UopDivType.VEC_0XV -> 2.U, 91 UopDivType.DIR -> 2.U, 92 UopDivType.VEC_VVV -> lmul, 93 UopDivType.VEC_EXT2 -> lmul, 94 UopDivType.VEC_EXT4 -> lmul, 95 UopDivType.VEC_EXT8 -> lmul, 96 UopDivType.VEC_VVM -> lmul, 97 UopDivType.VEC_VXM -> (lmul + 1.U), 98 UopDivType.VEC_VXV -> (lmul + 1.U), 99 UopDivType.VEC_VVW -> (lmul + lmul), // lmul <= 4 100 UopDivType.VEC_WVW -> (lmul + lmul), // lmul <= 4 101 UopDivType.VEC_VXW -> (lmul + lmul + 1.U), // lmul <= 4 102 UopDivType.VEC_WXW -> (lmul + lmul + 1.U), // lmul <= 4 103 UopDivType.VEC_WVV -> (lmul + lmul), // lmul <= 4 104 UopDivType.VEC_WXV -> (lmul + lmul + 1.U), // lmul <= 4 105 UopDivType.VEC_SLIDE1UP -> (lmul + 1.U) 106 )) 107 108 val src1 = ctrl_flow.instr(19, 15) 109 val src2 = ctrl_flow.instr(24, 20) 110 val dest = ctrl_flow.instr(11, 7) 111 112 //uop div up to maxNumOfUop 113 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 114 csBundle.map { case dst => 115 dst := cf_ctrl_u 116 dst.ctrl.firstUop := false.B 117 dst.ctrl.lastUop := false.B 118 } 119 120 csBundle(0).ctrl.firstUop := true.B 121 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 122 123 switch(typeOfDiv) { 124 is(UopDivType.DIR) { 125 when(isVset_u) { 126 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR || ALUOpType.isVsetvl(cf_ctrl_u.ctrl.fuOpType) 127 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 128 csBundle(1).ctrl.ldest := INT_VCONFIG.U 129 csBundle(1).ctrl.flushPipe := false.B 130 } 131 } 132 is(UopDivType.VEC_VVV) { 133 for (i <- 0 until MAX_VLMUL) { 134 csBundle(i).ctrl.lsrc(0) := src1 + i.U 135 csBundle(i).ctrl.lsrc(1) := src2 + i.U 136 csBundle(i).ctrl.lsrc(2) := dest + i.U 137 csBundle(i).ctrl.ldest := dest + i.U 138 csBundle(i).ctrl.uopIdx := i.U 139 } 140 } 141 is(UopDivType.VEC_EXT2) { 142 for (i <- 0 until MAX_VLMUL / 2) { 143 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 144 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 145 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 146 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 147 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 148 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 149 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 150 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 151 } 152 } 153 is(UopDivType.VEC_EXT4) { 154 for (i <- 0 until MAX_VLMUL / 4) { 155 csBundle(4 * i).ctrl.lsrc(1) := src2 + i.U 156 csBundle(4 * i).ctrl.lsrc(2) := dest + (4 * i).U 157 csBundle(4 * i).ctrl.ldest := dest + (4 * i).U 158 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 159 csBundle(4 * i + 1).ctrl.lsrc(1) := src2 + i.U 160 csBundle(4 * i + 1).ctrl.lsrc(2) := dest + (4 * i + 1).U 161 csBundle(4 * i + 1).ctrl.ldest := dest + (4 * i + 1).U 162 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 163 csBundle(4 * i + 2).ctrl.lsrc(1) := src2 + i.U 164 csBundle(4 * i + 2).ctrl.lsrc(2) := dest + (4 * i + 2).U 165 csBundle(4 * i + 2).ctrl.ldest := dest + (4 * i + 2).U 166 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 167 csBundle(4 * i + 3).ctrl.lsrc(1) := src2 + i.U 168 csBundle(4 * i + 3).ctrl.lsrc(2) := dest + (4 * i + 3).U 169 csBundle(4 * i + 3).ctrl.ldest := dest + (4 * i + 3).U 170 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 171 } 172 } 173 is(UopDivType.VEC_EXT8) { 174 for (i <- 0 until MAX_VLMUL) { 175 csBundle(i).ctrl.lsrc(1) := src2 176 csBundle(i).ctrl.lsrc(2) := dest + i.U 177 csBundle(i).ctrl.ldest := dest + i.U 178 csBundle(i).ctrl.uopIdx := i.U 179 } 180 } 181 is(UopDivType.VEC_0XV) { 182 /* 183 FMV.D.X 184 */ 185 csBundle(0).ctrl.srcType(0) := SrcType.reg 186 csBundle(0).ctrl.srcType(1) := SrcType.imm 187 csBundle(0).ctrl.lsrc(1) := 0.U 188 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 189 csBundle(0).ctrl.fuType := FuType.i2f 190 csBundle(0).ctrl.rfWen := false.B 191 csBundle(0).ctrl.fpWen := true.B 192 csBundle(0).ctrl.vecWen := false.B 193 csBundle(0).ctrl.fpu.isAddSub := false.B 194 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 195 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 196 csBundle(0).ctrl.fpu.fromInt := true.B 197 csBundle(0).ctrl.fpu.wflags := false.B 198 csBundle(0).ctrl.fpu.fpWen := true.B 199 csBundle(0).ctrl.fpu.div := false.B 200 csBundle(0).ctrl.fpu.sqrt := false.B 201 csBundle(0).ctrl.fpu.fcvt := false.B 202 /* 203 vfmv.s.f 204 */ 205 csBundle(1).ctrl.srcType(0) := SrcType.fp 206 csBundle(1).ctrl.srcType(1) := SrcType.vp 207 csBundle(1).ctrl.srcType(2) := SrcType.vp 208 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 209 csBundle(1).ctrl.lsrc(1) := 0.U 210 csBundle(1).ctrl.lsrc(2) := dest 211 csBundle(1).ctrl.ldest := dest 212 csBundle(1).ctrl.fuType := FuType.vppu 213 csBundle(1).ctrl.fuOpType := VppuType.f2s 214 csBundle(1).ctrl.rfWen := false.B 215 csBundle(1).ctrl.fpWen := false.B 216 csBundle(1).ctrl.vecWen := true.B 217 } 218 is(UopDivType.VEC_VXV) { 219 /* 220 FMV.D.X 221 */ 222 csBundle(0).ctrl.srcType(0) := SrcType.reg 223 csBundle(0).ctrl.srcType(1) := SrcType.imm 224 csBundle(0).ctrl.lsrc(1) := 0.U 225 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 226 csBundle(0).ctrl.fuType := FuType.i2f 227 csBundle(0).ctrl.rfWen := false.B 228 csBundle(0).ctrl.fpWen := true.B 229 csBundle(0).ctrl.vecWen := false.B 230 csBundle(0).ctrl.fpu.isAddSub := false.B 231 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 232 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 233 csBundle(0).ctrl.fpu.fromInt := true.B 234 csBundle(0).ctrl.fpu.wflags := false.B 235 csBundle(0).ctrl.fpu.fpWen := true.B 236 csBundle(0).ctrl.fpu.div := false.B 237 csBundle(0).ctrl.fpu.sqrt := false.B 238 csBundle(0).ctrl.fpu.fcvt := false.B 239 /* 240 LMUL 241 */ 242 for (i <- 0 until MAX_VLMUL) { 243 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 244 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 245 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 246 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 247 csBundle(i + 1).ctrl.ldest := dest + i.U 248 csBundle(i + 1).ctrl.uopIdx := i.U 249 } 250 } 251 is(UopDivType.VEC_VVW) { 252 for (i <- 0 until MAX_VLMUL / 2) { 253 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 254 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 255 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 256 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 257 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 258 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 259 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 260 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 261 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 262 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 263 } 264 } 265 is(UopDivType.VEC_WVW) { 266 for (i <- 0 until MAX_VLMUL / 2) { 267 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 268 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 269 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 270 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 271 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 272 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 273 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 274 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 275 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 276 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 277 } 278 } 279 is(UopDivType.VEC_VXW) { 280 /* 281 FMV.D.X 282 */ 283 csBundle(0).ctrl.srcType(0) := SrcType.reg 284 csBundle(0).ctrl.srcType(1) := SrcType.imm 285 csBundle(0).ctrl.lsrc(1) := 0.U 286 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 287 csBundle(0).ctrl.fuType := FuType.i2f 288 csBundle(0).ctrl.rfWen := false.B 289 csBundle(0).ctrl.fpWen := true.B 290 csBundle(0).ctrl.vecWen := false.B 291 csBundle(0).ctrl.fpu.isAddSub := false.B 292 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 293 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 294 csBundle(0).ctrl.fpu.fromInt := true.B 295 csBundle(0).ctrl.fpu.wflags := false.B 296 csBundle(0).ctrl.fpu.fpWen := true.B 297 csBundle(0).ctrl.fpu.div := false.B 298 csBundle(0).ctrl.fpu.sqrt := false.B 299 csBundle(0).ctrl.fpu.fcvt := false.B 300 301 for (i <- 0 until MAX_VLMUL / 2) { 302 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 303 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 304 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 305 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 306 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 307 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 308 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 309 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 310 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U 311 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 312 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 313 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 314 } 315 } 316 is(UopDivType.VEC_WXW) { 317 /* 318 FMV.D.X 319 */ 320 csBundle(0).ctrl.srcType(0) := SrcType.reg 321 csBundle(0).ctrl.srcType(1) := SrcType.imm 322 csBundle(0).ctrl.lsrc(1) := 0.U 323 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 324 csBundle(0).ctrl.fuType := FuType.i2f 325 csBundle(0).ctrl.rfWen := false.B 326 csBundle(0).ctrl.fpWen := true.B 327 csBundle(0).ctrl.vecWen := false.B 328 csBundle(0).ctrl.fpu.isAddSub := false.B 329 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 330 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 331 csBundle(0).ctrl.fpu.fromInt := true.B 332 csBundle(0).ctrl.fpu.wflags := false.B 333 csBundle(0).ctrl.fpu.fpWen := true.B 334 csBundle(0).ctrl.fpu.div := false.B 335 csBundle(0).ctrl.fpu.sqrt := false.B 336 csBundle(0).ctrl.fpu.fcvt := false.B 337 338 for (i <- 0 until MAX_VLMUL / 2) { 339 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 340 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 341 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 342 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 343 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 344 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 345 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 346 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 347 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 348 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 349 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 350 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 351 } 352 } 353 is(UopDivType.VEC_WVV) { 354 for (i <- 0 until MAX_VLMUL / 2) { 355 356 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 357 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 358 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 359 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 360 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 361 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 362 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 363 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 364 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 365 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 366 } 367 } 368 is(UopDivType.VEC_WXV) { 369 /* 370 FMV.D.X 371 */ 372 csBundle(0).ctrl.srcType(0) := SrcType.reg 373 csBundle(0).ctrl.srcType(1) := SrcType.imm 374 csBundle(0).ctrl.lsrc(1) := 0.U 375 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 376 csBundle(0).ctrl.fuType := FuType.i2f 377 csBundle(0).ctrl.rfWen := false.B 378 csBundle(0).ctrl.fpWen := true.B 379 csBundle(0).ctrl.vecWen := false.B 380 csBundle(0).ctrl.fpu.isAddSub := false.B 381 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 382 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 383 csBundle(0).ctrl.fpu.fromInt := true.B 384 csBundle(0).ctrl.fpu.wflags := false.B 385 csBundle(0).ctrl.fpu.fpWen := true.B 386 csBundle(0).ctrl.fpu.div := false.B 387 csBundle(0).ctrl.fpu.sqrt := false.B 388 csBundle(0).ctrl.fpu.fcvt := false.B 389 390 for (i <- 0 until MAX_VLMUL / 2) { 391 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 392 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 393 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 394 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 395 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 396 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 397 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 398 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 399 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 400 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 401 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 402 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 403 } 404 } 405 is(UopDivType.VEC_VVM) { 406 csBundle(0).ctrl.lsrc(2) := dest 407 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 408 csBundle(0).ctrl.uopIdx := 0.U 409 for(i <- 1 until MAX_VLMUL) { 410 csBundle(i).ctrl.lsrc(0) := src1 + i.U 411 csBundle(i).ctrl.lsrc(1) := src2 + i.U 412 csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 413 csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 414 csBundle(i).ctrl.uopIdx := i.U 415 } 416 csBundle(numOfUop - 1.U).ctrl.ldest := dest 417 } 418 is(UopDivType.VEC_VXM) { 419 /* 420 FMV.D.X 421 */ 422 csBundle(0).ctrl.srcType(0) := SrcType.reg 423 csBundle(0).ctrl.srcType(1) := SrcType.imm 424 csBundle(0).ctrl.lsrc(1) := 0.U 425 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 426 csBundle(0).ctrl.fuType := FuType.i2f 427 csBundle(0).ctrl.rfWen := false.B 428 csBundle(0).ctrl.fpWen := true.B 429 csBundle(0).ctrl.vecWen := false.B 430 csBundle(0).ctrl.fpu.isAddSub := false.B 431 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 432 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 433 csBundle(0).ctrl.fpu.fromInt := true.B 434 csBundle(0).ctrl.fpu.wflags := false.B 435 csBundle(0).ctrl.fpu.fpWen := true.B 436 csBundle(0).ctrl.fpu.div := false.B 437 csBundle(0).ctrl.fpu.sqrt := false.B 438 csBundle(0).ctrl.fpu.fcvt := false.B 439 //LMUL 440 csBundle(1).ctrl.srcType(0) := SrcType.fp 441 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 442 csBundle(1).ctrl.lsrc(2) := dest 443 csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 444 csBundle(1).ctrl.uopIdx := 0.U 445 for (i <- 1 until MAX_VLMUL) { 446 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 447 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 448 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 449 csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 450 csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 451 csBundle(i + 1).ctrl.uopIdx := i.U 452 } 453 csBundle(numOfUop - 1.U).ctrl.ldest := dest 454 } 455 is(UopDivType.VEC_SLIDE1UP) { 456 /* 457 FMV.D.X 458 */ 459 csBundle(0).ctrl.srcType(0) := SrcType.reg 460 csBundle(0).ctrl.srcType(1) := SrcType.imm 461 csBundle(0).ctrl.lsrc(1) := 0.U 462 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 463 csBundle(0).ctrl.fuType := FuType.i2f 464 csBundle(0).ctrl.rfWen := false.B 465 csBundle(0).ctrl.fpWen := true.B 466 csBundle(0).ctrl.vecWen := false.B 467 csBundle(0).ctrl.fpu.isAddSub := false.B 468 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 469 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 470 csBundle(0).ctrl.fpu.fromInt := true.B 471 csBundle(0).ctrl.fpu.wflags := false.B 472 csBundle(0).ctrl.fpu.fpWen := true.B 473 csBundle(0).ctrl.fpu.div := false.B 474 csBundle(0).ctrl.fpu.sqrt := false.B 475 csBundle(0).ctrl.fpu.fcvt := false.B 476 //LMUL 477 csBundle(1).ctrl.srcType(0) := SrcType.fp 478 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 479 csBundle(1).ctrl.lsrc(2) := dest 480 csBundle(1).ctrl.ldest := dest 481 csBundle(1).ctrl.uopIdx := 0.U 482 for (i <- 1 until MAX_VLMUL) { 483 csBundle(i + 1).ctrl.srcType(0) := SrcType.vp 484 csBundle(i + 1).ctrl.lsrc(0) := src2 + (i - 1).U 485 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 486 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 487 csBundle(i + 1).ctrl.ldest := dest + i.U 488 csBundle(i + 1).ctrl.uopIdx := i.U 489 } 490 } 491 } 492 493 //uops dispatch 494 val normal :: ext :: Nil = Enum(2) 495 val stateReg = RegInit(normal) 496 val uopRes = RegInit(0.U) 497 498 //readyFromRename Counter 499 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 500 501 switch(stateReg) { 502 is(normal) { 503 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 504 } 505 is(ext) { 506 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 507 } 508 } 509 510 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 511 val uopResJudge = Mux(stateReg === normal, 512 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 513 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 514 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 515 516 for(i <- 0 until RenameWidth) { 517 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 518 (stateReg === normal) -> csBundle(i), 519 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 520 )) 521 } 522 523 524 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 525 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 526 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 527 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 528 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 529 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 530 notInfVec(0) := true.B 531 532 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 533 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 534 1.U) 535 validToRename.zipWithIndex.foreach{ 536 case(dst, i) => 537 dst := MuxCase(false.B, Seq( 538 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 539 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 540 )) 541 } 542 543 readyToIBuf.zipWithIndex.foreach { 544 case (dst, i) => 545 dst := MuxCase(true.B, Seq( 546 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 547 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 548 )) 549 } 550 551 io.deq.cf_ctrl := cf_ctrl 552 io.deq.isVset := isVset_u 553 io.deq.complexNum := complexNum 554 io.deq.validToRename := validToRename 555 io.deq.readyToIBuf := readyToIBuf 556 557} 558 559