1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VpermType 31import scala.collection.Seq 32 33trait VectorConstants { 34 val MAX_VLMUL = 8 35 val INT_VCONFIG = 32 36 val FP_TMP_REG_MV = 32 37 val VECTOR_TMP_REG_LMUL = 32 38} 39 40class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 41 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 42 val vconfig = Input(new VConfig) 43 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 44 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 45 val readyFromRename = Input(Vec(RenameWidth, Bool())) 46 val deq = new Bundle { 47 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 48 val isVset = Output(Bool()) 49 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 50 val validToRename = Output(Vec(RenameWidth, Bool())) 51 val complexNum = Output(UInt(3.W)) 52 } 53 val csrCtrl = Input(new CustomCSRCtrlIO) 54} 55 56class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 57 val io = IO(new DecodeUnitCompIO) 58 //input bits 59 val ctrl_flow = Wire(new CtrlFlow) 60 ctrl_flow := io.enq.ctrl_flow 61 //output bits 62 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 63 val validToRename = Wire(Vec(RenameWidth, Bool())) 64 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 65 val complexNum = Wire(UInt(3.W)) 66 67 //output of DecodeUnit 68 val cf_ctrl_u = Wire(new CfCtrl) 69 val isVset_u = Wire(Bool()) 70 71 //pre decode 72 val simple = Module(new DecodeUnit) 73 simple.io.enq.ctrl_flow := ctrl_flow 74 simple.io.vconfig := io.vconfig 75 simple.io.csrCtrl := io.csrCtrl 76 cf_ctrl_u := simple.io.deq.cf_ctrl 77 isVset_u := simple.io.deq.isVset 78 79 //Type of uop Div 80 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 81 82 //LMUL 83 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(4.W), Array( 84 "b001".U -> 2.U, 85 "b010".U -> 4.U, 86 "b011".U -> 8.U 87 )) 88 //number of uop 89 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxNumOfUop+1).W), Array( 90 UopDivType.VEC_0XV -> 2.U, 91 UopDivType.DIR -> 2.U, 92 UopDivType.VEC_VVV -> lmul, 93 UopDivType.VEC_EXT2 -> lmul, 94 UopDivType.VEC_EXT4 -> lmul, 95 UopDivType.VEC_EXT8 -> lmul, 96 UopDivType.VEC_VVM -> lmul, 97 UopDivType.VEC_VXM -> (lmul +& 1.U), 98 UopDivType.VEC_VXV -> (lmul +& 1.U), 99 UopDivType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 100 UopDivType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 101 UopDivType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 102 UopDivType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 103 UopDivType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 104 UopDivType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 105 UopDivType.VEC_SLIDE1UP -> (lmul +& 1.U), 106 UopDivType.VEC_FSLIDE1UP -> lmul, 107 UopDivType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 108 UopDivType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 109 )) 110 111 val src1 = ctrl_flow.instr(19, 15) 112 val src2 = ctrl_flow.instr(24, 20) 113 val dest = ctrl_flow.instr(11, 7) 114 115 //uop div up to maxNumOfUop 116 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 117 csBundle.map { case dst => 118 dst := cf_ctrl_u 119 dst.ctrl.firstUop := false.B 120 dst.ctrl.lastUop := false.B 121 } 122 123 csBundle(0).ctrl.firstUop := true.B 124 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 125 126 switch(typeOfDiv) { 127 is(UopDivType.DIR) { 128 when(isVset_u) { 129 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR || ALUOpType.isVsetvl(cf_ctrl_u.ctrl.fuOpType) 130 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 131 csBundle(1).ctrl.ldest := INT_VCONFIG.U 132 csBundle(1).ctrl.flushPipe := false.B 133 } 134 } 135 is(UopDivType.VEC_VVV) { 136 for (i <- 0 until MAX_VLMUL) { 137 csBundle(i).ctrl.lsrc(0) := src1 + i.U 138 csBundle(i).ctrl.lsrc(1) := src2 + i.U 139 csBundle(i).ctrl.lsrc(2) := dest + i.U 140 csBundle(i).ctrl.ldest := dest + i.U 141 csBundle(i).ctrl.uopIdx := i.U 142 } 143 } 144 is(UopDivType.VEC_EXT2) { 145 for (i <- 0 until MAX_VLMUL / 2) { 146 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 147 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 148 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 149 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 150 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 151 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 152 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 153 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 154 } 155 } 156 is(UopDivType.VEC_EXT4) { 157 for (i <- 0 until MAX_VLMUL / 4) { 158 csBundle(4 * i).ctrl.lsrc(1) := src2 + i.U 159 csBundle(4 * i).ctrl.lsrc(2) := dest + (4 * i).U 160 csBundle(4 * i).ctrl.ldest := dest + (4 * i).U 161 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 162 csBundle(4 * i + 1).ctrl.lsrc(1) := src2 + i.U 163 csBundle(4 * i + 1).ctrl.lsrc(2) := dest + (4 * i + 1).U 164 csBundle(4 * i + 1).ctrl.ldest := dest + (4 * i + 1).U 165 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 166 csBundle(4 * i + 2).ctrl.lsrc(1) := src2 + i.U 167 csBundle(4 * i + 2).ctrl.lsrc(2) := dest + (4 * i + 2).U 168 csBundle(4 * i + 2).ctrl.ldest := dest + (4 * i + 2).U 169 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 170 csBundle(4 * i + 3).ctrl.lsrc(1) := src2 + i.U 171 csBundle(4 * i + 3).ctrl.lsrc(2) := dest + (4 * i + 3).U 172 csBundle(4 * i + 3).ctrl.ldest := dest + (4 * i + 3).U 173 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 174 } 175 } 176 is(UopDivType.VEC_EXT8) { 177 for (i <- 0 until MAX_VLMUL) { 178 csBundle(i).ctrl.lsrc(1) := src2 179 csBundle(i).ctrl.lsrc(2) := dest + i.U 180 csBundle(i).ctrl.ldest := dest + i.U 181 csBundle(i).ctrl.uopIdx := i.U 182 } 183 } 184 is(UopDivType.VEC_0XV) { 185 /* 186 FMV.D.X 187 */ 188 csBundle(0).ctrl.srcType(0) := SrcType.reg 189 csBundle(0).ctrl.srcType(1) := SrcType.imm 190 csBundle(0).ctrl.lsrc(1) := 0.U 191 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 192 csBundle(0).ctrl.fuType := FuType.i2f 193 csBundle(0).ctrl.rfWen := false.B 194 csBundle(0).ctrl.fpWen := true.B 195 csBundle(0).ctrl.vecWen := false.B 196 csBundle(0).ctrl.fpu.isAddSub := false.B 197 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 198 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 199 csBundle(0).ctrl.fpu.fromInt := true.B 200 csBundle(0).ctrl.fpu.wflags := false.B 201 csBundle(0).ctrl.fpu.fpWen := true.B 202 csBundle(0).ctrl.fpu.div := false.B 203 csBundle(0).ctrl.fpu.sqrt := false.B 204 csBundle(0).ctrl.fpu.fcvt := false.B 205 /* 206 vfmv.s.f 207 */ 208 csBundle(1).ctrl.srcType(0) := SrcType.fp 209 csBundle(1).ctrl.srcType(1) := SrcType.vp 210 csBundle(1).ctrl.srcType(2) := SrcType.vp 211 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 212 csBundle(1).ctrl.lsrc(1) := 0.U 213 csBundle(1).ctrl.lsrc(2) := dest 214 csBundle(1).ctrl.ldest := dest 215 csBundle(1).ctrl.fuType := FuType.vppu 216 csBundle(1).ctrl.fuOpType := VpermType.vfmv_s_f 217 csBundle(1).ctrl.rfWen := false.B 218 csBundle(1).ctrl.fpWen := false.B 219 csBundle(1).ctrl.vecWen := true.B 220 } 221 is(UopDivType.VEC_VXV) { 222 /* 223 FMV.D.X 224 */ 225 csBundle(0).ctrl.srcType(0) := SrcType.reg 226 csBundle(0).ctrl.srcType(1) := SrcType.imm 227 csBundle(0).ctrl.lsrc(1) := 0.U 228 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 229 csBundle(0).ctrl.fuType := FuType.i2f 230 csBundle(0).ctrl.rfWen := false.B 231 csBundle(0).ctrl.fpWen := true.B 232 csBundle(0).ctrl.vecWen := false.B 233 csBundle(0).ctrl.fpu.isAddSub := false.B 234 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 235 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 236 csBundle(0).ctrl.fpu.fromInt := true.B 237 csBundle(0).ctrl.fpu.wflags := false.B 238 csBundle(0).ctrl.fpu.fpWen := true.B 239 csBundle(0).ctrl.fpu.div := false.B 240 csBundle(0).ctrl.fpu.sqrt := false.B 241 csBundle(0).ctrl.fpu.fcvt := false.B 242 /* 243 LMUL 244 */ 245 for (i <- 0 until MAX_VLMUL) { 246 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 247 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 248 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 249 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 250 csBundle(i + 1).ctrl.ldest := dest + i.U 251 csBundle(i + 1).ctrl.uopIdx := i.U 252 } 253 } 254 is(UopDivType.VEC_VVW) { 255 for (i <- 0 until MAX_VLMUL / 2) { 256 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 257 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 258 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 259 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 260 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 261 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 262 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 263 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 264 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 265 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 266 } 267 } 268 is(UopDivType.VEC_WVW) { 269 for (i <- 0 until MAX_VLMUL / 2) { 270 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 271 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 272 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 273 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 274 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 275 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 276 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 277 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 278 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 279 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 280 } 281 } 282 is(UopDivType.VEC_VXW) { 283 /* 284 FMV.D.X 285 */ 286 csBundle(0).ctrl.srcType(0) := SrcType.reg 287 csBundle(0).ctrl.srcType(1) := SrcType.imm 288 csBundle(0).ctrl.lsrc(1) := 0.U 289 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 290 csBundle(0).ctrl.fuType := FuType.i2f 291 csBundle(0).ctrl.rfWen := false.B 292 csBundle(0).ctrl.fpWen := true.B 293 csBundle(0).ctrl.vecWen := false.B 294 csBundle(0).ctrl.fpu.isAddSub := false.B 295 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 296 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 297 csBundle(0).ctrl.fpu.fromInt := true.B 298 csBundle(0).ctrl.fpu.wflags := false.B 299 csBundle(0).ctrl.fpu.fpWen := true.B 300 csBundle(0).ctrl.fpu.div := false.B 301 csBundle(0).ctrl.fpu.sqrt := false.B 302 csBundle(0).ctrl.fpu.fcvt := false.B 303 304 for (i <- 0 until MAX_VLMUL / 2) { 305 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 306 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 307 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 308 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 309 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 310 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 311 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 312 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 313 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U 314 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 315 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 316 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 317 } 318 } 319 is(UopDivType.VEC_WXW) { 320 /* 321 FMV.D.X 322 */ 323 csBundle(0).ctrl.srcType(0) := SrcType.reg 324 csBundle(0).ctrl.srcType(1) := SrcType.imm 325 csBundle(0).ctrl.lsrc(1) := 0.U 326 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 327 csBundle(0).ctrl.fuType := FuType.i2f 328 csBundle(0).ctrl.rfWen := false.B 329 csBundle(0).ctrl.fpWen := true.B 330 csBundle(0).ctrl.vecWen := false.B 331 csBundle(0).ctrl.fpu.isAddSub := false.B 332 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 333 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 334 csBundle(0).ctrl.fpu.fromInt := true.B 335 csBundle(0).ctrl.fpu.wflags := false.B 336 csBundle(0).ctrl.fpu.fpWen := true.B 337 csBundle(0).ctrl.fpu.div := false.B 338 csBundle(0).ctrl.fpu.sqrt := false.B 339 csBundle(0).ctrl.fpu.fcvt := false.B 340 341 for (i <- 0 until MAX_VLMUL / 2) { 342 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 343 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 344 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 345 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 346 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 347 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 348 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 349 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 350 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 351 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 352 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 353 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 354 } 355 } 356 is(UopDivType.VEC_WVV) { 357 for (i <- 0 until MAX_VLMUL / 2) { 358 359 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 360 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 361 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 362 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 363 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 364 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 365 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 366 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 367 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 368 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 369 } 370 } 371 is(UopDivType.VEC_WXV) { 372 /* 373 FMV.D.X 374 */ 375 csBundle(0).ctrl.srcType(0) := SrcType.reg 376 csBundle(0).ctrl.srcType(1) := SrcType.imm 377 csBundle(0).ctrl.lsrc(1) := 0.U 378 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 379 csBundle(0).ctrl.fuType := FuType.i2f 380 csBundle(0).ctrl.rfWen := false.B 381 csBundle(0).ctrl.fpWen := true.B 382 csBundle(0).ctrl.vecWen := false.B 383 csBundle(0).ctrl.fpu.isAddSub := false.B 384 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 385 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 386 csBundle(0).ctrl.fpu.fromInt := true.B 387 csBundle(0).ctrl.fpu.wflags := false.B 388 csBundle(0).ctrl.fpu.fpWen := true.B 389 csBundle(0).ctrl.fpu.div := false.B 390 csBundle(0).ctrl.fpu.sqrt := false.B 391 csBundle(0).ctrl.fpu.fcvt := false.B 392 393 for (i <- 0 until MAX_VLMUL / 2) { 394 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 395 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 396 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 397 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 398 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 399 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 400 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 401 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 402 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 403 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 404 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 405 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 406 } 407 } 408 is(UopDivType.VEC_VVM) { 409 csBundle(0).ctrl.lsrc(2) := dest 410 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 411 csBundle(0).ctrl.uopIdx := 0.U 412 for(i <- 1 until MAX_VLMUL) { 413 csBundle(i).ctrl.lsrc(0) := src1 + i.U 414 csBundle(i).ctrl.lsrc(1) := src2 + i.U 415 csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 416 csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 417 csBundle(i).ctrl.uopIdx := i.U 418 } 419 csBundle(numOfUop - 1.U).ctrl.ldest := dest 420 } 421 is(UopDivType.VEC_VXM) { 422 /* 423 FMV.D.X 424 */ 425 csBundle(0).ctrl.srcType(0) := SrcType.reg 426 csBundle(0).ctrl.srcType(1) := SrcType.imm 427 csBundle(0).ctrl.lsrc(1) := 0.U 428 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 429 csBundle(0).ctrl.fuType := FuType.i2f 430 csBundle(0).ctrl.rfWen := false.B 431 csBundle(0).ctrl.fpWen := true.B 432 csBundle(0).ctrl.vecWen := false.B 433 csBundle(0).ctrl.fpu.isAddSub := false.B 434 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 435 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 436 csBundle(0).ctrl.fpu.fromInt := true.B 437 csBundle(0).ctrl.fpu.wflags := false.B 438 csBundle(0).ctrl.fpu.fpWen := true.B 439 csBundle(0).ctrl.fpu.div := false.B 440 csBundle(0).ctrl.fpu.sqrt := false.B 441 csBundle(0).ctrl.fpu.fcvt := false.B 442 //LMUL 443 csBundle(1).ctrl.srcType(0) := SrcType.fp 444 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 445 csBundle(1).ctrl.lsrc(2) := dest 446 csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 447 csBundle(1).ctrl.uopIdx := 0.U 448 for (i <- 1 until MAX_VLMUL) { 449 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 450 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 451 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 452 csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 453 csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 454 csBundle(i + 1).ctrl.uopIdx := i.U 455 } 456 csBundle(numOfUop - 1.U).ctrl.ldest := dest 457 } 458 is(UopDivType.VEC_SLIDE1UP) { 459 /* 460 FMV.D.X 461 */ 462 csBundle(0).ctrl.srcType(0) := SrcType.reg 463 csBundle(0).ctrl.srcType(1) := SrcType.imm 464 csBundle(0).ctrl.lsrc(1) := 0.U 465 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 466 csBundle(0).ctrl.fuType := FuType.i2f 467 csBundle(0).ctrl.rfWen := false.B 468 csBundle(0).ctrl.fpWen := true.B 469 csBundle(0).ctrl.vecWen := false.B 470 csBundle(0).ctrl.fpu.isAddSub := false.B 471 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 472 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 473 csBundle(0).ctrl.fpu.fromInt := true.B 474 csBundle(0).ctrl.fpu.wflags := false.B 475 csBundle(0).ctrl.fpu.fpWen := true.B 476 csBundle(0).ctrl.fpu.div := false.B 477 csBundle(0).ctrl.fpu.sqrt := false.B 478 csBundle(0).ctrl.fpu.fcvt := false.B 479 //LMUL 480 csBundle(1).ctrl.srcType(0) := SrcType.fp 481 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 482 csBundle(1).ctrl.lsrc(2) := dest 483 csBundle(1).ctrl.ldest := dest 484 csBundle(1).ctrl.uopIdx := 0.U 485 for (i <- 1 until MAX_VLMUL) { 486 csBundle(i + 1).ctrl.srcType(0) := SrcType.vp 487 csBundle(i + 1).ctrl.lsrc(0) := src2 + (i - 1).U 488 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 489 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 490 csBundle(i + 1).ctrl.ldest := dest + i.U 491 csBundle(i + 1).ctrl.uopIdx := i.U 492 } 493 } 494 is(UopDivType.VEC_FSLIDE1UP) { 495 //LMUL 496 csBundle(0).ctrl.srcType(0) := SrcType.fp 497 csBundle(0).ctrl.lsrc(0) := src1 498 csBundle(0).ctrl.lsrc(1) := src2 499 csBundle(0).ctrl.lsrc(2) := dest 500 csBundle(0).ctrl.ldest := dest 501 csBundle(0).ctrl.uopIdx := 0.U 502 for (i <- 1 until MAX_VLMUL) { 503 csBundle(i).ctrl.srcType(0) := SrcType.vp 504 csBundle(i).ctrl.lsrc(0) := src2 + (i - 1).U 505 csBundle(i).ctrl.lsrc(1) := src2 + i.U 506 csBundle(i).ctrl.lsrc(2) := dest + i.U 507 csBundle(i).ctrl.ldest := dest + i.U 508 csBundle(i).ctrl.uopIdx := i.U 509 } 510 } 511 is(UopDivType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 512 /* 513 FMV.D.X 514 */ 515 csBundle(0).ctrl.srcType(0) := SrcType.reg 516 csBundle(0).ctrl.srcType(1) := SrcType.imm 517 csBundle(0).ctrl.lsrc(1) := 0.U 518 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 519 csBundle(0).ctrl.fuType := FuType.i2f 520 csBundle(0).ctrl.rfWen := false.B 521 csBundle(0).ctrl.fpWen := true.B 522 csBundle(0).ctrl.vecWen := false.B 523 csBundle(0).ctrl.fpu.isAddSub := false.B 524 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 525 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 526 csBundle(0).ctrl.fpu.fromInt := true.B 527 csBundle(0).ctrl.fpu.wflags := false.B 528 csBundle(0).ctrl.fpu.fpWen := true.B 529 csBundle(0).ctrl.fpu.div := false.B 530 csBundle(0).ctrl.fpu.sqrt := false.B 531 csBundle(0).ctrl.fpu.fcvt := false.B 532 //LMUL 533 for (i <- 0 until MAX_VLMUL) { 534 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp 535 csBundle(2 * i + 1).ctrl.srcType(1) := SrcType.vp 536 csBundle(2 * i + 1).ctrl.lsrc(0) := src2 + (i+1).U 537 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 538 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 539 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 540 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 541 if (2 * i + 2 < MAX_VLMUL * 2 ){ 542 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 543 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 544 // csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U // DontCare 545 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 546 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 547 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 548 } 549 } 550 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 551 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := FP_TMP_REG_MV.U 552 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 553 } 554 is(UopDivType.VEC_FSLIDE1DOWN) { 555 //LMUL 556 for (i <- 0 until MAX_VLMUL) { 557 csBundle(2 * i).ctrl.srcType(0) := SrcType.vp 558 csBundle(2 * i).ctrl.srcType(1) := SrcType.vp 559 csBundle(2 * i).ctrl.lsrc(0) := src2 + (i+1).U 560 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 561 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 562 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 563 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 564 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 565 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 566 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 567 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 568 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 569 } 570 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 571 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1 572 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 573 } 574 } 575 576 //uops dispatch 577 val normal :: ext :: Nil = Enum(2) 578 val stateReg = RegInit(normal) 579 val uopRes = RegInit(0.U) 580 581 //readyFromRename Counter 582 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 583 584 switch(stateReg) { 585 is(normal) { 586 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 587 } 588 is(ext) { 589 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 590 } 591 } 592 593 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 594 val uopResJudge = Mux(stateReg === normal, 595 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 596 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 597 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 598 599 for(i <- 0 until RenameWidth) { 600 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 601 (stateReg === normal) -> csBundle(i), 602 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 603 )) 604 } 605 606 607 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 608 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 609 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 610 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 611 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 612 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 613 notInfVec(0) := true.B 614 615 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 616 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 617 1.U) 618 validToRename.zipWithIndex.foreach{ 619 case(dst, i) => 620 dst := MuxCase(false.B, Seq( 621 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 622 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 623 )) 624 } 625 626 readyToIBuf.zipWithIndex.foreach { 627 case (dst, i) => 628 dst := MuxCase(true.B, Seq( 629 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 630 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 631 )) 632 } 633 634 io.deq.cf_ctrl := cf_ctrl 635 io.deq.isVset := isVset_u 636 io.deq.complexNum := complexNum 637 io.deq.validToRename := validToRename 638 io.deq.readyToIBuf := readyToIBuf 639 640} 641 642