1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VppuType 31import scala.collection.Seq 32 33trait VectorConstants { 34 val MAX_VLMUL = 8 35 val XP_TMP_REG_VCONFIG = 32 36 val FP_TMP_REG_MV = 32 37 val VECTOR_TMP_REG_LMUL = 32 38} 39 40class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 41 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 42 val vconfig = Input(new VConfig) 43 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 44 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 45 val readyFromRename = Input(Vec(RenameWidth, Bool())) 46 val deq = new Bundle { 47 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 48 val isVset = Output(Bool()) 49 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 50 val validToRename = Output(Vec(RenameWidth, Bool())) 51 val complexNum = Output(UInt(3.W)) 52 } 53 val csrCtrl = Input(new CustomCSRCtrlIO) 54} 55 56class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 57 val io = IO(new DecodeUnitCompIO) 58 //input bits 59 val ctrl_flow = Wire(new CtrlFlow) 60 ctrl_flow := io.enq.ctrl_flow 61 //output bits 62 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 63 val validToRename = Wire(Vec(RenameWidth, Bool())) 64 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 65 val complexNum = Wire(UInt(3.W)) 66 67 //output of DecodeUnit 68 val cf_ctrl_u = Wire(new CfCtrl) 69 val isVset_u = Wire(Bool()) 70 71 //pre decode 72 val simple = Module(new DecodeUnit) 73 simple.io.enq.ctrl_flow := ctrl_flow 74 simple.io.vconfig := io.vconfig 75 simple.io.csrCtrl := io.csrCtrl 76 cf_ctrl_u := simple.io.deq.cf_ctrl 77 isVset_u := simple.io.deq.isVset 78 79 //Type of uop Div 80 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 81 82 //LMUL 83 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U, Array( 84 "b001".U -> 2.U, 85 "b010".U -> 4.U, 86 "b011".U -> 8.U 87 )) 88 //number of uop 89 val numOfUop = MuxLookup(typeOfDiv, 1.U, Array( 90 UopDivType.VEC_0XV -> 2.U, 91 UopDivType.DIR -> 2.U, 92 UopDivType.VEC_VVV -> lmul, 93 UopDivType.VEC_EXT2 -> lmul, 94 UopDivType.VEC_EXT4 -> lmul, 95 UopDivType.VEC_EXT8 -> lmul, 96 UopDivType.VEC_VVM -> lmul, 97 UopDivType.VEC_VXM -> (lmul + 1.U), 98 UopDivType.VEC_VXV -> (lmul + 1.U), 99 UopDivType.VEC_VVW -> (lmul + lmul), // lmul <= 4 100 UopDivType.VEC_WVW -> (lmul + lmul), // lmul <= 4 101 UopDivType.VEC_VXW -> (lmul + lmul + 1.U), // lmul <= 4 102 UopDivType.VEC_WXW -> (lmul + lmul + 1.U), // lmul <= 4 103 UopDivType.VEC_WVV -> (lmul + lmul), // lmul <= 4 104 UopDivType.VEC_WXV -> (lmul + lmul + 1.U) // lmul <= 4 105 )) 106 107 val src1 = ctrl_flow.instr(19, 15) 108 val src2 = ctrl_flow.instr(24, 20) 109 val dest = ctrl_flow.instr(11, 7) 110 111 //uop div up to maxNumOfUop 112 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 113 csBundle.map { case dst => 114 dst := cf_ctrl_u 115 dst.ctrl.firstUop := false.B 116 dst.ctrl.lastUop := false.B 117 } 118 119 csBundle(0).ctrl.firstUop := true.B 120 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 121 122 switch(typeOfDiv) { 123 is(UopDivType.DIR) { 124 when(isVset_u) { 125 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR 126 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 127 csBundle(1).ctrl.ldest := XP_TMP_REG_VCONFIG.U 128 csBundle(1).ctrl.flushPipe := false.B 129 } 130 } 131 is(UopDivType.VEC_VVV) { 132 for (i <- 0 until MAX_VLMUL) { 133 csBundle(i).ctrl.lsrc(0) := src1 + i.U 134 csBundle(i).ctrl.lsrc(1) := src2 + i.U 135 csBundle(i).ctrl.ldest := dest + i.U 136 csBundle(i).ctrl.uopIdx := i.U 137 } 138 } 139 is(UopDivType.VEC_EXT2) { 140 for (i <- 0 until MAX_VLMUL / 2) { 141 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 142 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 143 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 144 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 145 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 146 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 147 } 148 } 149 is(UopDivType.VEC_EXT4) { 150 for (i <- 0 until MAX_VLMUL / 4) { 151 csBundle(4 * i).ctrl.lsrc(1) := src2 + i.U 152 csBundle(4 * i).ctrl.ldest := dest + (4 * i).U 153 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 154 csBundle(4 * i + 1).ctrl.lsrc(1) := src2 + i.U 155 csBundle(4 * i + 1).ctrl.ldest := dest + (4 * i + 1).U 156 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 157 csBundle(4 * i + 2).ctrl.lsrc(1) := src2 + i.U 158 csBundle(4 * i + 2).ctrl.ldest := dest + (4 * i + 2).U 159 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 160 csBundle(4 * i + 3).ctrl.lsrc(1) := src2 + i.U 161 csBundle(4 * i + 3).ctrl.ldest := dest + (4 * i + 3).U 162 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 163 } 164 } 165 is(UopDivType.VEC_EXT8) { 166 for (i <- 0 until MAX_VLMUL) { 167 csBundle(i).ctrl.lsrc(1) := src2 168 csBundle(i).ctrl.ldest := dest + i.U 169 csBundle(i).ctrl.uopIdx := i.U 170 } 171 } 172 is(UopDivType.VEC_0XV) { 173 /* 174 FMV.D.X 175 */ 176 csBundle(0).ctrl.srcType(0) := SrcType.reg 177 csBundle(0).ctrl.srcType(1) := SrcType.imm 178 csBundle(0).ctrl.lsrc(1) := 0.U 179 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 180 csBundle(0).ctrl.fuType := FuType.i2f 181 csBundle(0).ctrl.rfWen := false.B 182 csBundle(0).ctrl.fpWen := true.B 183 csBundle(0).ctrl.vecWen := false.B 184 csBundle(0).ctrl.fpu.isAddSub := false.B 185 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 186 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 187 csBundle(0).ctrl.fpu.fromInt := true.B 188 csBundle(0).ctrl.fpu.wflags := false.B 189 csBundle(0).ctrl.fpu.fpWen := true.B 190 csBundle(0).ctrl.fpu.div := false.B 191 csBundle(0).ctrl.fpu.sqrt := false.B 192 csBundle(0).ctrl.fpu.fcvt := false.B 193 /* 194 vfmv.s.f 195 */ 196 csBundle(1).ctrl.srcType(0) := SrcType.fp 197 csBundle(1).ctrl.srcType(1) := SrcType.vp 198 csBundle(1).ctrl.srcType(2) := SrcType.vp 199 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 200 csBundle(1).ctrl.lsrc(1) := 0.U 201 csBundle(1).ctrl.lsrc(2) := dest 202 csBundle(1).ctrl.ldest := dest 203 csBundle(1).ctrl.fuType := FuType.vppu 204 csBundle(1).ctrl.fuOpType := VppuType.f2s 205 csBundle(1).ctrl.rfWen := false.B 206 csBundle(1).ctrl.fpWen := false.B 207 csBundle(1).ctrl.vecWen := true.B 208 } 209 is(UopDivType.VEC_VXV) { 210 /* 211 FMV.D.X 212 */ 213 csBundle(0).ctrl.srcType(0) := SrcType.reg 214 csBundle(0).ctrl.srcType(1) := SrcType.imm 215 csBundle(0).ctrl.lsrc(1) := 0.U 216 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 217 csBundle(0).ctrl.fuType := FuType.i2f 218 csBundle(0).ctrl.rfWen := false.B 219 csBundle(0).ctrl.fpWen := true.B 220 csBundle(0).ctrl.vecWen := false.B 221 csBundle(0).ctrl.fpu.isAddSub := false.B 222 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 223 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 224 csBundle(0).ctrl.fpu.fromInt := true.B 225 csBundle(0).ctrl.fpu.wflags := false.B 226 csBundle(0).ctrl.fpu.fpWen := true.B 227 csBundle(0).ctrl.fpu.div := false.B 228 csBundle(0).ctrl.fpu.sqrt := false.B 229 csBundle(0).ctrl.fpu.fcvt := false.B 230 /* 231 LMUL 232 */ 233 for (i <- 0 until MAX_VLMUL) { 234 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 235 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 236 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 237 csBundle(i + 1).ctrl.ldest := dest + i.U 238 csBundle(i + 1).ctrl.uopIdx := i.U 239 } 240 } 241 is(UopDivType.VEC_VVW) { 242 for (i <- 0 until MAX_VLMUL / 2) { 243 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 244 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 245 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 246 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 247 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 248 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 249 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 250 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 251 } 252 } 253 is(UopDivType.VEC_WVW) { 254 for (i <- 0 until MAX_VLMUL / 2) { 255 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 256 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 257 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 258 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 259 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 260 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 261 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 262 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 263 } 264 } 265 is(UopDivType.VEC_VXW) { 266 /* 267 FMV.D.X 268 */ 269 csBundle(0).ctrl.srcType(0) := SrcType.reg 270 csBundle(0).ctrl.srcType(1) := SrcType.imm 271 csBundle(0).ctrl.lsrc(1) := 0.U 272 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 273 csBundle(0).ctrl.fuType := FuType.i2f 274 csBundle(0).ctrl.rfWen := false.B 275 csBundle(0).ctrl.fpWen := true.B 276 csBundle(0).ctrl.vecWen := false.B 277 csBundle(0).ctrl.fpu.isAddSub := false.B 278 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 279 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 280 csBundle(0).ctrl.fpu.fromInt := true.B 281 csBundle(0).ctrl.fpu.wflags := false.B 282 csBundle(0).ctrl.fpu.fpWen := true.B 283 csBundle(0).ctrl.fpu.div := false.B 284 csBundle(0).ctrl.fpu.sqrt := false.B 285 csBundle(0).ctrl.fpu.fcvt := false.B 286 287 for (i <- 0 until MAX_VLMUL / 2) { 288 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 289 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 290 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 291 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 292 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 293 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 294 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 295 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U 296 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 297 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 298 } 299 } 300 is(UopDivType.VEC_WXW) { 301 /* 302 FMV.D.X 303 */ 304 csBundle(0).ctrl.srcType(0) := SrcType.reg 305 csBundle(0).ctrl.srcType(1) := SrcType.imm 306 csBundle(0).ctrl.lsrc(1) := 0.U 307 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 308 csBundle(0).ctrl.fuType := FuType.i2f 309 csBundle(0).ctrl.rfWen := false.B 310 csBundle(0).ctrl.fpWen := true.B 311 csBundle(0).ctrl.vecWen := false.B 312 csBundle(0).ctrl.fpu.isAddSub := false.B 313 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 314 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 315 csBundle(0).ctrl.fpu.fromInt := true.B 316 csBundle(0).ctrl.fpu.wflags := false.B 317 csBundle(0).ctrl.fpu.fpWen := true.B 318 csBundle(0).ctrl.fpu.div := false.B 319 csBundle(0).ctrl.fpu.sqrt := false.B 320 csBundle(0).ctrl.fpu.fcvt := false.B 321 322 for (i <- 0 until MAX_VLMUL / 2) { 323 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 324 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 325 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 326 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 327 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 328 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 329 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 330 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 331 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 332 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 333 } 334 } 335 is(UopDivType.VEC_WVV) { 336 for (i <- 0 until MAX_VLMUL / 2) { 337 338 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 339 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 340 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 341 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 342 csBundle(2 * i + 1).ctrl.srcType(2) := SrcType.vp 343 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 344 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 345 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 346 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 347 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 348 } 349 } 350 is(UopDivType.VEC_WXV) { 351 /* 352 FMV.D.X 353 */ 354 csBundle(0).ctrl.srcType(0) := SrcType.reg 355 csBundle(0).ctrl.srcType(1) := SrcType.imm 356 csBundle(0).ctrl.lsrc(1) := 0.U 357 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 358 csBundle(0).ctrl.fuType := FuType.i2f 359 csBundle(0).ctrl.rfWen := false.B 360 csBundle(0).ctrl.fpWen := true.B 361 csBundle(0).ctrl.vecWen := false.B 362 csBundle(0).ctrl.fpu.isAddSub := false.B 363 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 364 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 365 csBundle(0).ctrl.fpu.fromInt := true.B 366 csBundle(0).ctrl.fpu.wflags := false.B 367 csBundle(0).ctrl.fpu.fpWen := true.B 368 csBundle(0).ctrl.fpu.div := false.B 369 csBundle(0).ctrl.fpu.sqrt := false.B 370 csBundle(0).ctrl.fpu.fcvt := false.B 371 372 for (i <- 0 until MAX_VLMUL / 2) { 373 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 374 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 375 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 376 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 377 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 378 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 379 csBundle(2 * i + 2).ctrl.srcType(2) := SrcType.vp 380 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 381 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 382 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 383 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 384 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 385 } 386 } 387 is(UopDivType.VEC_VVM) { 388 csBundle(0).ctrl.srcType(2) := SrcType.vp 389 csBundle(0).ctrl.lsrc(2) := dest 390 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 391 csBundle(0).ctrl.uopIdx := 0.U 392 for(i <- 1 until MAX_VLMUL) { 393 csBundle(i).ctrl.srcType(2) := SrcType.vp 394 csBundle(i).ctrl.lsrc(0) := src1 + i.U 395 csBundle(i).ctrl.lsrc(1) := src2 + i.U 396 csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 397 csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 398 csBundle(i).ctrl.uopIdx := i.U 399 } 400 csBundle(numOfUop - 1.U).ctrl.ldest := dest 401 } 402 is(UopDivType.VEC_VXM) { 403 /* 404 FMV.D.X 405 */ 406 csBundle(0).ctrl.srcType(0) := SrcType.reg 407 csBundle(0).ctrl.srcType(1) := SrcType.imm 408 csBundle(0).ctrl.lsrc(1) := 0.U 409 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 410 csBundle(0).ctrl.fuType := FuType.i2f 411 csBundle(0).ctrl.rfWen := false.B 412 csBundle(0).ctrl.fpWen := true.B 413 csBundle(0).ctrl.vecWen := false.B 414 csBundle(0).ctrl.fpu.isAddSub := false.B 415 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 416 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 417 csBundle(0).ctrl.fpu.fromInt := true.B 418 csBundle(0).ctrl.fpu.wflags := false.B 419 csBundle(0).ctrl.fpu.fpWen := true.B 420 csBundle(0).ctrl.fpu.div := false.B 421 csBundle(0).ctrl.fpu.sqrt := false.B 422 csBundle(0).ctrl.fpu.fcvt := false.B 423 //LMUL 424 csBundle(1).ctrl.srcType(0) := SrcType.fp 425 csBundle(1).ctrl.srcType(2) := SrcType.vp 426 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 427 csBundle(1).ctrl.lsrc(2) := dest 428 csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 429 csBundle(1).ctrl.uopIdx := 0.U 430 for (i <- 1 until MAX_VLMUL) { 431 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 432 csBundle(i + 1).ctrl.srcType(2) := SrcType.vp 433 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 434 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 435 csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 436 csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 437 csBundle(i + 1).ctrl.uopIdx := i.U 438 } 439 csBundle(numOfUop - 1.U).ctrl.ldest := dest 440 } 441 } 442 443 //uops dispatch 444 val normal :: ext :: Nil = Enum(2) 445 val stateReg = RegInit(normal) 446 val uopRes = RegInit(0.U) 447 448 //readyFromRename Counter 449 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 450 451 switch(stateReg) { 452 is(normal) { 453 when(!io.validFromIBuf(0)) { 454 stateReg := normal 455 uopRes := 0.U 456 }.elsewhen((numOfUop > readyCounter) && (readyCounter =/= 0.U)){ 457 stateReg := ext 458 uopRes := numOfUop - readyCounter 459 }.otherwise { 460 stateReg := normal 461 uopRes := 0.U 462 } 463 } 464 is(ext) { 465 when(!io.validFromIBuf(0)) { 466 stateReg := normal 467 uopRes := 0.U 468 }.elsewhen(uopRes > readyCounter) { 469 stateReg := ext 470 uopRes := uopRes - readyCounter 471 }.otherwise { 472 stateReg := normal 473 uopRes := 0.U 474 } 475 } 476 } 477 478 for(i <- 0 until RenameWidth) { 479 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 480 (stateReg === normal) -> csBundle(i), 481 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 482 )) 483 } 484 485 486 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 487 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 488 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 489 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 490 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 491 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 492 notInfVec(0) := true.B 493 494 complexNum := 1.U 495 validToRename.map{ case dst => dst := false.B } 496 readyToIBuf .map{ case dst => dst := false.B } 497 switch(stateReg) { 498 is(normal) { 499 when(!io.validFromIBuf(0)) { 500 complexNum := 1.U 501 validToRename(0) := false.B 502 for (i <- 1 until RenameWidth) { 503 validToRename(i) := notInfVec(i - 1) && validSimple(i - 1) 504 } 505 readyToIBuf(0) := io.readyFromRename(0) 506 for(i <- 1 until DecodeWidth) { 507 readyToIBuf(i) := notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i) 508 } 509 }.elsewhen(numOfUop > readyCounter) { 510 complexNum := Mux(readyCounter === 0.U, 1.U, readyCounter) 511 for (i <- 0 until RenameWidth) { 512 validToRename(i) := Mux(readyCounter > i.U, true.B, false.B) 513 } 514 readyToIBuf.map{ case dst => dst := false.B } 515 }.otherwise { 516 complexNum := numOfUop 517 for (i <- 0 until RenameWidth) { 518 validToRename(i) := Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)) 519 } 520 readyToIBuf(0) := true.B 521 for (i <- 1 until DecodeWidth) { 522 readyToIBuf(i) := Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B) 523 } 524 } 525 } 526 is(ext) { 527 when(!io.validFromIBuf(0)) { 528 complexNum := 1.U 529 validToRename.map{ case dst => dst := false.B } 530 readyToIBuf.map{ case dst => dst := true.B } 531 }.elsewhen(uopRes > readyCounter) { 532 complexNum := Mux(readyCounter === 0.U, 1.U, readyCounter) 533 for (i <- 0 until RenameWidth) { 534 validToRename(i) := Mux(readyCounter > i.U, true.B, false.B) 535 } 536 readyToIBuf.map{ case dst => dst := false.B } 537 }.otherwise { 538 complexNum := uopRes 539 for (i <- 0 until RenameWidth) { 540 validToRename(i) := Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)) 541 } 542 readyToIBuf(0) := true.B 543 for (i <- 1 until DecodeWidth) { 544 readyToIBuf(i) := Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B) 545 } 546 } 547 } 548 } 549 550 io.deq.cf_ctrl := cf_ctrl 551 io.deq.isVset := isVset_u 552 io.deq.complexNum := complexNum 553 io.deq.validToRename := validToRename 554 io.deq.readyToIBuf := readyToIBuf 555 556} 557 558