1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.VType 34import yunsuan.VpermType 35 36import scala.collection.Seq 37 38trait VectorConstants { 39 val MAX_VLMUL = 8 40 val FP_TMP_REG_MV = 32 41 val VECTOR_TMP_REG_LMUL = 33 // 33~47 -> 15 42} 43 44class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 45 val enq = new Bundle { val staticInst = Input(new StaticInst) } 46 val vtype = Input(new VType) 47 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 48 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 49 val readyFromRename = Input(Vec(RenameWidth, Bool())) 50 val deq = new Bundle { 51 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 52 val isVset = Output(Bool()) 53 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 54 val validToRename = Output(Vec(RenameWidth, Bool())) 55 val complexNum = Output(UInt(3.W)) 56 } 57 val csrCtrl = Input(new CustomCSRCtrlIO) 58} 59 60/** 61 * @author zly 62 */ 63class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 64 val io = IO(new DecodeUnitCompIO) 65 66 val maxUopSize = MaxUopSize 67 //input bits 68 val staticInst = Wire(new StaticInst) 69 70 71 staticInst := io.enq.staticInst 72 private val inst: XSInstBitFields = staticInst.instr.asTypeOf(new XSInstBitFields) 73 74 val src1 = Cat(0.U(1.W), inst.RS1) 75 val src2 = Cat(0.U(1.W), inst.RS2) 76 val dest = Cat(0.U(1.W), inst.RD) 77 78 79 //output bits 80 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 81 val validToRename = Wire(Vec(RenameWidth, Bool())) 82 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 83 val complexNum = Wire(UInt(3.W)) 84 85 //output of DecodeUnit 86 val decodedInstsSimple = Wire(new DecodedInst) 87 val numOfUop = Wire(UInt(log2Up(maxUopSize+1).W)) 88 val lmul = Wire(UInt(4.W)) 89 val isVsetSimple = Wire(Bool()) 90 91 //pre decode 92 val simple = Module(new DecodeUnit) 93 simple.io.enq.ctrlFlow := staticInst 94 simple.io.enq.vtype := io.vtype 95 simple.io.csrCtrl := io.csrCtrl 96 decodedInstsSimple := simple.io.deq.decodedInst 97 lmul := simple.io.deq.uopInfo.lmul 98 isVsetSimple := simple.io.deq.decodedInst.isVset 99 when(isVsetSimple) { 100 when(dest === 0.U && src1 === 0.U) { 101 decodedInstsSimple.fuOpType := VSETOpType.keepVl(simple.io.deq.decodedInst.fuOpType) 102 }.elsewhen(src1 === 0.U) { 103 decodedInstsSimple.fuOpType := VSETOpType.setVlmax(simple.io.deq.decodedInst.fuOpType) 104 } 105 when(io.vtype.illegal){ 106 decodedInstsSimple.flushPipe := true.B 107 } 108 } 109 //Type of uop Div 110 val typeOfSplit = decodedInstsSimple.uopSplitType 111 112 when(typeOfSplit === UopSplitType.DIR) { 113 numOfUop := Mux(dest =/= 0.U, 2.U, 114 Mux(src1 =/= 0.U, 1.U, 115 Mux(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType), 2.U, 1.U))) 116 } .otherwise { 117 numOfUop := simple.io.deq.uopInfo.numOfUop 118 } 119 120 121 //uop div up to maxUopSize 122 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 123 csBundle.map { case dst => 124 dst := decodedInstsSimple 125 dst.firstUop := false.B 126 dst.lastUop := false.B 127 } 128 129 csBundle(0).numUops := numOfUop 130 csBundle(0).firstUop := true.B 131 csBundle(numOfUop - 1.U).lastUop := true.B 132 133 switch(typeOfSplit) { 134 is(UopSplitType.DIR) { 135 when(isVsetSimple) { 136 when(dest =/= 0.U) { 137 csBundle(0).fuType := FuType.vsetiwi.U 138 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInstsSimple.fuOpType) 139 csBundle(0).flushPipe := false.B 140 csBundle(0).rfWen := true.B 141 csBundle(0).vecWen := false.B 142 csBundle(1).ldest := VCONFIG_IDX.U 143 csBundle(1).rfWen := false.B 144 csBundle(1).vecWen := true.B 145 }.elsewhen(src1 =/= 0.U) { 146 csBundle(0).ldest := VCONFIG_IDX.U 147 }.elsewhen(VSETOpType.isVsetvli(decodedInstsSimple.fuOpType)) { 148 csBundle(0).fuType := FuType.vsetfwf.U 149 csBundle(0).srcType(0) := SrcType.vp 150 csBundle(0).lsrc(0) := VCONFIG_IDX.U 151 }.elsewhen(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType)) { 152 csBundle(0).srcType(0) := SrcType.reg 153 csBundle(0).srcType(1) := SrcType.imm 154 csBundle(0).lsrc(1) := 0.U 155 csBundle(0).ldest := FP_TMP_REG_MV.U 156 csBundle(0).fuType := FuType.i2f.U 157 csBundle(0).rfWen := false.B 158 csBundle(0).fpWen := true.B 159 csBundle(0).vecWen := false.B 160 csBundle(0).fpu.isAddSub := false.B 161 csBundle(0).fpu.typeTagIn := FPU.D 162 csBundle(0).fpu.typeTagOut := FPU.D 163 csBundle(0).fpu.fromInt := true.B 164 csBundle(0).fpu.wflags := false.B 165 csBundle(0).fpu.fpWen := true.B 166 csBundle(0).fpu.div := false.B 167 csBundle(0).fpu.sqrt := false.B 168 csBundle(0).fpu.fcvt := false.B 169 csBundle(0).flushPipe := false.B 170 csBundle(1).fuType := FuType.vsetfwf.U 171 csBundle(1).srcType(0) := SrcType.vp 172 csBundle(1).lsrc(0) := VCONFIG_IDX.U 173 csBundle(1).srcType(1) := SrcType.fp 174 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 175 csBundle(1).ldest := VCONFIG_IDX.U 176 } 177 } 178 } 179 is(UopSplitType.VEC_VVV) { 180 for (i <- 0 until MAX_VLMUL) { 181 csBundle(i).lsrc(0) := src1 + i.U 182 csBundle(i).lsrc(1) := src2 + i.U 183 csBundle(i).lsrc(2) := dest + i.U 184 csBundle(i).ldest := dest + i.U 185 csBundle(i).uopIdx := i.U 186 } 187 } 188 is(UopSplitType.VEC_VFV) { 189 for (i <- 0 until MAX_VLMUL) { 190 csBundle(i).lsrc(1) := src2 + i.U 191 csBundle(i).lsrc(2) := dest + i.U 192 csBundle(i).ldest := dest + i.U 193 csBundle(i).uopIdx := i.U 194 } 195 } 196 is(UopSplitType.VEC_EXT2) { 197 for (i <- 0 until MAX_VLMUL / 2) { 198 csBundle(2 * i).lsrc(1) := src2 + i.U 199 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 200 csBundle(2 * i).ldest := dest + (2 * i).U 201 csBundle(2 * i).uopIdx := (2 * i).U 202 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 203 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 204 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 205 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 206 } 207 } 208 is(UopSplitType.VEC_EXT4) { 209 for (i <- 0 until MAX_VLMUL / 4) { 210 csBundle(4 * i).lsrc(1) := src2 + i.U 211 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 212 csBundle(4 * i).ldest := dest + (4 * i).U 213 csBundle(4 * i).uopIdx := (4 * i).U 214 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 215 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 216 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 217 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 218 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 219 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 220 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 221 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 222 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 223 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 224 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 225 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 226 } 227 } 228 is(UopSplitType.VEC_EXT8) { 229 for (i <- 0 until MAX_VLMUL) { 230 csBundle(i).lsrc(1) := src2 231 csBundle(i).lsrc(2) := dest + i.U 232 csBundle(i).ldest := dest + i.U 233 csBundle(i).uopIdx := i.U 234 } 235 } 236 is(UopSplitType.VEC_0XV) { 237 /* 238 FMV.D.X 239 */ 240 csBundle(0).srcType(0) := SrcType.reg 241 csBundle(0).srcType(1) := SrcType.imm 242 csBundle(0).lsrc(1) := 0.U 243 csBundle(0).ldest := FP_TMP_REG_MV.U 244 csBundle(0).fuType := FuType.i2f.U 245 csBundle(0).rfWen := false.B 246 csBundle(0).fpWen := true.B 247 csBundle(0).vecWen := false.B 248 csBundle(0).fpu.isAddSub := false.B 249 csBundle(0).fpu.typeTagIn := FPU.D 250 csBundle(0).fpu.typeTagOut := FPU.D 251 csBundle(0).fpu.fromInt := true.B 252 csBundle(0).fpu.wflags := false.B 253 csBundle(0).fpu.fpWen := true.B 254 csBundle(0).fpu.div := false.B 255 csBundle(0).fpu.sqrt := false.B 256 csBundle(0).fpu.fcvt := false.B 257 /* 258 vfmv.s.f 259 */ 260 csBundle(1).srcType(0) := SrcType.fp 261 csBundle(1).srcType(1) := SrcType.vp 262 csBundle(1).srcType(2) := SrcType.vp 263 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 264 csBundle(1).lsrc(1) := 0.U 265 csBundle(1).lsrc(2) := dest 266 csBundle(1).ldest := dest 267 csBundle(1).fuType := FuType.vppu.U 268 csBundle(1).fuOpType := VpermType.dummy 269 csBundle(1).rfWen := false.B 270 csBundle(1).fpWen := false.B 271 csBundle(1).vecWen := true.B 272 } 273 is(UopSplitType.VEC_VXV) { 274 /* 275 FMV.D.X 276 */ 277 csBundle(0).srcType(0) := SrcType.reg 278 csBundle(0).srcType(1) := SrcType.imm 279 csBundle(0).lsrc(1) := 0.U 280 csBundle(0).ldest := FP_TMP_REG_MV.U 281 csBundle(0).fuType := FuType.i2f.U 282 csBundle(0).rfWen := false.B 283 csBundle(0).fpWen := true.B 284 csBundle(0).vecWen := false.B 285 csBundle(0).fpu.isAddSub := false.B 286 csBundle(0).fpu.typeTagIn := FPU.D 287 csBundle(0).fpu.typeTagOut := FPU.D 288 csBundle(0).fpu.fromInt := true.B 289 csBundle(0).fpu.wflags := false.B 290 csBundle(0).fpu.fpWen := true.B 291 csBundle(0).fpu.div := false.B 292 csBundle(0).fpu.sqrt := false.B 293 csBundle(0).fpu.fcvt := false.B 294 /* 295 LMUL 296 */ 297 for (i <- 0 until MAX_VLMUL) { 298 csBundle(i + 1).srcType(0) := SrcType.fp 299 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 300 csBundle(i + 1).lsrc(1) := src2 + i.U 301 csBundle(i + 1).lsrc(2) := dest + i.U 302 csBundle(i + 1).ldest := dest + i.U 303 csBundle(i + 1).uopIdx := i.U 304 } 305 } 306 is(UopSplitType.VEC_VVW) { 307 for (i <- 0 until MAX_VLMUL / 2) { 308 csBundle(2 * i).lsrc(0) := src1 + i.U 309 csBundle(2 * i).lsrc(1) := src2 + i.U 310 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 311 csBundle(2 * i).ldest := dest + (2 * i).U 312 csBundle(2 * i).uopIdx := (2 * i).U 313 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 314 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 315 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 316 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 317 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 318 } 319 } 320 is(UopSplitType.VEC_VFW) { 321 for (i <- 0 until MAX_VLMUL / 2) { 322 csBundle(2 * i).lsrc(0) := src1 323 csBundle(2 * i).lsrc(1) := src2 + i.U 324 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 325 csBundle(2 * i).ldest := dest + (2 * i).U 326 csBundle(2 * i).uopIdx := (2 * i).U 327 csBundle(2 * i + 1).lsrc(0) := src1 328 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 329 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 330 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 331 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 332 } 333 } 334 is(UopSplitType.VEC_WVW) { 335 for (i <- 0 until MAX_VLMUL / 2) { 336 csBundle(2 * i).lsrc(0) := src1 + i.U 337 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 338 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 339 csBundle(2 * i).ldest := dest + (2 * i).U 340 csBundle(2 * i).uopIdx := (2 * i).U 341 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 342 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 343 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 344 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 345 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 346 } 347 } 348 is(UopSplitType.VEC_VXW) { 349 /* 350 FMV.D.X 351 */ 352 csBundle(0).srcType(0) := SrcType.reg 353 csBundle(0).srcType(1) := SrcType.imm 354 csBundle(0).lsrc(1) := 0.U 355 csBundle(0).ldest := FP_TMP_REG_MV.U 356 csBundle(0).fuType := FuType.i2f.U 357 csBundle(0).rfWen := false.B 358 csBundle(0).fpWen := true.B 359 csBundle(0).vecWen := false.B 360 csBundle(0).fpu.isAddSub := false.B 361 csBundle(0).fpu.typeTagIn := FPU.D 362 csBundle(0).fpu.typeTagOut := FPU.D 363 csBundle(0).fpu.fromInt := true.B 364 csBundle(0).fpu.wflags := false.B 365 csBundle(0).fpu.fpWen := true.B 366 csBundle(0).fpu.div := false.B 367 csBundle(0).fpu.sqrt := false.B 368 csBundle(0).fpu.fcvt := false.B 369 370 for (i <- 0 until MAX_VLMUL / 2) { 371 csBundle(2 * i + 1).srcType(0) := SrcType.fp 372 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 373 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 374 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 375 csBundle(2 * i + 1).ldest := dest + (2 * i).U 376 csBundle(2 * i + 1).uopIdx := (2 * i).U 377 csBundle(2 * i + 2).srcType(0) := SrcType.fp 378 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 379 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 380 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 381 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 382 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 383 } 384 } 385 is(UopSplitType.VEC_WXW) { 386 /* 387 FMV.D.X 388 */ 389 csBundle(0).srcType(0) := SrcType.reg 390 csBundle(0).srcType(1) := SrcType.imm 391 csBundle(0).lsrc(1) := 0.U 392 csBundle(0).ldest := FP_TMP_REG_MV.U 393 csBundle(0).fuType := FuType.i2f.U 394 csBundle(0).rfWen := false.B 395 csBundle(0).fpWen := true.B 396 csBundle(0).vecWen := false.B 397 csBundle(0).fpu.isAddSub := false.B 398 csBundle(0).fpu.typeTagIn := FPU.D 399 csBundle(0).fpu.typeTagOut := FPU.D 400 csBundle(0).fpu.fromInt := true.B 401 csBundle(0).fpu.wflags := false.B 402 csBundle(0).fpu.fpWen := true.B 403 csBundle(0).fpu.div := false.B 404 csBundle(0).fpu.sqrt := false.B 405 csBundle(0).fpu.fcvt := false.B 406 407 for (i <- 0 until MAX_VLMUL / 2) { 408 csBundle(2 * i + 1).srcType(0) := SrcType.fp 409 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 410 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 411 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 412 csBundle(2 * i + 1).ldest := dest + (2 * i).U 413 csBundle(2 * i + 1).uopIdx := (2 * i).U 414 csBundle(2 * i + 2).srcType(0) := SrcType.fp 415 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 416 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 417 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 418 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 419 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 420 } 421 } 422 is(UopSplitType.VEC_WVV) { 423 for (i <- 0 until MAX_VLMUL / 2) { 424 425 csBundle(2 * i).lsrc(0) := src1 + i.U 426 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 427 csBundle(2 * i).lsrc(2) := dest + i.U 428 csBundle(2 * i).ldest := dest + i.U 429 csBundle(2 * i).uopIdx := (2 * i).U 430 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 431 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 432 csBundle(2 * i + 1).lsrc(2) := dest + i.U 433 csBundle(2 * i + 1).ldest := dest + i.U 434 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 435 } 436 } 437 is(UopSplitType.VEC_WFW) { 438 for (i <- 0 until MAX_VLMUL / 2) { 439 csBundle(2 * i).lsrc(0) := src1 440 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 441 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 442 csBundle(2 * i).ldest := dest + (2 * i).U 443 csBundle(2 * i).uopIdx := (2 * i).U 444 csBundle(2 * i + 1).lsrc(0) := src1 445 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 446 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 447 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 448 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 449 } 450 } 451 is(UopSplitType.VEC_WXV) { 452 /* 453 FMV.D.X 454 */ 455 csBundle(0).srcType(0) := SrcType.reg 456 csBundle(0).srcType(1) := SrcType.imm 457 csBundle(0).lsrc(1) := 0.U 458 csBundle(0).ldest := FP_TMP_REG_MV.U 459 csBundle(0).fuType := FuType.i2f.U 460 csBundle(0).rfWen := false.B 461 csBundle(0).fpWen := true.B 462 csBundle(0).vecWen := false.B 463 csBundle(0).fpu.isAddSub := false.B 464 csBundle(0).fpu.typeTagIn := FPU.D 465 csBundle(0).fpu.typeTagOut := FPU.D 466 csBundle(0).fpu.fromInt := true.B 467 csBundle(0).fpu.wflags := false.B 468 csBundle(0).fpu.fpWen := true.B 469 csBundle(0).fpu.div := false.B 470 csBundle(0).fpu.sqrt := false.B 471 csBundle(0).fpu.fcvt := false.B 472 473 for (i <- 0 until MAX_VLMUL / 2) { 474 csBundle(2 * i + 1).srcType(0) := SrcType.fp 475 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 476 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 477 csBundle(2 * i + 1).lsrc(2) := dest + i.U 478 csBundle(2 * i + 1).ldest := dest + i.U 479 csBundle(2 * i + 1).uopIdx := (2 * i).U 480 csBundle(2 * i + 2).srcType(0) := SrcType.fp 481 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 482 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 483 csBundle(2 * i + 2).lsrc(2) := dest + i.U 484 csBundle(2 * i + 2).ldest := dest + i.U 485 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 486 } 487 } 488 is(UopSplitType.VEC_VVM) { 489 csBundle(0).lsrc(2) := dest 490 csBundle(0).ldest := dest 491 csBundle(0).uopIdx := 0.U 492 for (i <- 1 until MAX_VLMUL) { 493 csBundle(i).lsrc(0) := src1 + i.U 494 csBundle(i).lsrc(1) := src2 + i.U 495 csBundle(i).lsrc(2) := dest 496 csBundle(i).ldest := dest 497 csBundle(i).uopIdx := i.U 498 } 499 csBundle(numOfUop - 1.U).ldest := dest 500 } 501 is(UopSplitType.VEC_VXM) { 502 /* 503 FMV.D.X 504 */ 505 csBundle(0).srcType(0) := SrcType.reg 506 csBundle(0).srcType(1) := SrcType.imm 507 csBundle(0).lsrc(1) := 0.U 508 csBundle(0).ldest := FP_TMP_REG_MV.U 509 csBundle(0).fuType := FuType.i2f.U 510 csBundle(0).rfWen := false.B 511 csBundle(0).fpWen := true.B 512 csBundle(0).vecWen := false.B 513 csBundle(0).fpu.isAddSub := false.B 514 csBundle(0).fpu.typeTagIn := FPU.D 515 csBundle(0).fpu.typeTagOut := FPU.D 516 csBundle(0).fpu.fromInt := true.B 517 csBundle(0).fpu.wflags := false.B 518 csBundle(0).fpu.fpWen := true.B 519 csBundle(0).fpu.div := false.B 520 csBundle(0).fpu.sqrt := false.B 521 csBundle(0).fpu.fcvt := false.B 522 //LMUL 523 csBundle(1).srcType(0) := SrcType.fp 524 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 525 csBundle(1).lsrc(2) := dest 526 csBundle(1).ldest := dest 527 csBundle(1).uopIdx := 0.U 528 for (i <- 1 until MAX_VLMUL) { 529 csBundle(i + 1).srcType(0) := SrcType.fp 530 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 531 csBundle(i + 1).lsrc(1) := src2 + i.U 532 csBundle(i + 1).lsrc(2) := dest 533 csBundle(i + 1).ldest := dest 534 csBundle(i + 1).uopIdx := i.U 535 } 536 csBundle(numOfUop - 1.U).ldest := dest 537 } 538 is(UopSplitType.VEC_SLIDE1UP) { 539 /* 540 FMV.D.X 541 */ 542 csBundle(0).srcType(0) := SrcType.reg 543 csBundle(0).srcType(1) := SrcType.imm 544 csBundle(0).lsrc(1) := 0.U 545 csBundle(0).ldest := FP_TMP_REG_MV.U 546 csBundle(0).fuType := FuType.i2f.U 547 csBundle(0).rfWen := false.B 548 csBundle(0).fpWen := true.B 549 csBundle(0).vecWen := false.B 550 csBundle(0).fpu.isAddSub := false.B 551 csBundle(0).fpu.typeTagIn := FPU.D 552 csBundle(0).fpu.typeTagOut := FPU.D 553 csBundle(0).fpu.fromInt := true.B 554 csBundle(0).fpu.wflags := false.B 555 csBundle(0).fpu.fpWen := true.B 556 csBundle(0).fpu.div := false.B 557 csBundle(0).fpu.sqrt := false.B 558 csBundle(0).fpu.fcvt := false.B 559 //LMUL 560 csBundle(1).srcType(0) := SrcType.fp 561 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 562 csBundle(1).lsrc(2) := dest 563 csBundle(1).ldest := dest 564 csBundle(1).uopIdx := 0.U 565 for (i <- 1 until MAX_VLMUL) { 566 csBundle(i + 1).srcType(0) := SrcType.vp 567 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 568 csBundle(i + 1).lsrc(1) := src2 + i.U 569 csBundle(i + 1).lsrc(2) := dest + i.U 570 csBundle(i + 1).ldest := dest + i.U 571 csBundle(i + 1).uopIdx := i.U 572 } 573 } 574 is(UopSplitType.VEC_FSLIDE1UP) { 575 //LMUL 576 csBundle(0).srcType(0) := SrcType.fp 577 csBundle(0).lsrc(0) := src1 578 csBundle(0).lsrc(1) := src2 579 csBundle(0).lsrc(2) := dest 580 csBundle(0).ldest := dest 581 csBundle(0).uopIdx := 0.U 582 for (i <- 1 until MAX_VLMUL) { 583 csBundle(i).srcType(0) := SrcType.vp 584 csBundle(i).lsrc(0) := src2 + (i - 1).U 585 csBundle(i).lsrc(1) := src2 + i.U 586 csBundle(i).lsrc(2) := dest + i.U 587 csBundle(i).ldest := dest + i.U 588 csBundle(i).uopIdx := i.U 589 } 590 } 591 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 592 /* 593 FMV.D.X 594 */ 595 csBundle(0).srcType(0) := SrcType.reg 596 csBundle(0).srcType(1) := SrcType.imm 597 csBundle(0).lsrc(1) := 0.U 598 csBundle(0).ldest := FP_TMP_REG_MV.U 599 csBundle(0).fuType := FuType.i2f.U 600 csBundle(0).rfWen := false.B 601 csBundle(0).fpWen := true.B 602 csBundle(0).vecWen := false.B 603 csBundle(0).fpu.isAddSub := false.B 604 csBundle(0).fpu.typeTagIn := FPU.D 605 csBundle(0).fpu.typeTagOut := FPU.D 606 csBundle(0).fpu.fromInt := true.B 607 csBundle(0).fpu.wflags := false.B 608 csBundle(0).fpu.fpWen := true.B 609 csBundle(0).fpu.div := false.B 610 csBundle(0).fpu.sqrt := false.B 611 csBundle(0).fpu.fcvt := false.B 612 //LMUL 613 for (i <- 0 until MAX_VLMUL) { 614 csBundle(2 * i + 1).srcType(0) := SrcType.vp 615 csBundle(2 * i + 1).srcType(1) := SrcType.vp 616 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 617 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 618 csBundle(2 * i + 1).lsrc(2) := dest + i.U 619 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 620 csBundle(2 * i + 1).uopIdx := (2 * i).U 621 if (2 * i + 2 < MAX_VLMUL * 2) { 622 csBundle(2 * i + 2).srcType(0) := SrcType.fp 623 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 624 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 625 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 626 csBundle(2 * i + 2).ldest := dest + i.U 627 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 628 } 629 } 630 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 631 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 632 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 633 } 634 is(UopSplitType.VEC_FSLIDE1DOWN) { 635 //LMUL 636 for (i <- 0 until MAX_VLMUL) { 637 csBundle(2 * i).srcType(0) := SrcType.vp 638 csBundle(2 * i).srcType(1) := SrcType.vp 639 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 640 csBundle(2 * i).lsrc(1) := src2 + i.U 641 csBundle(2 * i).lsrc(2) := dest + i.U 642 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 643 csBundle(2 * i).uopIdx := (2 * i).U 644 csBundle(2 * i + 1).srcType(0) := SrcType.fp 645 csBundle(2 * i + 1).lsrc(0) := src1 646 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 647 csBundle(2 * i + 1).ldest := dest + i.U 648 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 649 } 650 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 651 csBundle(numOfUop - 1.U).lsrc(0) := src1 652 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 653 } 654 is(UopSplitType.VEC_VRED) { 655 when(simple.io.enq.vtype.vlmul === "b001".U) { 656 csBundle(0).srcType(2) := SrcType.DC 657 csBundle(0).lsrc(0) := src2 + 1.U 658 csBundle(0).lsrc(1) := src2 659 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 660 csBundle(0).uopIdx := 0.U 661 } 662 when(simple.io.enq.vtype.vlmul === "b010".U) { 663 csBundle(0).srcType(2) := SrcType.DC 664 csBundle(0).lsrc(0) := src2 + 1.U 665 csBundle(0).lsrc(1) := src2 666 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 667 csBundle(0).uopIdx := 0.U 668 669 csBundle(1).srcType(2) := SrcType.DC 670 csBundle(1).lsrc(0) := src2 + 3.U 671 csBundle(1).lsrc(1) := src2 + 2.U 672 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 673 csBundle(1).uopIdx := 1.U 674 675 csBundle(2).srcType(2) := SrcType.DC 676 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 677 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 678 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 679 csBundle(2).uopIdx := 2.U 680 } 681 when(simple.io.enq.vtype.vlmul === "b011".U) { 682 for (i <- 0 until MAX_VLMUL) { 683 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 684 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 685 csBundle(i).lsrc(1) := src2 + (i * 2).U 686 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 687 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 688 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 689 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 690 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 691 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 692 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 693 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 694 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 695 } 696 csBundle(i).srcType(2) := SrcType.DC 697 csBundle(i).uopIdx := i.U 698 } 699 } 700 when(simple.io.enq.vtype.vlmul.orR()) { 701 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 702 csBundle(numOfUop - 1.U).lsrc(0) := src1 703 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 704 csBundle(numOfUop - 1.U).lsrc(2) := dest 705 csBundle(numOfUop - 1.U).ldest := dest 706 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 707 } 708 } 709 710 is(UopSplitType.VEC_SLIDEUP) { 711 // FMV.D.X 712 csBundle(0).srcType(0) := SrcType.reg 713 csBundle(0).srcType(1) := SrcType.imm 714 csBundle(0).lsrc(1) := 0.U 715 csBundle(0).ldest := FP_TMP_REG_MV.U 716 csBundle(0).fuType := FuType.i2f.U 717 csBundle(0).rfWen := false.B 718 csBundle(0).fpWen := true.B 719 csBundle(0).vecWen := false.B 720 csBundle(0).fpu.isAddSub := false.B 721 csBundle(0).fpu.typeTagIn := FPU.D 722 csBundle(0).fpu.typeTagOut := FPU.D 723 csBundle(0).fpu.fromInt := true.B 724 csBundle(0).fpu.wflags := false.B 725 csBundle(0).fpu.fpWen := true.B 726 csBundle(0).fpu.div := false.B 727 csBundle(0).fpu.sqrt := false.B 728 csBundle(0).fpu.fcvt := false.B 729 // LMUL 730 for (i <- 0 until MAX_VLMUL) 731 for (j <- 0 to i) { 732 val old_vd = if (j == 0) { 733 dest + i.U 734 } else (VECTOR_TMP_REG_LMUL + j - 1).U 735 val vd = if (j == i) { 736 dest + i.U 737 } else (VECTOR_TMP_REG_LMUL + j).U 738 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.fp 739 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := FP_TMP_REG_MV.U 740 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 741 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 742 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 743 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 744 } 745 } 746 747 is(UopSplitType.VEC_ISLIDEUP) { 748 // LMUL 749 for (i <- 0 until MAX_VLMUL) 750 for (j <- 0 to i) { 751 val old_vd = if (j == 0) { 752 dest + i.U 753 } else (VECTOR_TMP_REG_LMUL + j - 1).U 754 val vd = if (j == i) { 755 dest + i.U 756 } else (VECTOR_TMP_REG_LMUL + j).U 757 csBundle(i * (i + 1) / 2 + j).lsrc(1) := src2 + j.U 758 csBundle(i * (i + 1) / 2 + j).lsrc(2) := old_vd 759 csBundle(i * (i + 1) / 2 + j).ldest := vd 760 csBundle(i * (i + 1) / 2 + j).uopIdx := (i * (i + 1) / 2 + j).U 761 } 762 } 763 764 is(UopSplitType.VEC_SLIDEDOWN) { 765 // FMV.D.X 766 csBundle(0).srcType(0) := SrcType.reg 767 csBundle(0).srcType(1) := SrcType.imm 768 csBundle(0).lsrc(1) := 0.U 769 csBundle(0).ldest := FP_TMP_REG_MV.U 770 csBundle(0).fuType := FuType.i2f.U 771 csBundle(0).rfWen := false.B 772 csBundle(0).fpWen := true.B 773 csBundle(0).vecWen := false.B 774 csBundle(0).fpu.isAddSub := false.B 775 csBundle(0).fpu.typeTagIn := FPU.D 776 csBundle(0).fpu.typeTagOut := FPU.D 777 csBundle(0).fpu.fromInt := true.B 778 csBundle(0).fpu.wflags := false.B 779 csBundle(0).fpu.fpWen := true.B 780 csBundle(0).fpu.div := false.B 781 csBundle(0).fpu.sqrt := false.B 782 csBundle(0).fpu.fcvt := false.B 783 // LMUL 784 for (i <- 0 until MAX_VLMUL) 785 for (j <- (0 to i).reverse) { 786 when(i.U < lmul) { 787 val old_vd = if (j == 0) { 788 dest + lmul - 1.U - i.U 789 } else (VECTOR_TMP_REG_LMUL + j - 1).U 790 val vd = if (j == i) { 791 dest + lmul - 1.U - i.U 792 } else (VECTOR_TMP_REG_LMUL + j).U 793 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.fp 794 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := FP_TMP_REG_MV.U 795 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 796 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 797 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 798 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 799 } 800 } 801 } 802 803 is(UopSplitType.VEC_ISLIDEDOWN) { 804 // LMUL 805 for (i <- 0 until MAX_VLMUL) 806 for (j <- (0 to i).reverse) { 807 when(i.U < lmul) { 808 val old_vd = if (j == 0) { 809 dest + lmul - 1.U - i.U 810 } else (VECTOR_TMP_REG_LMUL + j - 1).U 811 val vd = if (j == i) { 812 dest + lmul - 1.U - i.U 813 } else (VECTOR_TMP_REG_LMUL + j).U 814 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 815 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 816 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 817 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 1).U 818 } 819 } 820 } 821 822 is(UopSplitType.VEC_M0X) { 823 // LMUL 824 for (i <- 0 until MAX_VLMUL) { 825 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 826 val ldest = (VECTOR_TMP_REG_LMUL + i).U 827 csBundle(i).srcType(0) := srcType0 828 csBundle(i).srcType(1) := SrcType.vp 829 csBundle(i).rfWen := false.B 830 csBundle(i).vecWen := true.B 831 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 832 csBundle(i).lsrc(1) := src2 833 // csBundle(i).lsrc(2) := dest + i.U DontCare 834 csBundle(i).ldest := ldest 835 csBundle(i).uopIdx := i.U 836 } 837 csBundle(lmul - 1.U).vecWen := false.B 838 csBundle(lmul - 1.U).fpWen := true.B 839 csBundle(lmul - 1.U).ldest := FP_TMP_REG_MV.U 840 // FMV_X_D 841 csBundle(lmul).srcType(0) := SrcType.fp 842 csBundle(lmul).srcType(1) := SrcType.imm 843 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 844 csBundle(lmul).lsrc(1) := 0.U 845 csBundle(lmul).ldest := dest 846 csBundle(lmul).fuType := FuType.fmisc.U 847 csBundle(lmul).rfWen := true.B 848 csBundle(lmul).fpWen := false.B 849 csBundle(lmul).vecWen := false.B 850 csBundle(lmul).fpu.isAddSub := false.B 851 csBundle(lmul).fpu.typeTagIn := FPU.D 852 csBundle(lmul).fpu.typeTagOut := FPU.D 853 csBundle(lmul).fpu.fromInt := false.B 854 csBundle(lmul).fpu.wflags := false.B 855 csBundle(lmul).fpu.fpWen := false.B 856 csBundle(lmul).fpu.div := false.B 857 csBundle(lmul).fpu.sqrt := false.B 858 csBundle(lmul).fpu.fcvt := false.B 859 } 860 861 is(UopSplitType.VEC_MVV) { 862 // LMUL 863 for (i <- 0 until MAX_VLMUL) { 864 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 865 csBundle(i * 2 + 0).srcType(0) := srcType0 866 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 867 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 868 csBundle(i * 2 + 0).lsrc(1) := src2 869 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 870 csBundle(i * 2 + 0).ldest := dest + i.U 871 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 872 873 csBundle(i * 2 + 1).srcType(0) := srcType0 874 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 875 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 876 csBundle(i * 2 + 1).lsrc(1) := src2 877 // csBundle(i).lsrc(2) := dest + i.U DontCare 878 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 879 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 880 } 881 } 882 883 is(UopSplitType.VEC_M0X_VFIRST) { 884 // LMUL 885 csBundle(0).rfWen := false.B 886 csBundle(0).fpWen := true.B 887 csBundle(0).ldest := FP_TMP_REG_MV.U 888 // FMV_X_D 889 csBundle(1).srcType(0) := SrcType.fp 890 csBundle(1).srcType(1) := SrcType.imm 891 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 892 csBundle(1).lsrc(1) := 0.U 893 csBundle(1).ldest := dest 894 csBundle(1).fuType := FuType.fmisc.U 895 csBundle(1).rfWen := true.B 896 csBundle(1).fpWen := false.B 897 csBundle(1).vecWen := false.B 898 csBundle(1).fpu.isAddSub := false.B 899 csBundle(1).fpu.typeTagIn := FPU.D 900 csBundle(1).fpu.typeTagOut := FPU.D 901 csBundle(1).fpu.fromInt := false.B 902 csBundle(1).fpu.wflags := false.B 903 csBundle(1).fpu.fpWen := false.B 904 csBundle(1).fpu.div := false.B 905 csBundle(1).fpu.sqrt := false.B 906 csBundle(1).fpu.fcvt := false.B 907 } 908 is(UopSplitType.VEC_VWW) { 909 for (i <- 0 until MAX_VLMUL*2) { 910 when(i.U < lmul){ 911 csBundle(i).srcType(2) := SrcType.DC 912 csBundle(i).lsrc(0) := src2 + i.U 913 csBundle(i).lsrc(1) := src2 + i.U 914 // csBundle(i).lsrc(2) := dest + (2 * i).U 915 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 916 csBundle(i).uopIdx := i.U 917 } otherwise { 918 csBundle(i).srcType(2) := SrcType.DC 919 csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 920 csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 921 // csBundle(i).lsrc(2) := dest + (2 * i).U 922 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 923 csBundle(i).uopIdx := i.U 924 } 925 csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 926 csBundle(numOfUop-1.U).lsrc(0) := src1 927 csBundle(numOfUop-1.U).lsrc(2) := dest 928 csBundle(numOfUop-1.U).ldest := dest 929 } 930 } 931 is(UopSplitType.VEC_RGATHER) { 932 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 933 for (i <- 0 until len) 934 for (j <- 0 until len) { 935 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 936 // csBundle(i * len + j).srcType(1) := SrcType.vp 937 // csBundle(i * len + j).srcType(2) := SrcType.vp 938 csBundle(i * len + j).lsrc(0) := src1 + i.U 939 csBundle(i * len + j).lsrc(1) := src2 + j.U 940 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 941 csBundle(i * len + j).lsrc(2) := vd_old 942 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 943 csBundle(i * len + j).ldest := vd 944 csBundle(i * len + j).uopIdx := (i * len + j).U 945 } 946 } 947 switch(simple.io.enq.vtype.vlmul) { 948 is("b001".U ){ 949 genCsBundle_VEC_RGATHER(2) 950 } 951 is("b010".U ){ 952 genCsBundle_VEC_RGATHER(4) 953 } 954 is("b011".U ){ 955 genCsBundle_VEC_RGATHER(8) 956 } 957 } 958 } 959 is(UopSplitType.VEC_RGATHER_VX) { 960 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 961 for (i <- 0 until len) 962 for (j <- 0 until len) { 963 csBundle(i * len + j + 1).srcType(0) := SrcType.fp 964 // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 965 // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 966 csBundle(i * len + j + 1).lsrc(0) := FP_TMP_REG_MV.U 967 csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 968 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 969 csBundle(i * len + j + 1).lsrc(2) := vd_old 970 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 971 csBundle(i * len + j + 1).ldest := vd 972 csBundle(i * len + j + 1).uopIdx := (i * len + j).U 973 } 974 } 975 // FMV.D.X 976 csBundle(0).srcType(0) := SrcType.reg 977 csBundle(0).srcType(1) := SrcType.imm 978 csBundle(0).lsrc(1) := 0.U 979 csBundle(0).ldest := FP_TMP_REG_MV.U 980 csBundle(0).fuType := FuType.i2f.U 981 csBundle(0).rfWen := false.B 982 csBundle(0).fpWen := true.B 983 csBundle(0).vecWen := false.B 984 csBundle(0).fpu.isAddSub := false.B 985 csBundle(0).fpu.typeTagIn := FPU.D 986 csBundle(0).fpu.typeTagOut := FPU.D 987 csBundle(0).fpu.fromInt := true.B 988 csBundle(0).fpu.wflags := false.B 989 csBundle(0).fpu.fpWen := true.B 990 csBundle(0).fpu.div := false.B 991 csBundle(0).fpu.sqrt := false.B 992 csBundle(0).fpu.fcvt := false.B 993 switch(simple.io.enq.vtype.vlmul) { 994 is("b000".U ){ 995 genCsBundle_RGATHER_VX(1) 996 } 997 is("b001".U ){ 998 genCsBundle_RGATHER_VX(2) 999 } 1000 is("b010".U ){ 1001 genCsBundle_RGATHER_VX(4) 1002 } 1003 is("b011".U ){ 1004 genCsBundle_RGATHER_VX(8) 1005 } 1006 } 1007 } 1008 is(UopSplitType.VEC_RGATHEREI16) { 1009 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 1010 for (i <- 0 until len) 1011 for (j <- 0 until len) { 1012 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 1013 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 1014 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1015 // csBundle(i * len + j).srcType(1) := SrcType.vp 1016 // csBundle(i * len + j).srcType(2) := SrcType.vp 1017 csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 1018 csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 1019 csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 1020 csBundle((i * len + j)*2+0).ldest := vd0 1021 csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 1022 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 1023 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 1024 csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 1025 csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 1026 csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 1027 csBundle((i * len + j)*2+1).ldest := vd1 1028 csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 1029 } 1030 } 1031 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 1032 for (i <- 0 until len) 1033 for (j <- 0 until len) { 1034 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 1035 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1036 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1037 // csBundle(i * len + j).srcType(1) := SrcType.vp 1038 // csBundle(i * len + j).srcType(2) := SrcType.vp 1039 csBundle(i * len + j).lsrc(0) := src1 + i.U 1040 csBundle(i * len + j).lsrc(1) := src2 + j.U 1041 csBundle(i * len + j).lsrc(2) := vd_old 1042 csBundle(i * len + j).ldest := vd 1043 csBundle(i * len + j).uopIdx := (i * len + j).U 1044 } 1045 } 1046 switch(simple.io.enq.vtype.vlmul) { 1047 is("b000".U ){ 1048 when(!simple.io.enq.vtype.vsew.orR){ 1049 genCsBundle_VEC_RGATHEREI16_SEW8(1) 1050 } .otherwise{ 1051 genCsBundle_VEC_RGATHEREI16(1) 1052 } 1053 } 1054 is("b001".U) { 1055 when(!simple.io.enq.vtype.vsew.orR) { 1056 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1057 }.otherwise { 1058 genCsBundle_VEC_RGATHEREI16(2) 1059 } 1060 } 1061 is("b010".U) { 1062 when(!simple.io.enq.vtype.vsew.orR) { 1063 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1064 }.otherwise { 1065 genCsBundle_VEC_RGATHEREI16(4) 1066 } 1067 } 1068 is("b011".U) { 1069 genCsBundle_VEC_RGATHEREI16(8) 1070 } 1071 } 1072 } 1073 is(UopSplitType.VEC_COMPRESS) { 1074 def genCsBundle_VEC_COMPRESS(len:Int): Unit ={ 1075 for (i <- 0 until len){ 1076 val jlen = if (i == len-1) i+1 else i+2 1077 for (j <- 0 until jlen) { 1078 val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1079 val vd = if(i==len-1) (dest + j.U) else{ 1080 if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1081 } 1082 val src23Type = if (j == i+1) DontCare else SrcType.vp 1083 csBundle(i*(i+3)/2 + j).srcType(0) := SrcType.vp 1084 csBundle(i*(i+3)/2 + j).srcType(1) := src23Type 1085 csBundle(i*(i+3)/2 + j).srcType(2) := src23Type 1086 csBundle(i*(i+3)/2 + j).lsrc(0) := src1 1087 csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1088 csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1089 // csBundle(i*(i+3)/2 + j).lsrc(3) := VECTOR_TMP_REG_LMUL.U 1090 csBundle(i*(i+3)/2 + j).ldest := vd 1091 csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1092 } 1093 } 1094 } 1095 switch(simple.io.enq.vtype.vlmul) { 1096 is("b001".U ){ 1097 genCsBundle_VEC_COMPRESS(2) 1098 } 1099 is("b010".U ){ 1100 genCsBundle_VEC_COMPRESS(4) 1101 } 1102 is("b011".U ){ 1103 genCsBundle_VEC_COMPRESS(8) 1104 } 1105 } 1106 } 1107 is(UopSplitType.VEC_US_LD) { 1108 /* 1109 FMV.D.X 1110 */ 1111 csBundle(0).srcType(0) := SrcType.reg 1112 csBundle(0).srcType(1) := SrcType.imm 1113 csBundle(0).lsrc(1) := 0.U 1114 csBundle(0).ldest := FP_TMP_REG_MV.U 1115 csBundle(0).fuType := FuType.i2f.U 1116 csBundle(0).rfWen := false.B 1117 csBundle(0).fpWen := true.B 1118 csBundle(0).vecWen := false.B 1119 csBundle(0).fpu.isAddSub := false.B 1120 csBundle(0).fpu.typeTagIn := FPU.D 1121 csBundle(0).fpu.typeTagOut := FPU.D 1122 csBundle(0).fpu.fromInt := true.B 1123 csBundle(0).fpu.wflags := false.B 1124 csBundle(0).fpu.fpWen := true.B 1125 csBundle(0).fpu.div := false.B 1126 csBundle(0).fpu.sqrt := false.B 1127 csBundle(0).fpu.fcvt := false.B 1128 //LMUL 1129 for (i <- 0 until MAX_VLMUL) { 1130 csBundle(i + 1).srcType(0) := SrcType.fp 1131 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1132 csBundle(i + 1).ldest := dest + i.U 1133 csBundle(i + 1).uopIdx := i.U 1134 } 1135 } 1136 } 1137 1138 //uops dispatch 1139 val s_normal :: s_ext :: Nil = Enum(2) 1140 val state = RegInit(s_normal) 1141 val state_next = WireDefault(state) 1142 val uopRes = RegInit(0.U) 1143 1144 //readyFromRename Counter 1145 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 1146 1147 switch(state) { 1148 is(s_normal) { 1149 state_next := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), s_ext, s_normal) 1150 } 1151 is(s_ext) { 1152 state_next := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), s_ext, s_normal) 1153 } 1154 } 1155 1156 state := state_next 1157 1158 val uopRes0 = Mux(state === s_normal, numOfUop, uopRes) 1159 val uopResJudge = Mux(state === s_normal, 1160 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 1161 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 1162 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 1163 1164 for(i <- 0 until RenameWidth) { 1165 decodedInsts(i) := MuxCase(csBundle(i), Seq( 1166 (state === s_normal) -> csBundle(i), 1167 (state === s_ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 1168 )) 1169 } 1170 1171 1172 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 1173 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1174 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 1175 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1176 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1177 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1178 notInfVec(0) := true.B 1179 1180 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1181 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1182 1.U) 1183 validToRename.zipWithIndex.foreach{ 1184 case(dst, i) => 1185 dst := MuxCase(false.B, Seq( 1186 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 1187 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1188 )) 1189 } 1190 1191 readyToIBuf.zipWithIndex.foreach { 1192 case (dst, i) => 1193 dst := MuxCase(true.B, Seq( 1194 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 1195 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 1196 )) 1197 } 1198 1199 io.deq.decodedInsts := decodedInsts 1200 io.deq.isVset := isVsetSimple 1201 io.deq.complexNum := complexNum 1202 io.deq.validToRename := validToRename 1203 io.deq.readyToIBuf := readyToIBuf 1204 1205} 1206