1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VppuType 31import scala.collection.Seq 32 33trait VectorConstants { 34 val MAX_VLMUL = 8 35 val FP_TMP_REG_MV = 33 36 val VECTOR_TMP_REG_MV = 33 37 val VECTOR_TMP_REG_LMUL = 34 38} 39 40class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 41 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 42 val vconfig = Input(new VConfig) 43 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 44 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 45 val readyFromRename = Input(Vec(RenameWidth, Bool())) 46 val deq = new Bundle { 47 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 48 val isVset = Output(Bool()) 49 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 50 val validToRename = Output(Vec(RenameWidth, Bool())) 51 val complexNum = Output(UInt(3.W)) 52 } 53 val csrCtrl = Input(new CustomCSRCtrlIO) 54} 55 56class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 57 val io = IO(new DecodeUnitCompIO) 58 //input bits 59 val ctrl_flow = Wire(new CtrlFlow) 60 ctrl_flow := io.enq.ctrl_flow 61 //output bits 62 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 63 val validToRename = Wire(Vec(RenameWidth, Bool())) 64 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 65 val complexNum = Wire(UInt(3.W)) 66 67 //output of DecodeUnit 68 val cf_ctrl_u = Wire(new CfCtrl) 69 val isVset_u = Wire(Bool()) 70 val isComplex_u = Wire(Bool()) 71 72 //pre decode 73 val simple = Module(new DecodeUnit) 74 simple.io.enq.ctrl_flow := ctrl_flow 75 simple.io.vconfig := io.vconfig 76 simple.io.csrCtrl := io.csrCtrl 77 cf_ctrl_u := simple.io.deq.cf_ctrl 78 isVset_u := simple.io.deq.isVset 79 isComplex_u := simple.io.deq.isComplex 80 81 //Type of uop Div 82 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 83 84 //LMUL 85 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U, Array( 86 "b001".U -> 2.U, 87 "b010".U -> 4.U, 88 "b011".U -> 8.U 89 )) 90 //number of uop 91 val numOfUop = MuxLookup(typeOfDiv, 1.U, Array( 92 UopDivType.VEC_MV -> 2.U, 93 UopDivType.DIR -> 2.U, 94 UopDivType.VEC_LMUL -> lmul, 95 UopDivType.VEC_EXT2 -> lmul, 96 UopDivType.VEC_EXT4 -> lmul, 97 UopDivType.VEC_EXT8 -> lmul, 98 UopDivType.VEC_MASK -> lmul, 99 UopDivType.VEC_MV_MASK -> (lmul + 1.U), 100 UopDivType.VEC_MV_LMUL -> (lmul + 1.U), 101 UopDivType.VEC_WIDE -> (lmul + lmul), //lmul <= 4 102 UopDivType.VEC_WIDE0 -> (lmul + lmul), //lmul <= 4 103 UopDivType.VEC_MV_WIDE -> (lmul + lmul + 1.U), //lmul <= 4 104 UopDivType.VEC_MV_WIDE0 -> (lmul + lmul + 1.U), //lmul <= 4 105 UopDivType.VEC_NARROW -> (lmul + lmul), //lmul <= 4 106 UopDivType.VEC_MV_NARROW -> (lmul + lmul + 1.U) //lmul <= 4 107 )) 108 109 //uop div up to maxNumOfUop 110 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 111 csBundle.map { case dst => 112 dst := cf_ctrl_u 113 dst.ctrl.firstUop := false.B 114 dst.ctrl.lastUop := false.B 115 } 116 117 csBundle(0).ctrl.firstUop := true.B 118 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 119 120 switch(typeOfDiv) { 121 is(UopDivType.DIR) { 122 when(isVset_u) { 123 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR 124 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 125 csBundle(1).ctrl.ldest := 32.U 126 csBundle(1).ctrl.flushPipe := false.B 127 } 128 } 129 is(UopDivType.VEC_LMUL) { 130 for (i <- 0 until MAX_VLMUL) { 131 csBundle(i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 132 csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 133 csBundle(i).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 134 csBundle(i).ctrl.uopIdx := i.U 135 } 136 } 137 is(UopDivType.VEC_EXT2) { 138 for (i <- 0 until MAX_VLMUL / 2) { 139 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 140 csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 141 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 142 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 143 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 144 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 145 } 146 } 147 is(UopDivType.VEC_EXT4) { 148 for (i <- 0 until MAX_VLMUL / 4) { 149 csBundle(4 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 150 csBundle(4 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i).U 151 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 152 csBundle(4 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 153 csBundle(4 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 1).U 154 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 155 csBundle(4 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 156 csBundle(4 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 2).U 157 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 158 csBundle(4 * i + 3).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 159 csBundle(4 * i + 3).ctrl.ldest := ctrl_flow.instr(11, 7) + (4 * i + 3).U 160 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 161 } 162 } 163 is(UopDivType.VEC_EXT8) { 164 for (i <- 0 until MAX_VLMUL) { 165 csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) 166 csBundle(i).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 167 csBundle(i).ctrl.uopIdx := i.U 168 } 169 } 170 is(UopDivType.VEC_MV) { 171 /* 172 FMV.D.X 173 */ 174 csBundle(0).ctrl.srcType(0) := SrcType.reg 175 csBundle(0).ctrl.srcType(1) := SrcType.imm 176 csBundle(0).ctrl.lsrc(1) := 0.U 177 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 178 csBundle(0).ctrl.fuType := FuType.i2f 179 csBundle(0).ctrl.rfWen := false.B 180 csBundle(0).ctrl.fpWen := true.B 181 csBundle(0).ctrl.vecWen := false.B 182 csBundle(0).ctrl.fpu.isAddSub := false.B 183 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 184 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 185 csBundle(0).ctrl.fpu.fromInt := true.B 186 csBundle(0).ctrl.fpu.wflags := false.B 187 csBundle(0).ctrl.fpu.fpWen := true.B 188 csBundle(0).ctrl.fpu.div := false.B 189 csBundle(0).ctrl.fpu.sqrt := false.B 190 csBundle(0).ctrl.fpu.fcvt := false.B 191 /* 192 vfmv.s.f 193 */ 194 csBundle(1).ctrl.srcType(0) := SrcType.fp 195 csBundle(1).ctrl.srcType(1) := SrcType.vp 196 csBundle(1).ctrl.srcType(2) := SrcType.vp 197 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 198 csBundle(1).ctrl.lsrc(1) := 0.U 199 csBundle(1).ctrl.lsrc(2) := ctrl_flow.instr(11, 7) 200 csBundle(1).ctrl.ldest := ctrl_flow.instr(11, 7) 201 csBundle(1).ctrl.fuType := FuType.vppu 202 csBundle(1).ctrl.fuOpType := VppuType.f2s 203 csBundle(1).ctrl.rfWen := false.B 204 csBundle(1).ctrl.fpWen := false.B 205 csBundle(1).ctrl.vecWen := true.B 206 } 207 is(UopDivType.VEC_MV_LMUL) { 208 /* 209 FMV.D.X 210 */ 211 csBundle(0).ctrl.srcType(0) := SrcType.reg 212 csBundle(0).ctrl.srcType(1) := SrcType.imm 213 csBundle(0).ctrl.lsrc(1) := 0.U 214 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_MV.U 215 csBundle(0).ctrl.fuType := FuType.i2f 216 csBundle(0).ctrl.rfWen := false.B 217 csBundle(0).ctrl.fpWen := false.B 218 csBundle(0).ctrl.vecWen := true.B 219 csBundle(0).ctrl.fpu.isAddSub := false.B 220 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 221 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 222 csBundle(0).ctrl.fpu.fromInt := true.B 223 csBundle(0).ctrl.fpu.wflags := false.B 224 csBundle(0).ctrl.fpu.fpWen := false.B 225 csBundle(0).ctrl.fpu.div := false.B 226 csBundle(0).ctrl.fpu.sqrt := false.B 227 csBundle(0).ctrl.fpu.fcvt := false.B 228 /* 229 LMUL 230 */ 231 for (i <- 0 until MAX_VLMUL) { 232 csBundle(i + 1).ctrl.srcType(0) := SrcType.vp 233 csBundle(i + 1).ctrl.lsrc(0) := VECTOR_TMP_REG_MV.U 234 csBundle(i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 235 csBundle(i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 236 csBundle(i + 1).ctrl.uopIdx := i.U 237 } 238 } 239 is(UopDivType.VEC_WIDE) { 240 for (i <- 0 until MAX_VLMUL / 2) { 241 csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 242 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 243 csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 244 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 245 csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 246 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 247 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 248 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 249 } 250 } 251 is(UopDivType.VEC_WIDE0) { 252 for (i <- 0 until MAX_VLMUL / 2) { 253 csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 254 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 255 csBundle(2 * i).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 256 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 257 csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 258 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 259 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 260 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 261 } 262 } 263 is(UopDivType.VEC_MV_WIDE) { 264 /* 265 FMV.D.X 266 */ 267 csBundle(0).ctrl.srcType(0) := SrcType.reg 268 csBundle(0).ctrl.srcType(1) := SrcType.imm 269 csBundle(0).ctrl.lsrc(1) := 0.U 270 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_MV.U 271 csBundle(0).ctrl.fuType := FuType.i2f 272 csBundle(0).ctrl.rfWen := false.B 273 csBundle(0).ctrl.fpWen := false.B 274 csBundle(0).ctrl.vecWen := true.B 275 csBundle(0).ctrl.fpu.isAddSub := false.B 276 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 277 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 278 csBundle(0).ctrl.fpu.fromInt := true.B 279 csBundle(0).ctrl.fpu.wflags := false.B 280 csBundle(0).ctrl.fpu.fpWen := false.B 281 csBundle(0).ctrl.fpu.div := false.B 282 csBundle(0).ctrl.fpu.sqrt := false.B 283 csBundle(0).ctrl.fpu.fcvt := false.B 284 285 for (i <- 0 until MAX_VLMUL / 2) { 286 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp 287 csBundle(2 * i + 1).ctrl.lsrc(0) := VECTOR_TMP_REG_MV.U 288 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 289 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 290 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 291 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.vp 292 csBundle(2 * i + 2).ctrl.lsrc(0) := VECTOR_TMP_REG_MV.U 293 csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 294 csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 295 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 296 } 297 } 298 is(UopDivType.VEC_MV_WIDE0) { 299 /* 300 FMV.D.X 301 */ 302 csBundle(0).ctrl.srcType(0) := SrcType.reg 303 csBundle(0).ctrl.srcType(1) := SrcType.imm 304 csBundle(0).ctrl.lsrc(1) := 0.U 305 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_MV.U 306 csBundle(0).ctrl.fuType := FuType.i2f 307 csBundle(0).ctrl.rfWen := false.B 308 csBundle(0).ctrl.fpWen := false.B 309 csBundle(0).ctrl.vecWen := true.B 310 csBundle(0).ctrl.fpu.isAddSub := false.B 311 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 312 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 313 csBundle(0).ctrl.fpu.fromInt := true.B 314 csBundle(0).ctrl.fpu.wflags := false.B 315 csBundle(0).ctrl.fpu.fpWen := false.B 316 csBundle(0).ctrl.fpu.div := false.B 317 csBundle(0).ctrl.fpu.sqrt := false.B 318 csBundle(0).ctrl.fpu.fcvt := false.B 319 320 for (i <- 0 until MAX_VLMUL / 2) { 321 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp 322 csBundle(2 * i + 1).ctrl.lsrc(0) := VECTOR_TMP_REG_MV.U 323 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 324 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i).U 325 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 326 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.vp 327 csBundle(2 * i + 2).ctrl.lsrc(0) := VECTOR_TMP_REG_MV.U 328 csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 329 csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + (2 * i + 1).U 330 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 331 } 332 } 333 is(UopDivType.VEC_NARROW) { 334 for (i <- 0 until MAX_VLMUL / 2) { 335 336 csBundle(2 * i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 337 csBundle(2 * i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 338 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 339 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 340 csBundle(2 * i + 1).ctrl.srcType(2) := SrcType.vp 341 csBundle(2 * i + 1).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 342 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 343 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 344 csBundle(2 * i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 345 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 346 } 347 } 348 is(UopDivType.VEC_MV_NARROW) { 349 /* 350 FMV.D.X 351 */ 352 csBundle(0).ctrl.srcType(0) := SrcType.reg 353 csBundle(0).ctrl.srcType(1) := SrcType.imm 354 csBundle(0).ctrl.lsrc(1) := 0.U 355 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_MV.U 356 csBundle(0).ctrl.fuType := FuType.i2f 357 csBundle(0).ctrl.rfWen := false.B 358 csBundle(0).ctrl.fpWen := false.B 359 csBundle(0).ctrl.vecWen := true.B 360 csBundle(0).ctrl.fpu.isAddSub := false.B 361 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 362 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 363 csBundle(0).ctrl.fpu.fromInt := true.B 364 csBundle(0).ctrl.fpu.wflags := false.B 365 csBundle(0).ctrl.fpu.fpWen := false.B 366 csBundle(0).ctrl.fpu.div := false.B 367 csBundle(0).ctrl.fpu.sqrt := false.B 368 csBundle(0).ctrl.fpu.fcvt := false.B 369 370 for (i <- 0 until MAX_VLMUL / 2) { 371 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp 372 csBundle(2 * i + 1).ctrl.lsrc(0) := VECTOR_TMP_REG_MV.U 373 csBundle(2 * i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i).U 374 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 375 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 376 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.vp 377 csBundle(2 * i + 2).ctrl.srcType(2) := SrcType.vp 378 csBundle(2 * i + 2).ctrl.lsrc(0) := VECTOR_TMP_REG_MV.U 379 csBundle(2 * i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + (2 * i + 1).U 380 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 381 csBundle(2 * i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U 382 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 383 } 384 } 385 is(UopDivType.VEC_MASK) { 386 csBundle(0).ctrl.srcType(2) := SrcType.vp 387 csBundle(0).ctrl.lsrc(2) := ctrl_flow.instr(11, 7) 388 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 389 csBundle(0).ctrl.uopIdx := 0.U 390 for(i <- 1 until MAX_VLMUL) { 391 csBundle(i).ctrl.srcType(2) := SrcType.vp 392 csBundle(i).ctrl.lsrc(0) := ctrl_flow.instr(19, 15) + i.U 393 csBundle(i).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 394 csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 395 csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 396 csBundle(i).ctrl.uopIdx := i.U 397 } 398 csBundle(numOfUop - 1.U).ctrl.ldest := ctrl_flow.instr(11, 7) 399 } 400 is(UopDivType.VEC_MV_MASK) { 401 /* 402 FMV.D.X 403 */ 404 csBundle(0).ctrl.srcType(0) := SrcType.reg 405 csBundle(0).ctrl.srcType(1) := SrcType.imm 406 csBundle(0).ctrl.lsrc(1) := 0.U 407 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_MV.U 408 csBundle(0).ctrl.fuType := FuType.i2f 409 csBundle(0).ctrl.rfWen := false.B 410 csBundle(0).ctrl.fpWen := false.B 411 csBundle(0).ctrl.vecWen := true.B 412 csBundle(0).ctrl.fpu.isAddSub := false.B 413 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 414 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 415 csBundle(0).ctrl.fpu.fromInt := true.B 416 csBundle(0).ctrl.fpu.wflags := false.B 417 csBundle(0).ctrl.fpu.fpWen := false.B 418 csBundle(0).ctrl.fpu.div := false.B 419 csBundle(0).ctrl.fpu.sqrt := false.B 420 csBundle(0).ctrl.fpu.fcvt := false.B 421 //LMUL 422 csBundle(1).ctrl.srcType(0) := SrcType.vp 423 csBundle(1).ctrl.srcType(2) := SrcType.vp 424 csBundle(1).ctrl.lsrc(0) := VECTOR_TMP_REG_MV.U 425 csBundle(1).ctrl.lsrc(2) := ctrl_flow.instr(11, 7) 426 csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 427 csBundle(1).ctrl.uopIdx := 0.U 428 for (i <- 1 until MAX_VLMUL) { 429 csBundle(i + 1).ctrl.srcType(0) := SrcType.vp 430 csBundle(i + 1).ctrl.srcType(2) := SrcType.vp 431 csBundle(i + 1).ctrl.lsrc(0) := VECTOR_TMP_REG_MV.U 432 csBundle(i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U 433 csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 434 csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 435 csBundle(i + 1).ctrl.uopIdx := i.U 436 } 437 csBundle(numOfUop - 1.U).ctrl.ldest := ctrl_flow.instr(11,7) 438 } 439 } 440 441 //uops dispatch 442 val normal :: ext :: Nil = Enum(2) 443 val stateReg = RegInit(normal) 444 val uopRes = RegInit(0.U) 445 446 //readyFromRename Counter 447 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 448 449 switch(stateReg) { 450 is(normal) { 451 when(!io.validFromIBuf(0)) { 452 stateReg := normal 453 uopRes := 0.U 454 }.elsewhen((numOfUop > readyCounter) && (readyCounter =/= 0.U)){ 455 stateReg := ext 456 uopRes := numOfUop - readyCounter 457 }.otherwise { 458 stateReg := normal 459 uopRes := 0.U 460 } 461 } 462 is(ext) { 463 when(!io.validFromIBuf(0)) { 464 stateReg := normal 465 uopRes := 0.U 466 }.elsewhen(uopRes > readyCounter) { 467 stateReg := ext 468 uopRes := uopRes - readyCounter 469 }.otherwise { 470 stateReg := normal 471 uopRes := 0.U 472 } 473 } 474 } 475 476 for(i <- 0 until RenameWidth) { 477 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 478 (stateReg === normal) -> csBundle(i), 479 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 480 )) 481 } 482 483 484 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 485 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 486 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 487 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 488 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 489 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 490 notInfVec(0) := true.B 491 492 complexNum := 1.U 493 validToRename.map{ case dst => dst := false.B } 494 readyToIBuf .map{ case dst => dst := false.B } 495 switch(stateReg) { 496 is(normal) { 497 when(!io.validFromIBuf(0)) { 498 complexNum := 1.U 499 validToRename(0) := false.B 500 for (i <- 1 until RenameWidth) { 501 validToRename(i) := notInfVec(i - 1) && validSimple(i - 1) 502 } 503 readyToIBuf(0) := io.readyFromRename(0) 504 for(i <- 1 until DecodeWidth) { 505 readyToIBuf(i) := notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i) 506 } 507 }.elsewhen(numOfUop > readyCounter) { 508 complexNum := Mux(readyCounter === 0.U, 1.U, readyCounter) 509 for (i <- 0 until RenameWidth) { 510 validToRename(i) := Mux(readyCounter > i.U, true.B, false.B) 511 } 512 readyToIBuf.map{ case dst => dst := false.B } 513 }.otherwise { 514 complexNum := numOfUop 515 for (i <- 0 until RenameWidth) { 516 validToRename(i) := Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)) 517 } 518 readyToIBuf(0) := true.B 519 for (i <- 1 until DecodeWidth) { 520 readyToIBuf(i) := Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B) 521 } 522 } 523 } 524 is(ext) { 525 when(!io.validFromIBuf(0)) { 526 complexNum := 1.U 527 validToRename.map{ case dst => dst := false.B } 528 readyToIBuf.map{ case dst => dst := true.B } 529 }.elsewhen(uopRes > readyCounter) { 530 complexNum := Mux(readyCounter === 0.U, 1.U, readyCounter) 531 for (i <- 0 until RenameWidth) { 532 validToRename(i) := Mux(readyCounter > i.U, true.B, false.B) 533 } 534 readyToIBuf.map{ case dst => dst := false.B } 535 }.otherwise { 536 complexNum := uopRes 537 for (i <- 0 until RenameWidth) { 538 validToRename(i) := Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)) 539 } 540 readyToIBuf(0) := true.B 541 for (i <- 1 until DecodeWidth) { 542 readyToIBuf(i) := Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B) 543 } 544 } 545 } 546 } 547 548 io.deq.cf_ctrl := cf_ctrl 549 io.deq.isVset := isVset_u 550 io.deq.complexNum := complexNum 551 io.deq.validToRename := validToRename 552 io.deq.readyToIBuf := readyToIBuf 553 554} 555 556