1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.fu.vector.Bundles.VType 33import yunsuan.VpermType 34 35import scala.collection.Seq 36 37trait VectorConstants { 38 val MAX_VLMUL = 8 39 val FP_TMP_REG_MV = 32 40 val VECTOR_TMP_REG_LMUL = 32 // 32~38 -> 7 41 val VECTOR_VCONFIG = 39 42} 43 44class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 45 val enq = new Bundle { val staticInst = Input(new StaticInst) } 46 val vtype = Input(new VType) 47 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 48 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 49 val readyFromRename = Input(Vec(RenameWidth, Bool())) 50 val deq = new Bundle { 51 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 52 val isVset = Output(Bool()) 53 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 54 val validToRename = Output(Vec(RenameWidth, Bool())) 55 val complexNum = Output(UInt(3.W)) 56 } 57 val csrCtrl = Input(new CustomCSRCtrlIO) 58} 59 60/** 61 * @author zly 62 */ 63class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 64 val io = IO(new DecodeUnitCompIO) 65 66 val maxUopSize = MaxUopSize 67 //input bits 68 val staticInst = Wire(new StaticInst) 69 70 staticInst := io.enq.staticInst 71 72 val src1 = Cat(0.U(1.W), staticInst.instr(19, 15)) 73 val src2 = Cat(0.U(1.W), staticInst.instr(24, 20)) 74 val dest = Cat(0.U(1.W), staticInst.instr(11, 7)) 75 76 //output bits 77 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 78 val validToRename = Wire(Vec(RenameWidth, Bool())) 79 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 80 val complexNum = Wire(UInt(3.W)) 81 82 //output of DecodeUnit 83 val decodedInsts_u = Wire(new DecodedInst) 84 val isVset_u = Wire(Bool()) 85 86 //pre decode 87 val simple = Module(new DecodeUnit) 88 simple.io.enq.ctrlFlow := staticInst 89 simple.io.enq.vtype := io.vtype 90 simple.io.csrCtrl := io.csrCtrl 91 decodedInsts_u := simple.io.deq.decodedInst 92 isVset_u := simple.io.deq.decodedInst.isVset 93 when(isVset_u) { 94 when(dest === 0.U && src1 === 0.U) { 95 decodedInsts_u.fuOpType := VSETOpType.keepVl(simple.io.deq.decodedInst.fuOpType) 96 }.elsewhen(src1 === 0.U) { 97 decodedInsts_u.fuOpType := VSETOpType.setVlmax(simple.io.deq.decodedInst.fuOpType) 98 } 99 when(io.vtype.illegal){ 100 decodedInsts_u.flushPipe := true.B 101 } 102 } 103 //Type of uop Div 104 val typeOfDiv = decodedInsts_u.uopSplitType 105 106 //LMUL 107 val lmul = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(4.W), Array( 108 "b001".U -> 2.U, 109 "b010".U -> 4.U, 110 "b011".U -> 8.U 111 )) 112 val numOfUopVslide = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(log2Up(maxUopSize+1).W), Array( 113 "b001".U -> 3.U, 114 "b010".U -> 10.U, 115 "b011".U -> 36.U 116 )) 117 //number of uop 118 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxUopSize+1).W), Array( 119 UopSplitType.VEC_0XV -> 2.U, 120 UopSplitType.DIR -> Mux(dest =/= 0.U, 2.U, 121 Mux(src1 =/= 0.U, 1.U, 122 Mux(VSETOpType.isVsetvl(decodedInsts_u.fuOpType), 2.U, 1.U))), 123 UopSplitType.VEC_VVV -> lmul, 124 UopSplitType.VEC_EXT2 -> lmul, 125 UopSplitType.VEC_EXT4 -> lmul, 126 UopSplitType.VEC_EXT8 -> lmul, 127 UopSplitType.VEC_VVM -> lmul, 128 UopSplitType.VEC_VXM -> (lmul +& 1.U), 129 UopSplitType.VEC_VXV -> (lmul +& 1.U), 130 UopSplitType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 131 UopSplitType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 132 UopSplitType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 133 UopSplitType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 134 UopSplitType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 135 UopSplitType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 136 UopSplitType.VEC_SLIDE1UP -> (lmul +& 1.U), 137 UopSplitType.VEC_FSLIDE1UP -> lmul, 138 UopSplitType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 139 UopSplitType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 140 UopSplitType.VEC_VRED -> lmul, 141 UopSplitType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 142 UopSplitType.VEC_ISLIDEUP -> numOfUopVslide, 143 UopSplitType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 144 UopSplitType.VEC_ISLIDEDOWN -> numOfUopVslide, 145 UopSplitType.VEC_M0X -> (lmul +& 1.U), 146 UopSplitType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) -1.U), 147 UopSplitType.VEC_M0X_VFIRST -> 2.U, 148 )) 149 150 //uop div up to maxUopSize 151 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 152 csBundle.map { case dst => 153 dst := decodedInsts_u 154 dst.firstUop := false.B 155 dst.lastUop := false.B 156 } 157 158 csBundle(0).firstUop := true.B 159 csBundle(numOfUop - 1.U).lastUop := true.B 160 161 switch(typeOfDiv) { 162 is(UopSplitType.DIR) { 163 when(isVset_u) { 164 when(dest =/= 0.U) { 165 csBundle(0).fuType := FuType.vsetiwi.U 166 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInsts_u.fuOpType) 167 csBundle(0).flushPipe := false.B 168 csBundle(0).rfWen := true.B 169 csBundle(0).vecWen := false.B 170 csBundle(1).ldest := VECTOR_VCONFIG.U 171 }.elsewhen(src1 =/= 0.U) { 172 csBundle(0).ldest := VECTOR_VCONFIG.U 173 }.elsewhen(VSETOpType.isVsetvli(decodedInsts_u.fuOpType)) { 174 csBundle(0).fuType := FuType.vsetfwf.U 175 csBundle(0).srcType(0) := SrcType.vp 176 csBundle(0).lsrc(0) := VECTOR_VCONFIG.U 177 }.elsewhen(VSETOpType.isVsetvl(decodedInsts_u.fuOpType)) { 178 csBundle(0).srcType(0) := SrcType.reg 179 csBundle(0).srcType(1) := SrcType.imm 180 csBundle(0).lsrc(1) := 0.U 181 csBundle(0).ldest := FP_TMP_REG_MV.U 182 csBundle(0).fuType := FuType.i2f.U 183 csBundle(0).rfWen := false.B 184 csBundle(0).fpWen := true.B 185 csBundle(0).vecWen := false.B 186 csBundle(0).fpu.isAddSub := false.B 187 csBundle(0).fpu.typeTagIn := FPU.D 188 csBundle(0).fpu.typeTagOut := FPU.D 189 csBundle(0).fpu.fromInt := true.B 190 csBundle(0).fpu.wflags := false.B 191 csBundle(0).fpu.fpWen := true.B 192 csBundle(0).fpu.div := false.B 193 csBundle(0).fpu.sqrt := false.B 194 csBundle(0).fpu.fcvt := false.B 195 csBundle(0).flushPipe := false.B 196 csBundle(1).fuType := FuType.vsetfwf.U 197 csBundle(1).srcType(0) := SrcType.vp 198 csBundle(1).lsrc(0) := VECTOR_VCONFIG.U 199 csBundle(1).srcType(1) := SrcType.fp 200 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 201 csBundle(1).ldest := VECTOR_VCONFIG.U 202 } 203 } 204 } 205 is(UopSplitType.VEC_VVV) { 206 for (i <- 0 until MAX_VLMUL) { 207 csBundle(i).lsrc(0) := src1 + i.U 208 csBundle(i).lsrc(1) := src2 + i.U 209 csBundle(i).lsrc(2) := dest + i.U 210 csBundle(i).ldest := dest + i.U 211 csBundle(i).uopIdx := i.U 212 } 213 } 214 is(UopSplitType.VEC_EXT2) { 215 for (i <- 0 until MAX_VLMUL / 2) { 216 csBundle(2 * i).lsrc(1) := src2 + i.U 217 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 218 csBundle(2 * i).ldest := dest + (2 * i).U 219 csBundle(2 * i).uopIdx := (2 * i).U 220 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 221 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 222 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 223 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 224 } 225 } 226 is(UopSplitType.VEC_EXT4) { 227 for (i <- 0 until MAX_VLMUL / 4) { 228 csBundle(4 * i).lsrc(1) := src2 + i.U 229 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 230 csBundle(4 * i).ldest := dest + (4 * i).U 231 csBundle(4 * i).uopIdx := (4 * i).U 232 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 233 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 234 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 235 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 236 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 237 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 238 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 239 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 240 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 241 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 242 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 243 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 244 } 245 } 246 is(UopSplitType.VEC_EXT8) { 247 for (i <- 0 until MAX_VLMUL) { 248 csBundle(i).lsrc(1) := src2 249 csBundle(i).lsrc(2) := dest + i.U 250 csBundle(i).ldest := dest + i.U 251 csBundle(i).uopIdx := i.U 252 } 253 } 254 is(UopSplitType.VEC_0XV) { 255 /* 256 FMV.D.X 257 */ 258 csBundle(0).srcType(0) := SrcType.reg 259 csBundle(0).srcType(1) := SrcType.imm 260 csBundle(0).lsrc(1) := 0.U 261 csBundle(0).ldest := FP_TMP_REG_MV.U 262 csBundle(0).fuType := FuType.i2f.U 263 csBundle(0).rfWen := false.B 264 csBundle(0).fpWen := true.B 265 csBundle(0).vecWen := false.B 266 csBundle(0).fpu.isAddSub := false.B 267 csBundle(0).fpu.typeTagIn := FPU.D 268 csBundle(0).fpu.typeTagOut := FPU.D 269 csBundle(0).fpu.fromInt := true.B 270 csBundle(0).fpu.wflags := false.B 271 csBundle(0).fpu.fpWen := true.B 272 csBundle(0).fpu.div := false.B 273 csBundle(0).fpu.sqrt := false.B 274 csBundle(0).fpu.fcvt := false.B 275 /* 276 vfmv.s.f 277 */ 278 csBundle(1).srcType(0) := SrcType.fp 279 csBundle(1).srcType(1) := SrcType.vp 280 csBundle(1).srcType(2) := SrcType.vp 281 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 282 csBundle(1).lsrc(1) := 0.U 283 csBundle(1).lsrc(2) := dest 284 csBundle(1).ldest := dest 285 csBundle(1).fuType := FuType.vppu.U 286 csBundle(1).fuOpType := VpermType.dummy 287 csBundle(1).rfWen := false.B 288 csBundle(1).fpWen := false.B 289 csBundle(1).vecWen := true.B 290 } 291 is(UopSplitType.VEC_VXV) { 292 /* 293 FMV.D.X 294 */ 295 csBundle(0).srcType(0) := SrcType.reg 296 csBundle(0).srcType(1) := SrcType.imm 297 csBundle(0).lsrc(1) := 0.U 298 csBundle(0).ldest := FP_TMP_REG_MV.U 299 csBundle(0).fuType := FuType.i2f.U 300 csBundle(0).rfWen := false.B 301 csBundle(0).fpWen := true.B 302 csBundle(0).vecWen := false.B 303 csBundle(0).fpu.isAddSub := false.B 304 csBundle(0).fpu.typeTagIn := FPU.D 305 csBundle(0).fpu.typeTagOut := FPU.D 306 csBundle(0).fpu.fromInt := true.B 307 csBundle(0).fpu.wflags := false.B 308 csBundle(0).fpu.fpWen := true.B 309 csBundle(0).fpu.div := false.B 310 csBundle(0).fpu.sqrt := false.B 311 csBundle(0).fpu.fcvt := false.B 312 /* 313 LMUL 314 */ 315 for (i <- 0 until MAX_VLMUL) { 316 csBundle(i + 1).srcType(0) := SrcType.fp 317 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 318 csBundle(i + 1).lsrc(1) := src2 + i.U 319 csBundle(i + 1).lsrc(2) := dest + i.U 320 csBundle(i + 1).ldest := dest + i.U 321 csBundle(i + 1).uopIdx := i.U 322 } 323 } 324 is(UopSplitType.VEC_VVW) { 325 for (i <- 0 until MAX_VLMUL / 2) { 326 csBundle(2 * i).lsrc(0) := src1 + i.U 327 csBundle(2 * i).lsrc(1) := src2 + i.U 328 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 329 csBundle(2 * i).ldest := dest + (2 * i).U 330 csBundle(2 * i).uopIdx := (2 * i).U 331 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 332 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 333 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 334 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 335 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 336 } 337 } 338 is(UopSplitType.VEC_WVW) { 339 for (i <- 0 until MAX_VLMUL / 2) { 340 csBundle(2 * i).lsrc(0) := src1 + i.U 341 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 342 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 343 csBundle(2 * i).ldest := dest + (2 * i).U 344 csBundle(2 * i).uopIdx := (2 * i).U 345 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 346 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 347 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 348 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 349 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 350 } 351 } 352 is(UopSplitType.VEC_VXW) { 353 /* 354 FMV.D.X 355 */ 356 csBundle(0).srcType(0) := SrcType.reg 357 csBundle(0).srcType(1) := SrcType.imm 358 csBundle(0).lsrc(1) := 0.U 359 csBundle(0).ldest := FP_TMP_REG_MV.U 360 csBundle(0).fuType := FuType.i2f.U 361 csBundle(0).rfWen := false.B 362 csBundle(0).fpWen := true.B 363 csBundle(0).vecWen := false.B 364 csBundle(0).fpu.isAddSub := false.B 365 csBundle(0).fpu.typeTagIn := FPU.D 366 csBundle(0).fpu.typeTagOut := FPU.D 367 csBundle(0).fpu.fromInt := true.B 368 csBundle(0).fpu.wflags := false.B 369 csBundle(0).fpu.fpWen := true.B 370 csBundle(0).fpu.div := false.B 371 csBundle(0).fpu.sqrt := false.B 372 csBundle(0).fpu.fcvt := false.B 373 374 for (i <- 0 until MAX_VLMUL / 2) { 375 csBundle(2 * i + 1).srcType(0) := SrcType.fp 376 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 377 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 378 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 379 csBundle(2 * i + 1).ldest := dest + (2 * i).U 380 csBundle(2 * i + 1).uopIdx := (2 * i).U 381 csBundle(2 * i + 2).srcType(0) := SrcType.fp 382 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 383 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 384 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 385 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 386 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 387 } 388 } 389 is(UopSplitType.VEC_WXW) { 390 /* 391 FMV.D.X 392 */ 393 csBundle(0).srcType(0) := SrcType.reg 394 csBundle(0).srcType(1) := SrcType.imm 395 csBundle(0).lsrc(1) := 0.U 396 csBundle(0).ldest := FP_TMP_REG_MV.U 397 csBundle(0).fuType := FuType.i2f.U 398 csBundle(0).rfWen := false.B 399 csBundle(0).fpWen := true.B 400 csBundle(0).vecWen := false.B 401 csBundle(0).fpu.isAddSub := false.B 402 csBundle(0).fpu.typeTagIn := FPU.D 403 csBundle(0).fpu.typeTagOut := FPU.D 404 csBundle(0).fpu.fromInt := true.B 405 csBundle(0).fpu.wflags := false.B 406 csBundle(0).fpu.fpWen := true.B 407 csBundle(0).fpu.div := false.B 408 csBundle(0).fpu.sqrt := false.B 409 csBundle(0).fpu.fcvt := false.B 410 411 for (i <- 0 until MAX_VLMUL / 2) { 412 csBundle(2 * i + 1).srcType(0) := SrcType.fp 413 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 414 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 415 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 416 csBundle(2 * i + 1).ldest := dest + (2 * i).U 417 csBundle(2 * i + 1).uopIdx := (2 * i).U 418 csBundle(2 * i + 2).srcType(0) := SrcType.fp 419 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 420 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 421 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 422 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 423 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 424 } 425 } 426 is(UopSplitType.VEC_WVV) { 427 for (i <- 0 until MAX_VLMUL / 2) { 428 429 csBundle(2 * i).lsrc(0) := src1 + i.U 430 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 431 csBundle(2 * i).lsrc(2) := dest + i.U 432 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 433 csBundle(2 * i).uopIdx := (2 * i).U 434 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 435 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 436 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 437 csBundle(2 * i + 1).ldest := dest + i.U 438 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 439 } 440 } 441 is(UopSplitType.VEC_WXV) { 442 /* 443 FMV.D.X 444 */ 445 csBundle(0).srcType(0) := SrcType.reg 446 csBundle(0).srcType(1) := SrcType.imm 447 csBundle(0).lsrc(1) := 0.U 448 csBundle(0).ldest := FP_TMP_REG_MV.U 449 csBundle(0).fuType := FuType.i2f.U 450 csBundle(0).rfWen := false.B 451 csBundle(0).fpWen := true.B 452 csBundle(0).vecWen := false.B 453 csBundle(0).fpu.isAddSub := false.B 454 csBundle(0).fpu.typeTagIn := FPU.D 455 csBundle(0).fpu.typeTagOut := FPU.D 456 csBundle(0).fpu.fromInt := true.B 457 csBundle(0).fpu.wflags := false.B 458 csBundle(0).fpu.fpWen := true.B 459 csBundle(0).fpu.div := false.B 460 csBundle(0).fpu.sqrt := false.B 461 csBundle(0).fpu.fcvt := false.B 462 463 for (i <- 0 until MAX_VLMUL / 2) { 464 csBundle(2 * i + 1).srcType(0) := SrcType.fp 465 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 466 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 467 csBundle(2 * i + 1).lsrc(2) := dest + i.U 468 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 469 csBundle(2 * i + 1).uopIdx := (2 * i).U 470 csBundle(2 * i + 2).srcType(0) := SrcType.fp 471 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 472 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 473 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 474 csBundle(2 * i + 2).ldest := dest + i.U 475 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 476 } 477 } 478 is(UopSplitType.VEC_VVM) { 479 csBundle(0).lsrc(2) := dest 480 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 481 csBundle(0).uopIdx := 0.U 482 for(i <- 1 until MAX_VLMUL) { 483 csBundle(i).lsrc(0) := src1 + i.U 484 csBundle(i).lsrc(1) := src2 + i.U 485 csBundle(i).lsrc(2) := VECTOR_TMP_REG_LMUL.U 486 csBundle(i).ldest := VECTOR_TMP_REG_LMUL.U 487 csBundle(i).uopIdx := i.U 488 } 489 csBundle(numOfUop - 1.U).ldest := dest 490 } 491 is(UopSplitType.VEC_VXM) { 492 /* 493 FMV.D.X 494 */ 495 csBundle(0).srcType(0) := SrcType.reg 496 csBundle(0).srcType(1) := SrcType.imm 497 csBundle(0).lsrc(1) := 0.U 498 csBundle(0).ldest := FP_TMP_REG_MV.U 499 csBundle(0).fuType := FuType.i2f.U 500 csBundle(0).rfWen := false.B 501 csBundle(0).fpWen := true.B 502 csBundle(0).vecWen := false.B 503 csBundle(0).fpu.isAddSub := false.B 504 csBundle(0).fpu.typeTagIn := FPU.D 505 csBundle(0).fpu.typeTagOut := FPU.D 506 csBundle(0).fpu.fromInt := true.B 507 csBundle(0).fpu.wflags := false.B 508 csBundle(0).fpu.fpWen := true.B 509 csBundle(0).fpu.div := false.B 510 csBundle(0).fpu.sqrt := false.B 511 csBundle(0).fpu.fcvt := false.B 512 //LMUL 513 csBundle(1).srcType(0) := SrcType.fp 514 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 515 csBundle(1).lsrc(2) := dest 516 csBundle(1).ldest := VECTOR_TMP_REG_LMUL.U 517 csBundle(1).uopIdx := 0.U 518 for (i <- 1 until MAX_VLMUL) { 519 csBundle(i + 1).srcType(0) := SrcType.fp 520 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 521 csBundle(i + 1).lsrc(1) := src2 + i.U 522 csBundle(i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 523 csBundle(i + 1).ldest := VECTOR_TMP_REG_LMUL.U 524 csBundle(i + 1).uopIdx := i.U 525 } 526 csBundle(numOfUop - 1.U).ldest := dest 527 } 528 is(UopSplitType.VEC_SLIDE1UP) { 529 /* 530 FMV.D.X 531 */ 532 csBundle(0).srcType(0) := SrcType.reg 533 csBundle(0).srcType(1) := SrcType.imm 534 csBundle(0).lsrc(1) := 0.U 535 csBundle(0).ldest := FP_TMP_REG_MV.U 536 csBundle(0).fuType := FuType.i2f.U 537 csBundle(0).rfWen := false.B 538 csBundle(0).fpWen := true.B 539 csBundle(0).vecWen := false.B 540 csBundle(0).fpu.isAddSub := false.B 541 csBundle(0).fpu.typeTagIn := FPU.D 542 csBundle(0).fpu.typeTagOut := FPU.D 543 csBundle(0).fpu.fromInt := true.B 544 csBundle(0).fpu.wflags := false.B 545 csBundle(0).fpu.fpWen := true.B 546 csBundle(0).fpu.div := false.B 547 csBundle(0).fpu.sqrt := false.B 548 csBundle(0).fpu.fcvt := false.B 549 //LMUL 550 csBundle(1).srcType(0) := SrcType.fp 551 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 552 csBundle(1).lsrc(2) := dest 553 csBundle(1).ldest := dest 554 csBundle(1).uopIdx := 0.U 555 for (i <- 1 until MAX_VLMUL) { 556 csBundle(i + 1).srcType(0) := SrcType.vp 557 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 558 csBundle(i + 1).lsrc(1) := src2 + i.U 559 csBundle(i + 1).lsrc(2) := dest + i.U 560 csBundle(i + 1).ldest := dest + i.U 561 csBundle(i + 1).uopIdx := i.U 562 } 563 } 564 is(UopSplitType.VEC_FSLIDE1UP) { 565 //LMUL 566 csBundle(0).srcType(0) := SrcType.fp 567 csBundle(0).lsrc(0) := src1 568 csBundle(0).lsrc(1) := src2 569 csBundle(0).lsrc(2) := dest 570 csBundle(0).ldest := dest 571 csBundle(0).uopIdx := 0.U 572 for (i <- 1 until MAX_VLMUL) { 573 csBundle(i).srcType(0) := SrcType.vp 574 csBundle(i).lsrc(0) := src2 + (i - 1).U 575 csBundle(i).lsrc(1) := src2 + i.U 576 csBundle(i).lsrc(2) := dest + i.U 577 csBundle(i).ldest := dest + i.U 578 csBundle(i).uopIdx := i.U 579 } 580 } 581 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 582 /* 583 FMV.D.X 584 */ 585 csBundle(0).srcType(0) := SrcType.reg 586 csBundle(0).srcType(1) := SrcType.imm 587 csBundle(0).lsrc(1) := 0.U 588 csBundle(0).ldest := FP_TMP_REG_MV.U 589 csBundle(0).fuType := FuType.i2f.U 590 csBundle(0).rfWen := false.B 591 csBundle(0).fpWen := true.B 592 csBundle(0).vecWen := false.B 593 csBundle(0).fpu.isAddSub := false.B 594 csBundle(0).fpu.typeTagIn := FPU.D 595 csBundle(0).fpu.typeTagOut := FPU.D 596 csBundle(0).fpu.fromInt := true.B 597 csBundle(0).fpu.wflags := false.B 598 csBundle(0).fpu.fpWen := true.B 599 csBundle(0).fpu.div := false.B 600 csBundle(0).fpu.sqrt := false.B 601 csBundle(0).fpu.fcvt := false.B 602 //LMUL 603 for (i <- 0 until MAX_VLMUL) { 604 csBundle(2 * i + 1).srcType(0) := SrcType.vp 605 csBundle(2 * i + 1).srcType(1) := SrcType.vp 606 csBundle(2 * i + 1).lsrc(0) := src2 + (i+1).U 607 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 608 csBundle(2 * i + 1).lsrc(2) := dest + i.U 609 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 610 csBundle(2 * i + 1).uopIdx := (2 * i).U 611 if (2 * i + 2 < MAX_VLMUL * 2 ){ 612 csBundle(2 * i + 2).srcType(0) := SrcType.fp 613 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 614 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 615 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 616 csBundle(2 * i + 2).ldest := dest + i.U 617 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 618 } 619 } 620 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 621 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 622 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 623 } 624 is(UopSplitType.VEC_FSLIDE1DOWN) { 625 //LMUL 626 for (i <- 0 until MAX_VLMUL) { 627 csBundle(2 * i).srcType(0) := SrcType.vp 628 csBundle(2 * i).srcType(1) := SrcType.vp 629 csBundle(2 * i).lsrc(0) := src2 + (i+1).U 630 csBundle(2 * i).lsrc(1) := src2 + i.U 631 csBundle(2 * i).lsrc(2) := dest + i.U 632 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 633 csBundle(2 * i).uopIdx := (2 * i).U 634 csBundle(2 * i + 1).srcType(0) := SrcType.fp 635 csBundle(2 * i + 1).lsrc(0) := src1 636 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 637 csBundle(2 * i + 1).ldest := dest + i.U 638 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 639 } 640 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 641 csBundle(numOfUop - 1.U).lsrc(0) := src1 642 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 643 } 644 is(UopSplitType.VEC_VRED) { 645 when(simple.io.enq.vtype.vlmul === "b001".U){ 646 csBundle(0).srcType(2) := SrcType.DC 647 csBundle(0).lsrc(0) := src2 + 1.U 648 csBundle(0).lsrc(1) := src2 649 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 650 csBundle(0).uopIdx := 0.U 651 } 652 when(simple.io.enq.vtype.vlmul === "b010".U) { 653 csBundle(0).srcType(2) := SrcType.DC 654 csBundle(0).lsrc(0) := src2 + 1.U 655 csBundle(0).lsrc(1) := src2 656 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 657 csBundle(0).uopIdx := 0.U 658 659 csBundle(1).srcType(2) := SrcType.DC 660 csBundle(1).lsrc(0) := src2 + 3.U 661 csBundle(1).lsrc(1) := src2 + 2.U 662 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL+1).U 663 csBundle(1).uopIdx := 1.U 664 665 csBundle(2).srcType(2) := SrcType.DC 666 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL+1).U 667 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 668 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL+2).U 669 csBundle(2).uopIdx := 2.U 670 } 671 when(simple.io.enq.vtype.vlmul === "b011".U) { 672 for(i <- 0 until MAX_VLMUL){ 673 if(i < MAX_VLMUL - MAX_VLMUL/2){ 674 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 675 csBundle(i).lsrc(1) := src2 + (i * 2).U 676 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 677 } else if (i < MAX_VLMUL - MAX_VLMUL/4) { 678 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2 + 1).U 679 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2).U 680 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 681 }else if (i < MAX_VLMUL - MAX_VLMUL/8) { 682 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 683 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 684 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 685 } 686 csBundle(i).srcType(2) := SrcType.DC 687 csBundle(i).uopIdx := i.U 688 } 689 } 690 when (simple.io.enq.vtype.vlmul.orR()){ 691 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 692 csBundle(numOfUop - 1.U).lsrc(0) := src1 693 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 694 csBundle(numOfUop - 1.U).lsrc(2) := dest 695 csBundle(numOfUop - 1.U).ldest := dest 696 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 697 } 698 } 699 700 is(UopSplitType.VEC_SLIDEUP) { 701 // FMV.D.X 702 csBundle(0).srcType(0) := SrcType.reg 703 csBundle(0).srcType(1) := SrcType.imm 704 csBundle(0).lsrc(1) := 0.U 705 csBundle(0).ldest := FP_TMP_REG_MV.U 706 csBundle(0).fuType := FuType.i2f.U 707 csBundle(0).rfWen := false.B 708 csBundle(0).fpWen := true.B 709 csBundle(0).vecWen := false.B 710 csBundle(0).fpu.isAddSub := false.B 711 csBundle(0).fpu.typeTagIn := FPU.D 712 csBundle(0).fpu.typeTagOut := FPU.D 713 csBundle(0).fpu.fromInt := true.B 714 csBundle(0).fpu.wflags := false.B 715 csBundle(0).fpu.fpWen := true.B 716 csBundle(0).fpu.div := false.B 717 csBundle(0).fpu.sqrt := false.B 718 csBundle(0).fpu.fcvt := false.B 719 // LMUL 720 for(i <- 0 until MAX_VLMUL) 721 for(j <- 0 to i){ 722 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 723 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 724 csBundle(i*(i+1)/2+j+1).srcType(0) := SrcType.fp 725 csBundle(i*(i+1)/2+j+1).lsrc(0) := FP_TMP_REG_MV.U 726 csBundle(i*(i+1)/2+j+1).lsrc(1) := src2 + j.U 727 csBundle(i*(i+1)/2+j+1).lsrc(2) := old_vd 728 csBundle(i*(i+1)/2+j+1).ldest := vd 729 csBundle(i*(i+1)/2+j+1).uopIdx := (i*(i+1)/2+j).U 730 } 731 } 732 733 is(UopSplitType.VEC_ISLIDEUP) { 734 // LMUL 735 for(i <- 0 until MAX_VLMUL) 736 for(j <- 0 to i){ 737 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 738 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 739 csBundle(i*(i+1)/2+j).lsrc(1) := src2 + j.U 740 csBundle(i*(i+1)/2+j).lsrc(2) := old_vd 741 csBundle(i*(i+1)/2+j).ldest := vd 742 csBundle(i*(i+1)/2+j).uopIdx := (i*(i+1)/2+j).U 743 } 744 } 745 746 is(UopSplitType.VEC_SLIDEDOWN) { 747 // FMV.D.X 748 csBundle(0).srcType(0) := SrcType.reg 749 csBundle(0).srcType(1) := SrcType.imm 750 csBundle(0).lsrc(1) := 0.U 751 csBundle(0).ldest := FP_TMP_REG_MV.U 752 csBundle(0).fuType := FuType.i2f.U 753 csBundle(0).rfWen := false.B 754 csBundle(0).fpWen := true.B 755 csBundle(0).vecWen := false.B 756 csBundle(0).fpu.isAddSub := false.B 757 csBundle(0).fpu.typeTagIn := FPU.D 758 csBundle(0).fpu.typeTagOut := FPU.D 759 csBundle(0).fpu.fromInt := true.B 760 csBundle(0).fpu.wflags := false.B 761 csBundle(0).fpu.fpWen := true.B 762 csBundle(0).fpu.div := false.B 763 csBundle(0).fpu.sqrt := false.B 764 csBundle(0).fpu.fcvt := false.B 765 // LMUL 766 for(i <- 0 until MAX_VLMUL) 767 for(j <- (0 to i).reverse){ 768 when(i.U < lmul){ 769 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 770 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 771 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).srcType(0) := SrcType.fp 772 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(0) := FP_TMP_REG_MV.U 773 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(1) := src2 + lmul - 1.U - j.U 774 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(2) := old_vd 775 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ldest := vd 776 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).uopIdx := numOfUop-(i*(i+1)/2+i-j+2).U 777 } 778 } 779 } 780 781 is(UopSplitType.VEC_ISLIDEDOWN) { 782 // LMUL 783 for(i <- 0 until MAX_VLMUL) 784 for(j <- (0 to i).reverse){ 785 when(i.U < lmul){ 786 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 787 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 788 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(1) := src2 + lmul - 1.U - j.U 789 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(2) := old_vd 790 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ldest := vd 791 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).uopIdx := numOfUop-(i*(i+1)/2+i-j+1).U 792 } 793 } 794 } 795 796 is(UopSplitType.VEC_M0X) { 797 // LMUL 798 for (i <- 0 until MAX_VLMUL) { 799 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 800 val ldest = (VECTOR_TMP_REG_LMUL + i).U 801 csBundle(i).srcType(0) := srcType0 802 csBundle(i).srcType(1) := SrcType.vp 803 csBundle(i).rfWen := false.B 804 csBundle(i).vecWen := true.B 805 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 806 csBundle(i).lsrc(1) := src2 807 // csBundle(i).lsrc(2) := dest + i.U DontCare 808 csBundle(i).ldest := ldest 809 csBundle(i).uopIdx := i.U 810 } 811 csBundle(lmul-1.U).vecWen := false.B 812 csBundle(lmul-1.U).fpWen := true.B 813 csBundle(lmul-1.U).ldest := FP_TMP_REG_MV.U 814 // FMV_X_D 815 csBundle(lmul).srcType(0) := SrcType.fp 816 csBundle(lmul).srcType(1) := SrcType.imm 817 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 818 csBundle(lmul).lsrc(1) := 0.U 819 csBundle(lmul).ldest := dest 820 csBundle(lmul).fuType := FuType.fmisc.U 821 csBundle(lmul).rfWen := true.B 822 csBundle(lmul).fpWen := false.B 823 csBundle(lmul).vecWen := false.B 824 csBundle(lmul).fpu.isAddSub := false.B 825 csBundle(lmul).fpu.typeTagIn := FPU.D 826 csBundle(lmul).fpu.typeTagOut := FPU.D 827 csBundle(lmul).fpu.fromInt := false.B 828 csBundle(lmul).fpu.wflags := false.B 829 csBundle(lmul).fpu.fpWen := false.B 830 csBundle(lmul).fpu.div := false.B 831 csBundle(lmul).fpu.sqrt := false.B 832 csBundle(lmul).fpu.fcvt := false.B 833 } 834 835 is(UopSplitType.VEC_MVV) { 836 // LMUL 837 for (i <- 0 until MAX_VLMUL) { 838 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 839 csBundle(i*2+0).srcType(0) := srcType0 840 csBundle(i*2+0).srcType(1) := SrcType.vp 841 csBundle(i*2+0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 842 csBundle(i*2+0).lsrc(1) := src2 843 csBundle(i*2+0).lsrc(2) := dest + i.U 844 csBundle(i*2+0).ldest := dest + i.U 845 csBundle(i*2+0).uopIdx := (i*2+0).U 846 847 csBundle(i*2+1).srcType(0) := srcType0 848 csBundle(i*2+1).srcType(1) := SrcType.vp 849 csBundle(i*2+1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 850 csBundle(i*2+1).lsrc(1) := src2 851 // csBundle(i).lsrc(2) := dest + i.U DontCare 852 csBundle(i*2+1).ldest := (VECTOR_TMP_REG_LMUL + i).U 853 csBundle(i*2+1).uopIdx := (i*2+1).U 854 } 855 } 856 857 is(UopSplitType.VEC_M0X_VFIRST) { 858 // LMUL 859 csBundle(0).rfWen := false.B 860 csBundle(0).fpWen := true.B 861 csBundle(0).ldest := FP_TMP_REG_MV.U 862 // FMV_X_D 863 csBundle(1).srcType(0) := SrcType.fp 864 csBundle(1).srcType(1) := SrcType.imm 865 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 866 csBundle(1).lsrc(1) := 0.U 867 csBundle(1).ldest := dest 868 csBundle(1).fuType := FuType.fmisc.U 869 csBundle(1).rfWen := true.B 870 csBundle(1).fpWen := false.B 871 csBundle(1).vecWen := false.B 872 csBundle(1).fpu.isAddSub := false.B 873 csBundle(1).fpu.typeTagIn := FPU.D 874 csBundle(1).fpu.typeTagOut := FPU.D 875 csBundle(1).fpu.fromInt := false.B 876 csBundle(1).fpu.wflags := false.B 877 csBundle(1).fpu.fpWen := false.B 878 csBundle(1).fpu.div := false.B 879 csBundle(1).fpu.sqrt := false.B 880 csBundle(1).fpu.fcvt := false.B 881 } 882 } 883 884 //uops dispatch 885 val normal :: ext :: Nil = Enum(2) 886 val stateReg = RegInit(normal) 887 val uopRes = RegInit(0.U) 888 889 //readyFromRename Counter 890 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 891 892 switch(stateReg) { 893 is(normal) { 894 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 895 } 896 is(ext) { 897 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 898 } 899 } 900 901 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 902 val uopResJudge = Mux(stateReg === normal, 903 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 904 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 905 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 906 907 for(i <- 0 until RenameWidth) { 908 decodedInsts(i) := MuxCase(csBundle(i), Seq( 909 (stateReg === normal) -> csBundle(i), 910 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 911 )) 912 } 913 914 915 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 916 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 917 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 918 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 919 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 920 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 921 notInfVec(0) := true.B 922 923 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 924 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 925 1.U) 926 validToRename.zipWithIndex.foreach{ 927 case(dst, i) => 928 dst := MuxCase(false.B, Seq( 929 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 930 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 931 )) 932 } 933 934 readyToIBuf.zipWithIndex.foreach { 935 case (dst, i) => 936 dst := MuxCase(true.B, Seq( 937 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 938 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 939 )) 940 } 941 942 io.deq.decodedInsts := decodedInsts 943 io.deq.isVset := isVset_u 944 io.deq.complexNum := complexNum 945 io.deq.validToRename := validToRename 946 io.deq.readyToIBuf := readyToIBuf 947 948} 949