1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import freechips.rocketchip.rocket.Instructions._ 30import yunsuan.VpermType 31import scala.collection.Seq 32 33trait VectorConstants { 34 val MAX_VLMUL = 8 35 val INT_VCONFIG = 32 36 val FP_TMP_REG_MV = 32 37 val VECTOR_TMP_REG_LMUL = 32 // 32~38 -> 7 38} 39 40class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 41 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 42 val vconfig = Input(new VConfig) 43 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 44 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 45 val readyFromRename = Input(Vec(RenameWidth, Bool())) 46 val deq = new Bundle { 47 val cf_ctrl = Output(Vec(RenameWidth, new CfCtrl)) 48 val isVset = Output(Bool()) 49 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 50 val validToRename = Output(Vec(RenameWidth, Bool())) 51 val complexNum = Output(UInt(3.W)) 52 } 53 val csrCtrl = Input(new CustomCSRCtrlIO) 54} 55 56class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 57 val io = IO(new DecodeUnitCompIO) 58 //input bits 59 val ctrl_flow = Wire(new CtrlFlow) 60 ctrl_flow := io.enq.ctrl_flow 61 //output bits 62 val cf_ctrl = Wire(Vec(RenameWidth, new CfCtrl())) 63 val validToRename = Wire(Vec(RenameWidth, Bool())) 64 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 65 val complexNum = Wire(UInt(3.W)) 66 67 //output of DecodeUnit 68 val cf_ctrl_u = Wire(new CfCtrl) 69 val isVset_u = Wire(Bool()) 70 71 //pre decode 72 val simple = Module(new DecodeUnit) 73 simple.io.enq.ctrl_flow := ctrl_flow 74 simple.io.vconfig := io.vconfig 75 simple.io.csrCtrl := io.csrCtrl 76 cf_ctrl_u := simple.io.deq.cf_ctrl 77 isVset_u := simple.io.deq.isVset 78 79 //Type of uop Div 80 val typeOfDiv = cf_ctrl_u.ctrl.uopDivType 81 82 //LMUL 83 val lmul = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(4.W), Array( 84 "b001".U -> 2.U, 85 "b010".U -> 4.U, 86 "b011".U -> 8.U 87 )) 88 val numOfUopVslide = MuxLookup(simple.io.vconfig.vtype.vlmul, 1.U(log2Up(maxNumOfUop+1).W), Array( 89 "b001".U -> 3.U, 90 "b010".U -> 10.U, 91 "b011".U -> 36.U 92 )) 93 //number of uop 94 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxNumOfUop+1).W), Array( 95 UopDivType.VEC_0XV -> 2.U, 96 UopDivType.DIR -> 2.U, 97 UopDivType.VEC_VVV -> lmul, 98 UopDivType.VEC_EXT2 -> lmul, 99 UopDivType.VEC_EXT4 -> lmul, 100 UopDivType.VEC_EXT8 -> lmul, 101 UopDivType.VEC_VVM -> lmul, 102 UopDivType.VEC_VXM -> (lmul +& 1.U), 103 UopDivType.VEC_VXV -> (lmul +& 1.U), 104 UopDivType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 105 UopDivType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 106 UopDivType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 107 UopDivType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 108 UopDivType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 109 UopDivType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 110 UopDivType.VEC_SLIDE1UP -> (lmul +& 1.U), 111 UopDivType.VEC_FSLIDE1UP -> lmul, 112 UopDivType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 113 UopDivType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 114 UopDivType.VEC_VRED -> lmul, 115 UopDivType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 116 UopDivType.VEC_ISLIDEUP -> numOfUopVslide, 117 UopDivType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 118 UopDivType.VEC_ISLIDEDOWN -> numOfUopVslide, 119 UopDivType.VEC_0MX -> (lmul +& 1.U), 120 UopDivType.VEC_VMV -> (Cat(lmul, 0.U(1.W)) -1.U), 121 UopDivType.VEC_0MX_VFIRST -> 2.U, 122 )) 123 124 val src1 = Cat(0.U(1.W), ctrl_flow.instr(19, 15)) 125 val src2 = Cat(0.U(1.W), ctrl_flow.instr(24, 20)) 126 val dest = Cat(0.U(1.W), ctrl_flow.instr(11, 7 )) 127 128 //uop div up to maxNumOfUop 129 val csBundle = Wire(Vec(maxNumOfUop, new CfCtrl)) 130 csBundle.map { case dst => 131 dst := cf_ctrl_u 132 dst.ctrl.firstUop := false.B 133 dst.ctrl.lastUop := false.B 134 } 135 136 csBundle(0).ctrl.firstUop := true.B 137 csBundle(numOfUop - 1.U).ctrl.lastUop := true.B 138 139 switch(typeOfDiv) { 140 is(UopDivType.DIR) { 141 when(isVset_u) { 142 csBundle(0).ctrl.flushPipe := ALUOpType.isVsetvli(cf_ctrl_u.ctrl.fuOpType) && cf_ctrl_u.ctrl.lsrc(0).orR || ALUOpType.isVsetvl(cf_ctrl_u.ctrl.fuOpType) 143 csBundle(0).ctrl.fuOpType := ALUOpType.vsetExchange(cf_ctrl_u.ctrl.fuOpType) 144 csBundle(1).ctrl.ldest := INT_VCONFIG.U 145 csBundle(1).ctrl.flushPipe := false.B 146 } 147 } 148 is(UopDivType.VEC_VVV) { 149 for (i <- 0 until MAX_VLMUL) { 150 csBundle(i).ctrl.lsrc(0) := src1 + i.U 151 csBundle(i).ctrl.lsrc(1) := src2 + i.U 152 csBundle(i).ctrl.lsrc(2) := dest + i.U 153 csBundle(i).ctrl.ldest := dest + i.U 154 csBundle(i).ctrl.uopIdx := i.U 155 } 156 } 157 is(UopDivType.VEC_EXT2) { 158 for (i <- 0 until MAX_VLMUL / 2) { 159 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 160 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 161 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 162 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 163 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 164 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 165 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 166 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 167 } 168 } 169 is(UopDivType.VEC_EXT4) { 170 for (i <- 0 until MAX_VLMUL / 4) { 171 csBundle(4 * i).ctrl.lsrc(1) := src2 + i.U 172 csBundle(4 * i).ctrl.lsrc(2) := dest + (4 * i).U 173 csBundle(4 * i).ctrl.ldest := dest + (4 * i).U 174 csBundle(4 * i).ctrl.uopIdx := (4 * i).U 175 csBundle(4 * i + 1).ctrl.lsrc(1) := src2 + i.U 176 csBundle(4 * i + 1).ctrl.lsrc(2) := dest + (4 * i + 1).U 177 csBundle(4 * i + 1).ctrl.ldest := dest + (4 * i + 1).U 178 csBundle(4 * i + 1).ctrl.uopIdx := (4 * i + 1).U 179 csBundle(4 * i + 2).ctrl.lsrc(1) := src2 + i.U 180 csBundle(4 * i + 2).ctrl.lsrc(2) := dest + (4 * i + 2).U 181 csBundle(4 * i + 2).ctrl.ldest := dest + (4 * i + 2).U 182 csBundle(4 * i + 2).ctrl.uopIdx := (4 * i + 2).U 183 csBundle(4 * i + 3).ctrl.lsrc(1) := src2 + i.U 184 csBundle(4 * i + 3).ctrl.lsrc(2) := dest + (4 * i + 3).U 185 csBundle(4 * i + 3).ctrl.ldest := dest + (4 * i + 3).U 186 csBundle(4 * i + 3).ctrl.uopIdx := (4 * i + 3).U 187 } 188 } 189 is(UopDivType.VEC_EXT8) { 190 for (i <- 0 until MAX_VLMUL) { 191 csBundle(i).ctrl.lsrc(1) := src2 192 csBundle(i).ctrl.lsrc(2) := dest + i.U 193 csBundle(i).ctrl.ldest := dest + i.U 194 csBundle(i).ctrl.uopIdx := i.U 195 } 196 } 197 is(UopDivType.VEC_0XV) { 198 /* 199 FMV.D.X 200 */ 201 csBundle(0).ctrl.srcType(0) := SrcType.reg 202 csBundle(0).ctrl.srcType(1) := SrcType.imm 203 csBundle(0).ctrl.lsrc(1) := 0.U 204 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 205 csBundle(0).ctrl.fuType := FuType.i2f 206 csBundle(0).ctrl.rfWen := false.B 207 csBundle(0).ctrl.fpWen := true.B 208 csBundle(0).ctrl.vecWen := false.B 209 csBundle(0).ctrl.fpu.isAddSub := false.B 210 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 211 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 212 csBundle(0).ctrl.fpu.fromInt := true.B 213 csBundle(0).ctrl.fpu.wflags := false.B 214 csBundle(0).ctrl.fpu.fpWen := true.B 215 csBundle(0).ctrl.fpu.div := false.B 216 csBundle(0).ctrl.fpu.sqrt := false.B 217 csBundle(0).ctrl.fpu.fcvt := false.B 218 /* 219 vfmv.s.f 220 */ 221 csBundle(1).ctrl.srcType(0) := SrcType.fp 222 csBundle(1).ctrl.srcType(1) := SrcType.vp 223 csBundle(1).ctrl.srcType(2) := SrcType.vp 224 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 225 csBundle(1).ctrl.lsrc(1) := 0.U 226 csBundle(1).ctrl.lsrc(2) := dest 227 csBundle(1).ctrl.ldest := dest 228 csBundle(1).ctrl.fuType := FuType.vppu 229 csBundle(1).ctrl.fuOpType := VpermType.vfmv_s_f 230 csBundle(1).ctrl.rfWen := false.B 231 csBundle(1).ctrl.fpWen := false.B 232 csBundle(1).ctrl.vecWen := true.B 233 } 234 is(UopDivType.VEC_VXV) { 235 /* 236 FMV.D.X 237 */ 238 csBundle(0).ctrl.srcType(0) := SrcType.reg 239 csBundle(0).ctrl.srcType(1) := SrcType.imm 240 csBundle(0).ctrl.lsrc(1) := 0.U 241 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 242 csBundle(0).ctrl.fuType := FuType.i2f 243 csBundle(0).ctrl.rfWen := false.B 244 csBundle(0).ctrl.fpWen := true.B 245 csBundle(0).ctrl.vecWen := false.B 246 csBundle(0).ctrl.fpu.isAddSub := false.B 247 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 248 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 249 csBundle(0).ctrl.fpu.fromInt := true.B 250 csBundle(0).ctrl.fpu.wflags := false.B 251 csBundle(0).ctrl.fpu.fpWen := true.B 252 csBundle(0).ctrl.fpu.div := false.B 253 csBundle(0).ctrl.fpu.sqrt := false.B 254 csBundle(0).ctrl.fpu.fcvt := false.B 255 /* 256 LMUL 257 */ 258 for (i <- 0 until MAX_VLMUL) { 259 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 260 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 261 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 262 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 263 csBundle(i + 1).ctrl.ldest := dest + i.U 264 csBundle(i + 1).ctrl.uopIdx := i.U 265 } 266 } 267 is(UopDivType.VEC_VVW) { 268 for (i <- 0 until MAX_VLMUL / 2) { 269 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 270 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 271 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 272 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 273 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 274 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 275 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 276 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 277 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 278 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 279 } 280 } 281 is(UopDivType.VEC_WVW) { 282 for (i <- 0 until MAX_VLMUL / 2) { 283 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 284 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 285 csBundle(2 * i).ctrl.lsrc(2) := dest + (2 * i).U 286 csBundle(2 * i).ctrl.ldest := dest + (2 * i).U 287 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 288 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 289 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 290 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i + 1).U 291 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i + 1).U 292 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 293 } 294 } 295 is(UopDivType.VEC_VXW) { 296 /* 297 FMV.D.X 298 */ 299 csBundle(0).ctrl.srcType(0) := SrcType.reg 300 csBundle(0).ctrl.srcType(1) := SrcType.imm 301 csBundle(0).ctrl.lsrc(1) := 0.U 302 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 303 csBundle(0).ctrl.fuType := FuType.i2f 304 csBundle(0).ctrl.rfWen := false.B 305 csBundle(0).ctrl.fpWen := true.B 306 csBundle(0).ctrl.vecWen := false.B 307 csBundle(0).ctrl.fpu.isAddSub := false.B 308 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 309 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 310 csBundle(0).ctrl.fpu.fromInt := true.B 311 csBundle(0).ctrl.fpu.wflags := false.B 312 csBundle(0).ctrl.fpu.fpWen := true.B 313 csBundle(0).ctrl.fpu.div := false.B 314 csBundle(0).ctrl.fpu.sqrt := false.B 315 csBundle(0).ctrl.fpu.fcvt := false.B 316 317 for (i <- 0 until MAX_VLMUL / 2) { 318 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 319 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 320 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 321 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 322 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 323 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 324 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 325 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 326 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U 327 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 328 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 329 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 330 } 331 } 332 is(UopDivType.VEC_WXW) { 333 /* 334 FMV.D.X 335 */ 336 csBundle(0).ctrl.srcType(0) := SrcType.reg 337 csBundle(0).ctrl.srcType(1) := SrcType.imm 338 csBundle(0).ctrl.lsrc(1) := 0.U 339 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 340 csBundle(0).ctrl.fuType := FuType.i2f 341 csBundle(0).ctrl.rfWen := false.B 342 csBundle(0).ctrl.fpWen := true.B 343 csBundle(0).ctrl.vecWen := false.B 344 csBundle(0).ctrl.fpu.isAddSub := false.B 345 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 346 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 347 csBundle(0).ctrl.fpu.fromInt := true.B 348 csBundle(0).ctrl.fpu.wflags := false.B 349 csBundle(0).ctrl.fpu.fpWen := true.B 350 csBundle(0).ctrl.fpu.div := false.B 351 csBundle(0).ctrl.fpu.sqrt := false.B 352 csBundle(0).ctrl.fpu.fcvt := false.B 353 354 for (i <- 0 until MAX_VLMUL / 2) { 355 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 356 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 357 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 358 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + (2 * i).U 359 csBundle(2 * i + 1).ctrl.ldest := dest + (2 * i).U 360 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 361 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 362 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 363 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 364 csBundle(2 * i + 2).ctrl.lsrc(2) := dest + (2 * i + 1).U 365 csBundle(2 * i + 2).ctrl.ldest := dest + (2 * i + 1).U 366 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 367 } 368 } 369 is(UopDivType.VEC_WVV) { 370 for (i <- 0 until MAX_VLMUL / 2) { 371 372 csBundle(2 * i).ctrl.lsrc(0) := src1 + i.U 373 csBundle(2 * i).ctrl.lsrc(1) := src2 + (2 * i).U 374 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 375 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 376 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 377 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 + i.U 378 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i + 1).U 379 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 380 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 381 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 382 } 383 } 384 is(UopDivType.VEC_WXV) { 385 /* 386 FMV.D.X 387 */ 388 csBundle(0).ctrl.srcType(0) := SrcType.reg 389 csBundle(0).ctrl.srcType(1) := SrcType.imm 390 csBundle(0).ctrl.lsrc(1) := 0.U 391 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 392 csBundle(0).ctrl.fuType := FuType.i2f 393 csBundle(0).ctrl.rfWen := false.B 394 csBundle(0).ctrl.fpWen := true.B 395 csBundle(0).ctrl.vecWen := false.B 396 csBundle(0).ctrl.fpu.isAddSub := false.B 397 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 398 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 399 csBundle(0).ctrl.fpu.fromInt := true.B 400 csBundle(0).ctrl.fpu.wflags := false.B 401 csBundle(0).ctrl.fpu.fpWen := true.B 402 csBundle(0).ctrl.fpu.div := false.B 403 csBundle(0).ctrl.fpu.sqrt := false.B 404 csBundle(0).ctrl.fpu.fcvt := false.B 405 406 for (i <- 0 until MAX_VLMUL / 2) { 407 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 408 csBundle(2 * i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 409 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + (2 * i).U 410 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 411 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 412 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 413 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 414 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 415 csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + (2 * i + 1).U 416 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 417 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 418 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 419 } 420 } 421 is(UopDivType.VEC_VVM) { 422 csBundle(0).ctrl.lsrc(2) := dest 423 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 424 csBundle(0).ctrl.uopIdx := 0.U 425 for(i <- 1 until MAX_VLMUL) { 426 csBundle(i).ctrl.lsrc(0) := src1 + i.U 427 csBundle(i).ctrl.lsrc(1) := src2 + i.U 428 csBundle(i).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 429 csBundle(i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 430 csBundle(i).ctrl.uopIdx := i.U 431 } 432 csBundle(numOfUop - 1.U).ctrl.ldest := dest 433 } 434 is(UopDivType.VEC_VXM) { 435 /* 436 FMV.D.X 437 */ 438 csBundle(0).ctrl.srcType(0) := SrcType.reg 439 csBundle(0).ctrl.srcType(1) := SrcType.imm 440 csBundle(0).ctrl.lsrc(1) := 0.U 441 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 442 csBundle(0).ctrl.fuType := FuType.i2f 443 csBundle(0).ctrl.rfWen := false.B 444 csBundle(0).ctrl.fpWen := true.B 445 csBundle(0).ctrl.vecWen := false.B 446 csBundle(0).ctrl.fpu.isAddSub := false.B 447 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 448 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 449 csBundle(0).ctrl.fpu.fromInt := true.B 450 csBundle(0).ctrl.fpu.wflags := false.B 451 csBundle(0).ctrl.fpu.fpWen := true.B 452 csBundle(0).ctrl.fpu.div := false.B 453 csBundle(0).ctrl.fpu.sqrt := false.B 454 csBundle(0).ctrl.fpu.fcvt := false.B 455 //LMUL 456 csBundle(1).ctrl.srcType(0) := SrcType.fp 457 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 458 csBundle(1).ctrl.lsrc(2) := dest 459 csBundle(1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 460 csBundle(1).ctrl.uopIdx := 0.U 461 for (i <- 1 until MAX_VLMUL) { 462 csBundle(i + 1).ctrl.srcType(0) := SrcType.fp 463 csBundle(i + 1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 464 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 465 csBundle(i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 466 csBundle(i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 467 csBundle(i + 1).ctrl.uopIdx := i.U 468 } 469 csBundle(numOfUop - 1.U).ctrl.ldest := dest 470 } 471 is(UopDivType.VEC_SLIDE1UP) { 472 /* 473 FMV.D.X 474 */ 475 csBundle(0).ctrl.srcType(0) := SrcType.reg 476 csBundle(0).ctrl.srcType(1) := SrcType.imm 477 csBundle(0).ctrl.lsrc(1) := 0.U 478 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 479 csBundle(0).ctrl.fuType := FuType.i2f 480 csBundle(0).ctrl.rfWen := false.B 481 csBundle(0).ctrl.fpWen := true.B 482 csBundle(0).ctrl.vecWen := false.B 483 csBundle(0).ctrl.fpu.isAddSub := false.B 484 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 485 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 486 csBundle(0).ctrl.fpu.fromInt := true.B 487 csBundle(0).ctrl.fpu.wflags := false.B 488 csBundle(0).ctrl.fpu.fpWen := true.B 489 csBundle(0).ctrl.fpu.div := false.B 490 csBundle(0).ctrl.fpu.sqrt := false.B 491 csBundle(0).ctrl.fpu.fcvt := false.B 492 //LMUL 493 csBundle(1).ctrl.srcType(0) := SrcType.fp 494 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 495 csBundle(1).ctrl.lsrc(2) := dest 496 csBundle(1).ctrl.ldest := dest 497 csBundle(1).ctrl.uopIdx := 0.U 498 for (i <- 1 until MAX_VLMUL) { 499 csBundle(i + 1).ctrl.srcType(0) := SrcType.vp 500 csBundle(i + 1).ctrl.lsrc(0) := src2 + (i - 1).U 501 csBundle(i + 1).ctrl.lsrc(1) := src2 + i.U 502 csBundle(i + 1).ctrl.lsrc(2) := dest + i.U 503 csBundle(i + 1).ctrl.ldest := dest + i.U 504 csBundle(i + 1).ctrl.uopIdx := i.U 505 } 506 } 507 is(UopDivType.VEC_FSLIDE1UP) { 508 //LMUL 509 csBundle(0).ctrl.srcType(0) := SrcType.fp 510 csBundle(0).ctrl.lsrc(0) := src1 511 csBundle(0).ctrl.lsrc(1) := src2 512 csBundle(0).ctrl.lsrc(2) := dest 513 csBundle(0).ctrl.ldest := dest 514 csBundle(0).ctrl.uopIdx := 0.U 515 for (i <- 1 until MAX_VLMUL) { 516 csBundle(i).ctrl.srcType(0) := SrcType.vp 517 csBundle(i).ctrl.lsrc(0) := src2 + (i - 1).U 518 csBundle(i).ctrl.lsrc(1) := src2 + i.U 519 csBundle(i).ctrl.lsrc(2) := dest + i.U 520 csBundle(i).ctrl.ldest := dest + i.U 521 csBundle(i).ctrl.uopIdx := i.U 522 } 523 } 524 is(UopDivType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 525 /* 526 FMV.D.X 527 */ 528 csBundle(0).ctrl.srcType(0) := SrcType.reg 529 csBundle(0).ctrl.srcType(1) := SrcType.imm 530 csBundle(0).ctrl.lsrc(1) := 0.U 531 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 532 csBundle(0).ctrl.fuType := FuType.i2f 533 csBundle(0).ctrl.rfWen := false.B 534 csBundle(0).ctrl.fpWen := true.B 535 csBundle(0).ctrl.vecWen := false.B 536 csBundle(0).ctrl.fpu.isAddSub := false.B 537 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 538 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 539 csBundle(0).ctrl.fpu.fromInt := true.B 540 csBundle(0).ctrl.fpu.wflags := false.B 541 csBundle(0).ctrl.fpu.fpWen := true.B 542 csBundle(0).ctrl.fpu.div := false.B 543 csBundle(0).ctrl.fpu.sqrt := false.B 544 csBundle(0).ctrl.fpu.fcvt := false.B 545 //LMUL 546 for (i <- 0 until MAX_VLMUL) { 547 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.vp 548 csBundle(2 * i + 1).ctrl.srcType(1) := SrcType.vp 549 csBundle(2 * i + 1).ctrl.lsrc(0) := src2 + (i+1).U 550 csBundle(2 * i + 1).ctrl.lsrc(1) := src2 + i.U 551 csBundle(2 * i + 1).ctrl.lsrc(2) := dest + i.U 552 csBundle(2 * i + 1).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 553 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i).U 554 if (2 * i + 2 < MAX_VLMUL * 2 ){ 555 csBundle(2 * i + 2).ctrl.srcType(0) := SrcType.fp 556 csBundle(2 * i + 2).ctrl.lsrc(0) := FP_TMP_REG_MV.U 557 // csBundle(2 * i + 2).ctrl.lsrc(1) := src2 + i.U // DontCare 558 csBundle(2 * i + 2).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 559 csBundle(2 * i + 2).ctrl.ldest := dest + i.U 560 csBundle(2 * i + 2).ctrl.uopIdx := (2 * i + 1).U 561 } 562 } 563 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 564 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := FP_TMP_REG_MV.U 565 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 566 } 567 is(UopDivType.VEC_FSLIDE1DOWN) { 568 //LMUL 569 for (i <- 0 until MAX_VLMUL) { 570 csBundle(2 * i).ctrl.srcType(0) := SrcType.vp 571 csBundle(2 * i).ctrl.srcType(1) := SrcType.vp 572 csBundle(2 * i).ctrl.lsrc(0) := src2 + (i+1).U 573 csBundle(2 * i).ctrl.lsrc(1) := src2 + i.U 574 csBundle(2 * i).ctrl.lsrc(2) := dest + i.U 575 csBundle(2 * i).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 576 csBundle(2 * i).ctrl.uopIdx := (2 * i).U 577 csBundle(2 * i + 1).ctrl.srcType(0) := SrcType.fp 578 csBundle(2 * i + 1).ctrl.lsrc(0) := src1 579 csBundle(2 * i + 1).ctrl.lsrc(2) := VECTOR_TMP_REG_LMUL.U 580 csBundle(2 * i + 1).ctrl.ldest := dest + i.U 581 csBundle(2 * i + 1).ctrl.uopIdx := (2 * i + 1).U 582 } 583 csBundle(numOfUop - 1.U).ctrl.srcType(0) := SrcType.fp 584 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1 585 csBundle(numOfUop - 1.U).ctrl.ldest := dest + lmul - 1.U 586 } 587 is(UopDivType.VEC_VRED) { 588 when(simple.io.vconfig.vtype.vlmul === "b001".U){ 589 csBundle(0).ctrl.srcType(2) := SrcType.DC 590 csBundle(0).ctrl.lsrc(0) := src2 + 1.U 591 csBundle(0).ctrl.lsrc(1) := src2 592 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 593 csBundle(0).ctrl.uopIdx := 0.U 594 } 595 when(simple.io.vconfig.vtype.vlmul === "b010".U) { 596 csBundle(0).ctrl.srcType(2) := SrcType.DC 597 csBundle(0).ctrl.lsrc(0) := src2 + 1.U 598 csBundle(0).ctrl.lsrc(1) := src2 599 csBundle(0).ctrl.ldest := VECTOR_TMP_REG_LMUL.U 600 csBundle(0).ctrl.uopIdx := 0.U 601 602 csBundle(1).ctrl.srcType(2) := SrcType.DC 603 csBundle(1).ctrl.lsrc(0) := src2 + 3.U 604 csBundle(1).ctrl.lsrc(1) := src2 + 2.U 605 csBundle(1).ctrl.ldest := (VECTOR_TMP_REG_LMUL+1).U 606 csBundle(1).ctrl.uopIdx := 1.U 607 608 csBundle(2).ctrl.srcType(2) := SrcType.DC 609 csBundle(2).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL+1).U 610 csBundle(2).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U 611 csBundle(2).ctrl.ldest := (VECTOR_TMP_REG_LMUL+2).U 612 csBundle(2).ctrl.uopIdx := 2.U 613 } 614 when(simple.io.vconfig.vtype.vlmul === "b011".U) { 615 for(i <- 0 until MAX_VLMUL){ 616 if(i < MAX_VLMUL - MAX_VLMUL/2){ 617 csBundle(i).ctrl.lsrc(0) := src2 + (i * 2 + 1).U 618 csBundle(i).ctrl.lsrc(1) := src2 + (i * 2).U 619 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 620 } else if (i < MAX_VLMUL - MAX_VLMUL/4) { 621 csBundle(i).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2 + 1).U 622 csBundle(i).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2).U 623 csBundle(i).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 624 }else if (i < MAX_VLMUL - MAX_VLMUL/8) { 625 csBundle(6).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 626 csBundle(6).ctrl.lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 627 csBundle(6).ctrl.ldest := (VECTOR_TMP_REG_LMUL + 6).U 628 } 629 csBundle(i).ctrl.srcType(2) := SrcType.DC 630 csBundle(i).ctrl.uopIdx := i.U 631 } 632 } 633 when (simple.io.vconfig.vtype.vlmul.orR()){ 634 csBundle(numOfUop - 1.U).ctrl.srcType(2) := SrcType.vp 635 csBundle(numOfUop - 1.U).ctrl.lsrc(0) := src1 636 csBundle(numOfUop - 1.U).ctrl.lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 637 csBundle(numOfUop - 1.U).ctrl.lsrc(2) := dest 638 csBundle(numOfUop - 1.U).ctrl.ldest := dest 639 csBundle(numOfUop - 1.U).ctrl.uopIdx := numOfUop - 1.U 640 } 641 } 642 643 is(UopDivType.VEC_SLIDEUP) { 644 // FMV.D.X 645 csBundle(0).ctrl.srcType(0) := SrcType.reg 646 csBundle(0).ctrl.srcType(1) := SrcType.imm 647 csBundle(0).ctrl.lsrc(1) := 0.U 648 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 649 csBundle(0).ctrl.fuType := FuType.i2f 650 csBundle(0).ctrl.rfWen := false.B 651 csBundle(0).ctrl.fpWen := true.B 652 csBundle(0).ctrl.vecWen := false.B 653 csBundle(0).ctrl.fpu.isAddSub := false.B 654 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 655 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 656 csBundle(0).ctrl.fpu.fromInt := true.B 657 csBundle(0).ctrl.fpu.wflags := false.B 658 csBundle(0).ctrl.fpu.fpWen := true.B 659 csBundle(0).ctrl.fpu.div := false.B 660 csBundle(0).ctrl.fpu.sqrt := false.B 661 csBundle(0).ctrl.fpu.fcvt := false.B 662 // LMUL 663 for(i <- 0 until MAX_VLMUL) 664 for(j <- 0 to i){ 665 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 666 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 667 csBundle(i*(i+1)/2+j+1).ctrl.srcType(0) := SrcType.fp 668 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 669 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(1) := src2 + j.U 670 csBundle(i*(i+1)/2+j+1).ctrl.lsrc(2) := old_vd 671 csBundle(i*(i+1)/2+j+1).ctrl.ldest := vd 672 csBundle(i*(i+1)/2+j+1).ctrl.uopIdx := (i*(i+1)/2+j).U 673 } 674 } 675 676 is(UopDivType.VEC_ISLIDEUP) { 677 // LMUL 678 for(i <- 0 until MAX_VLMUL) 679 for(j <- 0 to i){ 680 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 681 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 682 csBundle(i*(i+1)/2+j).ctrl.lsrc(1) := src2 + j.U 683 csBundle(i*(i+1)/2+j).ctrl.lsrc(2) := old_vd 684 csBundle(i*(i+1)/2+j).ctrl.ldest := vd 685 csBundle(i*(i+1)/2+j).ctrl.uopIdx := (i*(i+1)/2+j).U 686 } 687 } 688 689 is(UopDivType.VEC_SLIDEDOWN) { 690 // FMV.D.X 691 csBundle(0).ctrl.srcType(0) := SrcType.reg 692 csBundle(0).ctrl.srcType(1) := SrcType.imm 693 csBundle(0).ctrl.lsrc(1) := 0.U 694 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 695 csBundle(0).ctrl.fuType := FuType.i2f 696 csBundle(0).ctrl.rfWen := false.B 697 csBundle(0).ctrl.fpWen := true.B 698 csBundle(0).ctrl.vecWen := false.B 699 csBundle(0).ctrl.fpu.isAddSub := false.B 700 csBundle(0).ctrl.fpu.typeTagIn := FPU.D 701 csBundle(0).ctrl.fpu.typeTagOut := FPU.D 702 csBundle(0).ctrl.fpu.fromInt := true.B 703 csBundle(0).ctrl.fpu.wflags := false.B 704 csBundle(0).ctrl.fpu.fpWen := true.B 705 csBundle(0).ctrl.fpu.div := false.B 706 csBundle(0).ctrl.fpu.sqrt := false.B 707 csBundle(0).ctrl.fpu.fcvt := false.B 708 // LMUL 709 for(i <- 0 until MAX_VLMUL) 710 for(j <- (0 to i).reverse){ 711 when(i.U < lmul){ 712 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 713 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 714 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.srcType(0) := SrcType.fp 715 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(0) := FP_TMP_REG_MV.U 716 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(1) := src2 + lmul - 1.U - j.U 717 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(2) := old_vd 718 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.ldest := vd 719 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.uopIdx := numOfUop-(i*(i+1)/2+i-j+2).U 720 } 721 } 722 } 723 724 is(UopDivType.VEC_ISLIDEDOWN) { 725 // LMUL 726 for(i <- 0 until MAX_VLMUL) 727 for(j <- (0 to i).reverse){ 728 when(i.U < lmul){ 729 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 730 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 731 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(1) := src2 + lmul - 1.U - j.U 732 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.lsrc(2) := old_vd 733 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.ldest := vd 734 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ctrl.uopIdx := numOfUop-(i*(i+1)/2+i-j+1).U 735 } 736 } 737 } 738 739 is(UopDivType.VEC_0MX) { 740 // LMUL 741 for (i <- 0 until MAX_VLMUL) { 742 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 743 val ldest = (VECTOR_TMP_REG_LMUL + i).U 744 csBundle(i).ctrl.srcType(0) := srcType0 745 csBundle(i).ctrl.srcType(1) := SrcType.vp 746 csBundle(i).ctrl.rfWen := false.B 747 csBundle(i).ctrl.vecWen := true.B 748 csBundle(i).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 749 csBundle(i).ctrl.lsrc(1) := src2 750 // csBundle(i).ctrl.lsrc(2) := dest + i.U DontCare 751 csBundle(i).ctrl.ldest := ldest 752 csBundle(i).ctrl.uopIdx := i.U 753 } 754 csBundle(lmul-1.U).ctrl.vecWen := false.B 755 csBundle(lmul-1.U).ctrl.fpWen := true.B 756 csBundle(lmul-1.U).ctrl.ldest := FP_TMP_REG_MV.U 757 // FMV_X_D 758 csBundle(lmul).ctrl.srcType(0) := SrcType.fp 759 csBundle(lmul).ctrl.srcType(1) := SrcType.imm 760 csBundle(lmul).ctrl.lsrc(0) := FP_TMP_REG_MV.U 761 csBundle(lmul).ctrl.lsrc(1) := 0.U 762 csBundle(lmul).ctrl.ldest := dest 763 csBundle(lmul).ctrl.fuType := FuType.fmisc 764 csBundle(lmul).ctrl.rfWen := true.B 765 csBundle(lmul).ctrl.fpWen := false.B 766 csBundle(lmul).ctrl.vecWen := false.B 767 csBundle(lmul).ctrl.fpu.isAddSub := false.B 768 csBundle(lmul).ctrl.fpu.typeTagIn := FPU.D 769 csBundle(lmul).ctrl.fpu.typeTagOut := FPU.D 770 csBundle(lmul).ctrl.fpu.fromInt := false.B 771 csBundle(lmul).ctrl.fpu.wflags := false.B 772 csBundle(lmul).ctrl.fpu.fpWen := false.B 773 csBundle(lmul).ctrl.fpu.div := false.B 774 csBundle(lmul).ctrl.fpu.sqrt := false.B 775 csBundle(lmul).ctrl.fpu.fcvt := false.B 776 } 777 778 is(UopDivType.VEC_VMV) { 779 // LMUL 780 for (i <- 0 until MAX_VLMUL) { 781 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 782 csBundle(i*2+0).ctrl.srcType(0) := srcType0 783 csBundle(i*2+0).ctrl.srcType(1) := SrcType.vp 784 csBundle(i*2+0).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 785 csBundle(i*2+0).ctrl.lsrc(1) := src2 786 csBundle(i*2+0).ctrl.lsrc(2) := dest + i.U 787 csBundle(i*2+0).ctrl.ldest := dest + i.U 788 csBundle(i*2+0).ctrl.uopIdx := (i*2+0).U 789 790 csBundle(i*2+1).ctrl.srcType(0) := srcType0 791 csBundle(i*2+1).ctrl.srcType(1) := SrcType.vp 792 csBundle(i*2+1).ctrl.lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 793 csBundle(i*2+1).ctrl.lsrc(1) := src2 794 // csBundle(i).ctrl.lsrc(2) := dest + i.U DontCare 795 csBundle(i*2+1).ctrl.ldest := (VECTOR_TMP_REG_LMUL + i).U 796 csBundle(i*2+1).ctrl.uopIdx := (i*2+1).U 797 } 798 } 799 800 is(UopDivType.VEC_0MX_VFIRST) { 801 // LMUL 802 csBundle(0).ctrl.rfWen := false.B 803 csBundle(0).ctrl.fpWen := true.B 804 csBundle(0).ctrl.ldest := FP_TMP_REG_MV.U 805 // FMV_X_D 806 csBundle(1).ctrl.srcType(0) := SrcType.fp 807 csBundle(1).ctrl.srcType(1) := SrcType.imm 808 csBundle(1).ctrl.lsrc(0) := FP_TMP_REG_MV.U 809 csBundle(1).ctrl.lsrc(1) := 0.U 810 csBundle(1).ctrl.ldest := dest 811 csBundle(1).ctrl.fuType := FuType.fmisc 812 csBundle(1).ctrl.rfWen := true.B 813 csBundle(1).ctrl.fpWen := false.B 814 csBundle(1).ctrl.vecWen := false.B 815 csBundle(1).ctrl.fpu.isAddSub := false.B 816 csBundle(1).ctrl.fpu.typeTagIn := FPU.D 817 csBundle(1).ctrl.fpu.typeTagOut := FPU.D 818 csBundle(1).ctrl.fpu.fromInt := false.B 819 csBundle(1).ctrl.fpu.wflags := false.B 820 csBundle(1).ctrl.fpu.fpWen := false.B 821 csBundle(1).ctrl.fpu.div := false.B 822 csBundle(1).ctrl.fpu.sqrt := false.B 823 csBundle(1).ctrl.fpu.fcvt := false.B 824 } 825 } 826 827 //uops dispatch 828 val normal :: ext :: Nil = Enum(2) 829 val stateReg = RegInit(normal) 830 val uopRes = RegInit(0.U) 831 832 //readyFromRename Counter 833 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 834 835 switch(stateReg) { 836 is(normal) { 837 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 838 } 839 is(ext) { 840 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 841 } 842 } 843 844 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 845 val uopResJudge = Mux(stateReg === normal, 846 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 847 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 848 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 849 850 for(i <- 0 until RenameWidth) { 851 cf_ctrl(i) := MuxCase(csBundle(i), Seq( 852 (stateReg === normal) -> csBundle(i), 853 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxNumOfUop.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxNumOfUop - 1)) 854 )) 855 } 856 857 858 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 859 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 860 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 861 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 862 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 863 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 864 notInfVec(0) := true.B 865 866 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 867 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 868 1.U) 869 validToRename.zipWithIndex.foreach{ 870 case(dst, i) => 871 dst := MuxCase(false.B, Seq( 872 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 873 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 874 )) 875 } 876 877 readyToIBuf.zipWithIndex.foreach { 878 case (dst, i) => 879 dst := MuxCase(true.B, Seq( 880 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 881 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 882 )) 883 } 884 885 io.deq.cf_ctrl := cf_ctrl 886 io.deq.isVset := isVset_u 887 io.deq.complexNum := complexNum 888 io.deq.validToRename := validToRename 889 io.deq.readyToIBuf := readyToIBuf 890 891} 892 893