1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import freechips.rocketchip.rocket.Instructions._ 29 30/** 31 * Abstract trait giving defaults and other relevant values to different Decode constants/ 32 */ 33abstract trait DecodeConstants { 34 // This X should be used only in 1-bit signal. Otherwise, use BitPat("b???") to align with the width of UInt. 35 def X = BitPat("b0") 36 def N = BitPat("b0") 37 def Y = BitPat("b1") 38 def T = true 39 def F = false 40 41 def decodeDefault: List[BitPat] = { // illegal instruction 42 // srcType(0) srcType(1) srcType(2) fuType fuOpType rfWen 43 // | | | | | | fpWen 44 // | | | | | | | vecWen 45 // | | | | | | | | isXSTrap 46 // | | | | | | | | | noSpecExec 47 // | | | | | | | | | | blockBackward 48 // | | | | | | | | | | | flushPipe 49 // | | | | | | | | | | | | uopDivType 50 // | | | | | | | | | | | | | selImm 51 List(SrcType.X, SrcType.X, SrcType.X, FuType.X, FuOpType.X, N, N, N, N, N, N, N, UopDivType.X, SelImm.INVALID_INSTR) 52 } // Use SelImm to indicate invalid instr 53 54 val decodeArray: Array[(BitPat, XSDecodeBase)] 55 final def table: Array[(BitPat, List[BitPat])] = decodeArray.map(x => (x._1, x._2.generate())) 56} 57 58trait DecodeUnitConstants 59{ 60 // abstract out instruction decode magic numbers 61 val RD_MSB = 11 62 val RD_LSB = 7 63 val RS1_MSB = 19 64 val RS1_LSB = 15 65 val RS2_MSB = 24 66 val RS2_LSB = 20 67 val RS3_MSB = 31 68 val RS3_LSB = 27 69} 70 71/** 72 * Decoded control signals 73 * See xiangshan/package.scala, xiangshan/backend/package.scala, Bundle.scala 74 */ 75 76abstract class XSDecodeBase { 77 def X = BitPat("b?") 78 def N = BitPat("b0") 79 def Y = BitPat("b1") 80 def T = true 81 def F = false 82 def generate() : List[BitPat] 83} 84 85case class XSDecode( 86 src1: BitPat, src2: BitPat, src3: BitPat, 87 fu: BitPat, fuOp: BitPat, selImm: BitPat, 88 uopDivType: BitPat = UopDivType.X, 89 xWen: Boolean = false, 90 fWen: Boolean = false, 91 vWen: Boolean = false, 92 mWen: Boolean = false, 93 xsTrap: Boolean = false, 94 noSpec: Boolean = false, 95 blockBack: Boolean = false, 96 flushPipe: Boolean = false, 97) extends XSDecodeBase { 98 def generate() : List[BitPat] = { 99 List (src1, src2, src3, fu, fuOp, xWen.B, fWen.B, (vWen || mWen).B, xsTrap.B, noSpec.B, blockBack.B, flushPipe.B, uopDivType, selImm) 100 } 101} 102 103case class FDecode( 104 src1: BitPat, src2: BitPat, src3: BitPat, 105 fu: BitPat, fuOp: BitPat, selImm: BitPat = SelImm.X, 106 uopDivType: BitPat = UopDivType.X, 107 xWen: Boolean = false, 108 fWen: Boolean = false, 109 vWen: Boolean = false, 110 mWen: Boolean = false, 111 xsTrap: Boolean = false, 112 noSpec: Boolean = false, 113 blockBack: Boolean = false, 114 flushPipe: Boolean = false, 115) extends XSDecodeBase { 116 def generate() : List[BitPat] = { 117 XSDecode(src1, src2, src3, fu, fuOp, uopDivType, selImm, xWen, fWen, vWen, mWen, xsTrap, noSpec, blockBack, flushPipe).generate() 118 } 119} 120 121/** 122 * Decode constants for RV64 123 */ 124object X64Decode extends DecodeConstants { 125 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 126 LD -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld , SelImm.IMM_I, xWen = T), 127 LWU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lwu , SelImm.IMM_I, xWen = T), 128 SD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sd , SelImm.IMM_S ), 129 130 SLLI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sll , SelImm.IMM_I, xWen = T), 131 SRLI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srl , SelImm.IMM_I, xWen = T), 132 SRAI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sra , SelImm.IMM_I, xWen = T), 133 134 ADDIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.addw, SelImm.IMM_I, xWen = T), 135 SLLIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sllw, SelImm.IMM_I, xWen = T), 136 SRAIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sraw, SelImm.IMM_I, xWen = T), 137 SRLIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srlw, SelImm.IMM_I, xWen = T), 138 139 ADDW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.addw, SelImm.X , xWen = T), 140 SUBW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.subw, SelImm.X , xWen = T), 141 SLLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sllw, SelImm.X , xWen = T), 142 SRAW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sraw, SelImm.X , xWen = T), 143 SRLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srlw, SelImm.X , xWen = T), 144 145 RORW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rorw, SelImm.X , xWen = T), 146 RORIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.rorw, SelImm.IMM_I, xWen = T), 147 ROLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rolw, SelImm.X , xWen = T), 148 ) 149} 150 151/** 152 * Overall Decode constants 153 */ 154object XDecode extends DecodeConstants { 155 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 156 LW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw , SelImm.IMM_I, xWen = T), 157 LH -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lh , SelImm.IMM_I, xWen = T), 158 LHU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lhu , SelImm.IMM_I, xWen = T), 159 LB -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lb , SelImm.IMM_I, xWen = T), 160 LBU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lbu , SelImm.IMM_I, xWen = T), 161 SW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sw , SelImm.IMM_S ), 162 SH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sh , SelImm.IMM_S ), 163 SB -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sb , SelImm.IMM_S ), 164 LUI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add , SelImm.IMM_U, xWen = T), 165 ADDI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add , SelImm.IMM_I, xWen = T), 166 ANDI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.and , SelImm.IMM_I, xWen = T), 167 ORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.or , SelImm.IMM_I, xWen = T), 168 XORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.xor , SelImm.IMM_I, xWen = T), 169 SLTI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slt , SelImm.IMM_I, xWen = T), 170 SLTIU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sltu, SelImm.IMM_I, xWen = T), 171 SLL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sll , SelImm.X , xWen = T), 172 ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.add , SelImm.X , xWen = T), 173 SUB -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sub , SelImm.X , xWen = T), 174 SLT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.slt , SelImm.X , xWen = T), 175 SLTU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sltu, SelImm.X , xWen = T), 176 AND -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.and , SelImm.X , xWen = T), 177 OR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.or , SelImm.X , xWen = T), 178 XOR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xor , SelImm.X , xWen = T), 179 SRA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sra , SelImm.X , xWen = T), 180 SRL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srl , SelImm.X , xWen = T), 181 182 MUL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mul , SelImm.X, xWen = T), 183 MULH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulh , SelImm.X, xWen = T), 184 MULHU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhu , SelImm.X, xWen = T), 185 MULHSU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhsu, SelImm.X, xWen = T), 186 MULW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulw , SelImm.X, xWen = T), 187 188 DIV -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.div , SelImm.X, xWen = T), 189 DIVU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divu , SelImm.X, xWen = T), 190 REM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.rem , SelImm.X, xWen = T), 191 REMU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remu , SelImm.X, xWen = T), 192 DIVW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divw , SelImm.X, xWen = T), 193 DIVUW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divuw , SelImm.X, xWen = T), 194 REMW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remw , SelImm.X, xWen = T), 195 REMUW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remuw , SelImm.X, xWen = T), 196 197 AUIPC -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.auipc, SelImm.IMM_U , xWen = T), 198 JAL -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jal , SelImm.IMM_UJ, xWen = T), 199 JALR -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jalr , SelImm.IMM_I , uopDivType = UopDivType.SCA_SIM, xWen = T), 200 BEQ -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.beq , SelImm.IMM_SB ), 201 BNE -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bne , SelImm.IMM_SB ), 202 BGE -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bge , SelImm.IMM_SB ), 203 BGEU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bgeu , SelImm.IMM_SB ), 204 BLT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.blt , SelImm.IMM_SB ), 205 BLTU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bltu , SelImm.IMM_SB ), 206 207 // I-type, XSDecodeiate12 holds the CSR register. 208 CSRRW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrt , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 209 CSRRS -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.set , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 210 CSRRC -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clr , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 211 212 CSRRWI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrti, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 213 CSRRSI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.seti, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 214 CSRRCI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clri, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 215 216 EBREAK -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 217 ECALL -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 218 SRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 219 MRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 220 DRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 221 WFI -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.csr, CSROpType.wfi, SelImm.X , xWen = T, noSpec = T, blockBack = T), 222 223 SFENCE_VMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 224 FENCE_I -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fencei, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 225 FENCE -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fence , SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 226 227 // A-type 228 AMOADD_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 229 AMOXOR_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 230 AMOSWAP_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 231 AMOAND_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 232 AMOOR_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 233 AMOMIN_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 234 AMOMINU_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 235 AMOMAX_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 236 AMOMAXU_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 237 238 AMOADD_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 239 AMOXOR_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 240 AMOSWAP_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 241 AMOAND_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 242 AMOOR_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 243 AMOMIN_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 244 AMOMINU_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 245 AMOMAX_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 246 AMOMAXU_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 247 248 LR_W -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 249 LR_D -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 250 SC_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 251 SC_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 252 253 ANDN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.andn, SelImm.X, xWen = T), 254 ORN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.orn , SelImm.X, xWen = T), 255 XNOR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xnor, SelImm.X, xWen = T), 256 ORC_B -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.orcb, SelImm.X, xWen = T), 257 258 MIN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.min , SelImm.X, xWen = T), 259 MINU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.minu, SelImm.X, xWen = T), 260 MAX -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.max , SelImm.X, xWen = T), 261 MAXU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.maxu, SelImm.X, xWen = T), 262 263 SEXT_B -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sextb, SelImm.X, xWen = T), 264 PACKH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packh, SelImm.X, xWen = T), 265 SEXT_H -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sexth, SelImm.X, xWen = T), 266 PACKW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packw, SelImm.X, xWen = T), 267 BREV8 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.revb , SelImm.X, xWen = T), 268 REV8 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.rev8 , SelImm.X, xWen = T), 269 PACK -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.pack , SelImm.X, xWen = T), 270 271 BSET -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bset, SelImm.X , xWen = T), 272 BSETI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bset, SelImm.IMM_I, xWen = T), 273 BCLR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bclr, SelImm.X , xWen = T), 274 BCLRI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bclr, SelImm.IMM_I, xWen = T), 275 BINV -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.binv, SelImm.X , xWen = T), 276 BINVI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.binv, SelImm.IMM_I, xWen = T), 277 BEXT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bext, SelImm.X , xWen = T), 278 BEXTI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bext, SelImm.IMM_I, xWen = T), 279 280 ROR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.ror, SelImm.X , xWen = T), 281 RORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.ror, SelImm.IMM_I , xWen = T), 282 ROL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rol, SelImm.X , xWen = T), 283 284 SH1ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1add , SelImm.X , xWen = T), 285 SH2ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2add , SelImm.X , xWen = T), 286 SH3ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3add , SelImm.X , xWen = T), 287 SH1ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1adduw, SelImm.X , xWen = T), 288 SH2ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2adduw, SelImm.X , xWen = T), 289 SH3ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3adduw, SelImm.X , xWen = T), 290 ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.adduw , SelImm.X , xWen = T), 291 SLLI_UW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slliuw , SelImm.IMM_I, xWen = T), 292 ) 293} 294 295/** 296 * FP Decode constants 297 */ 298object FpDecode extends DecodeConstants{ 299 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 300 FLW -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw, selImm = SelImm.IMM_I, fWen = T), 301 FLD -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld, selImm = SelImm.IMM_I, fWen = T), 302 FSW -> FDecode(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sw, selImm = SelImm.IMM_S ), 303 FSD -> FDecode(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sd, selImm = SelImm.IMM_S ), 304 305 FCLASS_S-> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 306 FCLASS_D-> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 307 308 FMV_X_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 309 FMV_X_W -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 310 311 FMV_D_X -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 312 FMV_W_X -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 313 314 FSGNJ_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 315 FSGNJ_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 316 FSGNJX_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 317 FSGNJX_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 318 FSGNJN_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 319 FSGNJN_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 320 321 // FP to FP 322 FCVT_S_D -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 323 FCVT_D_S -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 324 325 // Int to FP 326 FCVT_S_W -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 327 FCVT_S_WU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 328 FCVT_S_L -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 329 FCVT_S_LU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 330 331 FCVT_D_W -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 332 FCVT_D_WU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 333 FCVT_D_L -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 334 FCVT_D_LU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 335 336 // FP to Int 337 FCVT_W_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 338 FCVT_WU_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 339 FCVT_L_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 340 FCVT_LU_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 341 342 FCVT_W_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 343 FCVT_WU_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 344 FCVT_L_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 345 FCVT_LU_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 346 347 FEQ_S -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 348 FLT_S -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 349 FLE_S -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 350 351 FEQ_D -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 352 FLT_D -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 353 FLE_D -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 354 355 FMIN_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 356 FMAX_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 357 FMIN_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 358 FMAX_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 359 360 FADD_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 361 FSUB_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 362 FMUL_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 363 FADD_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 364 FSUB_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 365 FMUL_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 366 367 FMADD_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 368 FMSUB_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 369 FNMADD_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 370 FNMSUB_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 371 FMADD_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 372 FMSUB_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 373 FNMADD_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 374 FNMSUB_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 375 ) 376} 377 378/** 379 * Bit Manipulation Decode 380 */ 381object BDecode extends DecodeConstants{ 382 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 383 // Basic bit manipulation 384 CLZ -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clz, SelImm.X, xWen = T), 385 CTZ -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctz, SelImm.X, xWen = T), 386 CPOP -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpop, SelImm.X, xWen = T), 387 XPERM8 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermb, SelImm.X, xWen = T), 388 XPERM4 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermn, SelImm.X, xWen = T), 389 390 CLZW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clzw, SelImm.X, xWen = T), 391 CTZW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctzw, SelImm.X, xWen = T), 392 CPOPW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpopw, SelImm.X, xWen = T), 393 394 CLMUL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmul, SelImm.X, xWen = T), 395 CLMULH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulh, SelImm.X, xWen = T), 396 CLMULR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulr, SelImm.X, xWen = T), 397 398 AES64ES -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64es, SelImm.X , xWen = T), 399 AES64ESM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64esm, SelImm.X , xWen = T), 400 AES64DS -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ds, SelImm.X , xWen = T), 401 AES64DSM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64dsm, SelImm.X , xWen = T), 402 AES64IM -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.aes64im, SelImm.X , xWen = T), 403 AES64KS1I -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.bku, BKUOpType.aes64ks1i, SelImm.IMM_I, xWen = T), 404 AES64KS2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ks2, SelImm.X , xWen = T), 405 SHA256SUM0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum0, SelImm.X , xWen = T), 406 SHA256SUM1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum1, SelImm.X , xWen = T), 407 SHA256SIG0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig0, SelImm.X , xWen = T), 408 SHA256SIG1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig1, SelImm.X , xWen = T), 409 SHA512SUM0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum0, SelImm.X , xWen = T), 410 SHA512SUM1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum1, SelImm.X , xWen = T), 411 SHA512SIG0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig0, SelImm.X , xWen = T), 412 SHA512SIG1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig1, SelImm.X , xWen = T), 413 SM3P0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p0, SelImm.X , xWen = T), 414 SM3P1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p1, SelImm.X , xWen = T), 415 SM4KS0 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks0, SelImm.X , xWen = T), 416 SM4KS1 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks1, SelImm.X , xWen = T), 417 SM4KS2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks2, SelImm.X , xWen = T), 418 SM4KS3 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks3, SelImm.X , xWen = T), 419 SM4ED0 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed0, SelImm.X , xWen = T), 420 SM4ED1 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed1, SelImm.X , xWen = T), 421 SM4ED2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed2, SelImm.X , xWen = T), 422 SM4ED3 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed3, SelImm.X , xWen = T), 423 ) 424} 425 426/** 427 * FP Divide SquareRoot Constants 428 */ 429object FDivSqrtDecode extends DecodeConstants { 430 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 431 FDIV_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 432 FDIV_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 433 FSQRT_S -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 434 FSQRT_D -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 435 ) 436} 437 438/** 439 * Svinval extension Constants 440 */ 441object SvinvalDecode extends DecodeConstants { 442 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 443 /* sinval_vma is like sfence.vma , but sinval_vma can be dispatched and issued like normal instructions while sfence.vma 444 * must assure it is the ONLY instrucion executing in backend. 445 */ 446 SINVAL_VMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, SelImm.X), 447 /* sfecne.w.inval is the begin instrucion of a TLB flush which set *noSpecExec* and *blockBackward* signals 448 * so when it comes to dispatch , it will block all instruction after itself until all instrucions ahead of it in rob commit 449 * then dispatch and issue this instrucion to flush sbuffer to dcache 450 * after this instrucion commits , issue following sinval_vma instructions (out of order) to flush TLB 451 */ 452 SFENCE_W_INVAL -> XSDecode(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, SelImm.X, noSpec = T, blockBack = T), 453 /* sfecne.inval.ir is the end instrucion of a TLB flush which set *noSpecExec* *blockBackward* and *flushPipe* signals 454 * so when it comes to dispatch , it will wait until all sinval_vma ahead of it in rob commit 455 * then dispatch and issue this instrucion 456 * when it commit at the head of rob , flush the pipeline since some instrucions have been fetched to ibuffer using old TLB map 457 */ 458 SFENCE_INVAL_IR -> XSDecode(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, SelImm.X, noSpec = T, blockBack = T, flushPipe = T) 459 /* what is Svinval extension ? 460 * -----> sfecne.w.inval 461 * sfence.vma vpn1 -----> sinval_vma vpn1 462 * sfence.vma vpn2 -----> sinval_vma vpn2 463 * -----> sfecne.inval.ir 464 * 465 * sfence.vma should be executed in-order and it flushes the pipeline after committing 466 * we can parallel sfence instrucions with this extension 467 */ 468 ) 469} 470 471/* 472 * CBO decode 473 */ 474object CBODecode extends DecodeConstants { 475 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 476 CBO_ZERO -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_zero , SelImm.IMM_S), 477 CBO_CLEAN -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_clean, SelImm.IMM_S), 478 CBO_FLUSH -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_flush, SelImm.IMM_S), 479 CBO_INVAL -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_inval, SelImm.IMM_S) 480 ) 481} 482 483/** 484 * XiangShan Trap Decode constants 485 */ 486object XSTrapDecode extends DecodeConstants { 487 def TRAP = BitPat("b000000000000?????000000001101011") 488 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 489 TRAP -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add, SelImm.IMM_I, xWen = T, xsTrap = T, noSpec = T, blockBack = T) 490 ) 491} 492 493//object Imm32Gen { 494// def apply(sel: UInt, inst: UInt) = { 495// val sign = Mux(sel === SelImm.IMM_Z, 0.S, inst(31).asSInt) 496// val b30_20 = Mux(sel === SelImm.IMM_U, inst(30,20).asSInt, sign) 497// val b19_12 = Mux(sel =/= SelImm.IMM_U && sel =/= SelImm.IMM_UJ, sign, inst(19,12).asSInt) 498// val b11 = Mux(sel === SelImm.IMM_U || sel === SelImm.IMM_Z, 0.S, 499// Mux(sel === SelImm.IMM_UJ, inst(20).asSInt, 500// Mux(sel === SelImm.IMM_SB, inst(7).asSInt, sign))) 501// val b10_5 = Mux(sel === SelImm.IMM_U || sel === SelImm.IMM_Z, 0.U(1.W), inst(30,25)) 502// val b4_1 = Mux(sel === SelImm.IMM_U, 0.U(1.W), 503// Mux(sel === SelImm.IMM_S || sel === SelImm.IMM_SB, inst(11,8), 504// Mux(sel === SelImm.IMM_Z, inst(19,16), inst(24,21)))) 505// val b0 = Mux(sel === SelImm.IMM_S, inst(7), 506// Mux(sel === SelImm.IMM_I, inst(20), 507// Mux(sel === SelImm.IMM_Z, inst(15), 0.U(1.W)))) 508// 509// Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0) 510// } 511//} 512 513abstract class Imm(val len: Int) extends Bundle { 514 def toImm32(minBits: UInt): UInt = do_toImm32(minBits(len - 1, 0)) 515 def do_toImm32(minBits: UInt): UInt 516 def minBitsFromInstr(instr: UInt): UInt 517} 518 519case class Imm_I() extends Imm(12) { 520 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits(len - 1, 0), 32) 521 522 override def minBitsFromInstr(instr: UInt): UInt = 523 Cat(instr(31, 20)) 524} 525 526case class Imm_S() extends Imm(12) { 527 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 528 529 override def minBitsFromInstr(instr: UInt): UInt = 530 Cat(instr(31, 25), instr(11, 7)) 531} 532 533case class Imm_B() extends Imm(12) { 534 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 535 536 override def minBitsFromInstr(instr: UInt): UInt = 537 Cat(instr(31), instr(7), instr(30, 25), instr(11, 8)) 538} 539 540case class Imm_U() extends Imm(20){ 541 override def do_toImm32(minBits: UInt): UInt = Cat(minBits(len - 1, 0), 0.U(12.W)) 542 543 override def minBitsFromInstr(instr: UInt): UInt = { 544 instr(31, 12) 545 } 546} 547 548case class Imm_J() extends Imm(20){ 549 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 550 551 override def minBitsFromInstr(instr: UInt): UInt = { 552 Cat(instr(31), instr(19, 12), instr(20), instr(30, 25), instr(24, 21)) 553 } 554} 555 556case class Imm_Z() extends Imm(12 + 5){ 557 override def do_toImm32(minBits: UInt): UInt = minBits 558 559 override def minBitsFromInstr(instr: UInt): UInt = { 560 Cat(instr(19, 15), instr(31, 20)) 561 } 562} 563 564case class Imm_B6() extends Imm(6){ 565 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 566 567 override def minBitsFromInstr(instr: UInt): UInt = { 568 instr(25, 20) 569 } 570} 571 572case class Imm_OPIVIS() extends Imm(5){ 573 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 574 575 override def minBitsFromInstr(instr: UInt): UInt = { 576 instr(19, 15) 577 } 578} 579case class Imm_OPIVIU() extends Imm(5){ 580 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 581 582 override def minBitsFromInstr(instr: UInt): UInt = { 583 instr(19, 15) 584 } 585} 586case class Imm_VSETVLI() extends Imm(11){ 587 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 588 589 override def minBitsFromInstr(instr: UInt): UInt = { 590 instr(30, 20) 591 } 592} 593case class Imm_VSETIVLI() extends Imm(15){ 594 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 595 596 override def minBitsFromInstr(instr: UInt): UInt = { 597 Cat(instr(19, 15), instr(29, 20)) 598 } 599} 600object ImmUnion { 601 val I = Imm_I() 602 val S = Imm_S() 603 val B = Imm_B() 604 val U = Imm_U() 605 val J = Imm_J() 606 val Z = Imm_Z() 607 val B6 = Imm_B6() 608 val OPIVIS = Imm_OPIVIS() 609 val OPIVIU = Imm_OPIVIU() 610 val VSETVLI = Imm_VSETVLI() 611 val VSETIVLI = Imm_VSETIVLI() 612 613 val imms = Seq(I, S, B, U, J, Z, B6, OPIVIS, OPIVIU, VSETVLI, VSETIVLI) 614 val maxLen = imms.maxBy(_.len).len 615 val immSelMap = Seq( 616 SelImm.IMM_I, 617 SelImm.IMM_S, 618 SelImm.IMM_SB, 619 SelImm.IMM_U, 620 SelImm.IMM_UJ, 621 SelImm.IMM_Z, 622 SelImm.IMM_B6, 623 SelImm.IMM_OPIVIS, 624 SelImm.IMM_OPIVIU, 625 SelImm.IMM_VSETVLI, 626 SelImm.IMM_VSETIVLI 627 ).zip(imms) 628 println(s"ImmUnion max len: $maxLen") 629} 630 631case class Imm_LUI_LOAD() { 632 def immFromLuiLoad(lui_imm: UInt, load_imm: UInt): UInt = { 633 val loadImm = load_imm(Imm_I().len - 1, 0) 634 Cat(lui_imm(Imm_U().len - loadImm.getWidth - 1, 0), loadImm) 635 } 636 def getLuiImm(uop: MicroOp): UInt = { 637 val loadImmLen = Imm_I().len 638 val imm_u = Cat(uop.psrc(1), uop.psrc(0), uop.ctrl.imm(ImmUnion.maxLen - 1, loadImmLen)) 639 Imm_U().do_toImm32(imm_u) 640 } 641} 642 643/** 644 * IO bundle for the Decode unit 645 */ 646class DecodeUnitIO(implicit p: Parameters) extends XSBundle { 647 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 648 val vconfig = Input(new VConfig) 649 val deq = new Bundle { 650 val cf_ctrl = Output(new CfCtrl) 651 val isVset = Output(Bool()) 652 val isComplex = Output(Bool()) 653 } 654 val deq_isVset = new Bundle{ } 655 val csrCtrl = Input(new CustomCSRCtrlIO) 656} 657 658/** 659 * Decode unit that takes in a single CtrlFlow and generates a CfCtrl. 660 */ 661class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstants { 662 val io = IO(new DecodeUnitIO) 663 664 val ctrl_flow = Wire(new CtrlFlow) // input with RVC Expanded 665 val cf_ctrl = Wire(new CfCtrl) 666 667 ctrl_flow := io.enq.ctrl_flow 668 669 val decode_table: Array[(BitPat, List[BitPat])] = XDecode.table ++ 670 FpDecode.table ++ 671 FDivSqrtDecode.table ++ 672 X64Decode.table ++ 673 XSTrapDecode.table ++ 674 BDecode.table ++ 675 CBODecode.table ++ 676 SvinvalDecode.table ++ 677 VecDecoder.table 678 679 require(decode_table.map(_._2.length == 14).reduce(_ && _), "Decode tables have different column size") 680 // assertion for LUI: only LUI should be assigned `selImm === SelImm.IMM_U && fuType === FuType.alu` 681 val luiMatch = (t: Seq[BitPat]) => t(3).value == FuType.alu.litValue && t.reverse.head.value == SelImm.IMM_U.litValue 682 val luiTable = decode_table.filter(t => luiMatch(t._2)).map(_._1).distinct 683 assert(luiTable.length == 1 && luiTable.head == LUI, "Conflicts: LUI is determined by FuType and SelImm in Dispatch") 684 685 // output 686 cf_ctrl.cf := ctrl_flow 687 val cs: CtrlSignals = Wire(new CtrlSignals()).decode(ctrl_flow.instr, decode_table) 688 cs.singleStep := false.B 689 cs.replayInst := false.B 690 cs.debug_globalID := DontCare 691 692 val fpDecoder = Module(new FPDecoder) 693 fpDecoder.io.instr := ctrl_flow.instr 694 cs.fpu := fpDecoder.io.fpCtrl 695 696 cs.srcType(3) := SrcType.vp 697 cs.lsrc(3) := 0.U(5.W) // It is always 0 698 cs.uopIdx := "b11111".U 699 700 val isMove = BitPat("b000000000000_?????_000_?????_0010011") === ctrl_flow.instr 701 cs.isMove := isMove && ctrl_flow.instr(RD_MSB, RD_LSB) =/= 0.U 702 703 // read src1~3 location 704 cs.lsrc(0) := ctrl_flow.instr(RS1_MSB, RS1_LSB) 705 cs.lsrc(1) := ctrl_flow.instr(RS2_MSB, RS2_LSB) 706 cs.lsrc(2) := Mux(FuType.isVecExu(cs.fuType), ctrl_flow.instr(RD_MSB, RD_LSB), ctrl_flow.instr(RS3_MSB, RS3_LSB)) 707 // read dest location 708 cs.ldest := ctrl_flow.instr(RD_MSB, RD_LSB) 709 710 // fill in exception vector 711 cf_ctrl.cf.exceptionVec := io.enq.ctrl_flow.exceptionVec 712 cf_ctrl.cf.exceptionVec(illegalInstr) := cs.selImm === SelImm.INVALID_INSTR 713 714 when (!io.csrCtrl.svinval_enable) { 715 val base_ii = cs.selImm === SelImm.INVALID_INSTR 716 val sinval = BitPat("b0001011_?????_?????_000_00000_1110011") === ctrl_flow.instr 717 val w_inval = BitPat("b0001100_00000_00000_000_00000_1110011") === ctrl_flow.instr 718 val inval_ir = BitPat("b0001100_00001_00000_000_00000_1110011") === ctrl_flow.instr 719 val svinval_ii = sinval || w_inval || inval_ir 720 cf_ctrl.cf.exceptionVec(illegalInstr) := base_ii || svinval_ii 721 cs.flushPipe := false.B 722 } 723 724 // fix frflags 725 // fflags zero csrrs rd csr 726 val isFrflags = BitPat("b000000000001_00000_010_?????_1110011") === ctrl_flow.instr 727 when (cs.fuType === FuType.csr && isFrflags) { 728 cs.blockBackward := false.B 729 } 730 731 cs.imm := LookupTree(cs.selImm, ImmUnion.immSelMap.map( 732 x => { 733 val minBits = x._2.minBitsFromInstr(ctrl_flow.instr) 734 require(minBits.getWidth == x._2.len) 735 x._1 -> minBits 736 } 737 )) 738 739 cs.vconfig := 0.U.asTypeOf(new VConfig) 740 when(FuType.isVecExu(cs.fuType)){ 741 cs.vconfig := io.vconfig 742 } 743 cf_ctrl.ctrl := cs 744 745 io.deq.cf_ctrl := cf_ctrl 746 747 io.deq.isVset := FuType.isIntExu(cs.fuType) && ALUOpType.isVset(cs.fuOpType) 748 io.deq.isComplex := (cs.uopDivType === UopDivType.DIR) || (cs.uopDivType === UopDivType.VEC_LMUL) || (cs.uopDivType === UopDivType.VEC_MV_LMUL) 749 750 //------------------------------------------------------------- 751 // Debug Info 752 XSDebug("in: instr=%x pc=%x excepVec=%b crossPageIPFFix=%d\n", 753 io.enq.ctrl_flow.instr, io.enq.ctrl_flow.pc, io.enq.ctrl_flow.exceptionVec.asUInt, 754 io.enq.ctrl_flow.crossPageIPFFix) 755 XSDebug("out: srcType(0)=%b srcType(1)=%b srcType(2)=%b lsrc(0)=%d lsrc(1)=%d lsrc(2)=%d ldest=%d fuType=%b fuOpType=%b\n", 756 io.deq.cf_ctrl.ctrl.srcType(0), io.deq.cf_ctrl.ctrl.srcType(1), io.deq.cf_ctrl.ctrl.srcType(2), 757 io.deq.cf_ctrl.ctrl.lsrc(0), io.deq.cf_ctrl.ctrl.lsrc(1), io.deq.cf_ctrl.ctrl.lsrc(2), 758 io.deq.cf_ctrl.ctrl.ldest, io.deq.cf_ctrl.ctrl.fuType, io.deq.cf_ctrl.ctrl.fuOpType) 759 XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d flushPipe=%d imm=%x\n", 760 io.deq.cf_ctrl.ctrl.rfWen, io.deq.cf_ctrl.ctrl.fpWen, io.deq.cf_ctrl.ctrl.isXSTrap, 761 io.deq.cf_ctrl.ctrl.noSpecExec, io.deq.cf_ctrl.ctrl.blockBackward, io.deq.cf_ctrl.ctrl.flushPipe, 762 io.deq.cf_ctrl.ctrl.imm) 763 XSDebug("out: excepVec=%b\n", io.deq.cf_ctrl.cf.exceptionVec.asUInt) 764} 765