xref: /XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala (revision 2451989835a019d3c4848f7879147f7649adb760) 
1package xiangshan.backend.datapath
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility._
8import utils.OptionWrapper
9import xiangshan._
10import xiangshan.backend._
11import xiangshan.backend.datapath.WbConfig._
12import xiangshan.backend.exu.ExeUnitParams
13
14class WbFuBusyTable(bp: BackendParams)(implicit  p: Parameters) extends LazyModule {
15  implicit val params: BackendParams = bp
16  lazy val module = new WbFuBusyTableImp(this)
17}
18
19class WbFuBusyTableImp(override val wrapper: WbFuBusyTable)(implicit  p: Parameters, params: BackendParams) extends LazyModuleImp(wrapper) {
20  val io = IO(new WbFuBusyTableIO)
21
22  private val intSchdBusyTable = io.in.intSchdBusyTable
23  private val vfSchdBusyTable = io.in.vfSchdBusyTable
24  private val memSchdBusyTable = io.in.memSchdBusyTable
25  private val intRespRead = io.out.intRespRead
26  private val vfRespRead = io.out.vfRespRead
27  private val memRespRead = io.out.memRespRead
28  private val intAllWbConflictFlag = io.out.wbConflictRead.flatten.flatten.map(_.intConflict)
29  private val vfAllWbConflictFlag = io.out.wbConflictRead.flatten.flatten.map(_.vfConflict)
30
31  private val intAllBusyTable = (intSchdBusyTable ++ vfSchdBusyTable ++ memSchdBusyTable).flatten.map(_.intWbBusyTable)
32  private val vfAllBusyTable = (intSchdBusyTable ++ vfSchdBusyTable ++ memSchdBusyTable).flatten.map(_.vfWbBusyTable)
33  private val intAllDeqRespSet = (intSchdBusyTable ++ vfSchdBusyTable ++ memSchdBusyTable).flatten.map(_.intDeqRespSet)
34  private val vfAllDeqRespSet = (intSchdBusyTable ++ vfSchdBusyTable ++ memSchdBusyTable).flatten.map(_.vfDeqRespSet)
35  private val intAllRespRead = (intRespRead ++ vfRespRead ++ memRespRead).flatten.map(_.intWbBusyTable)
36  private val vfAllRespRead = (intRespRead ++ vfRespRead ++ memRespRead).flatten.map(_.vfWbBusyTable)
37
38  private val allExuParams = params.allExuParams
39  private val intAllBusyTableWithParms = intAllBusyTable.zip(allExuParams)
40  private val vfAllBusyTableWithParms = vfAllBusyTable.zip(allExuParams)
41  private val intAllDeqRespSetWithParms = intAllDeqRespSet.zip(allExuParams)
42  private val vfAllDeqRespSetWithParms = vfAllDeqRespSet.zip(allExuParams)
43
44  private val intWbLatencyMax = params.getIntWBExeGroup.map { case (portId, seq) => (portId, seq.map(_.intLatencyValMax).max, seq.forall(_.intLatencyCertain)) }
45  private val vfWbLatencyMax = params.getVfWBExeGroup.map { case (portId, seq) => (portId, seq.map(_.vfLatencyValMax).max, seq.forall(_.vfLatencyCertain)) }
46  private val intWbBusyTable: Map[Int, Option[UInt]] = intWbLatencyMax.map { case (portId, latMax, latCertain) => (portId, OptionWrapper(latCertain, Wire(UInt((latMax + 1).W)))) }.toMap
47  private val vfWbBusyTable = vfWbLatencyMax.map { case (portId, latMax, latCertain) => (portId, OptionWrapper(latCertain, Wire(UInt((latMax + 1).W)))) }.toMap
48  private val intConflict: Map[Int, Option[Bool]] = intWbLatencyMax.map { case (portId, latMax, latCertain) => (portId, OptionWrapper(latCertain, Reg(Bool()))) }.toMap
49  private val vfConflict = vfWbLatencyMax.map { case (portId, latMax, latCertain) => (portId, OptionWrapper(latCertain, Reg(Bool()))) }.toMap
50
51  def hitWbPort[T <: Data](source: Option[T], p: ExeUnitParams, portId: Int, isInt: Boolean) = {
52    if(isInt){
53      p.wbPortConfigs.collectFirst { case x : IntWB => x.port }.getOrElse(-1) == portId && source.nonEmpty
54    } else {
55      p.wbPortConfigs.collectFirst { case x : VfWB => x.port }.getOrElse(-1) == portId && source.nonEmpty
56    }
57  }
58
59  def writeBusyTable(wtBusyTable: Map[Int, Option[UInt]], busyTableWithParams: IndexedSeq[(Option[UInt], ExeUnitParams)], isInt: Boolean) = {
60    wtBusyTable.foreach { case (portId, busyTable) =>
61      if (busyTable.nonEmpty) {
62        busyTable.get := busyTableWithParams.filter { case (busyTable, p) => hitWbPort(busyTable, p, portId, isInt) }.map(_._1.get).reduce(_ | _)
63      }
64    }
65  }
66
67  def writeConflict(wtConflict: Map[Int, Option[Bool]], deqRespSetWithParams: IndexedSeq[(Option[UInt], ExeUnitParams)], isInt: Boolean) = {
68    wtConflict.foreach { case (portId, conflict) =>
69      if (conflict.nonEmpty) {
70        val deqRespSel = deqRespSetWithParams.filter { case (deqRespSet, p) => hitWbPort(deqRespSet, p, portId, isInt) }.map(_._1.get)
71        val width = deqRespSel.map(x => x.getWidth).max
72        val deqRespSelUnify = deqRespSel.map(x => x.asTypeOf(UInt(width.W)))
73        conflict.get := (0 until width).map{ case i =>
74          OnesMoreThan(deqRespSelUnify.map(x => x(i)), 2)
75        }.reduce(_ | _)
76      }
77    }
78  }
79
80  def readRes[T <: Data](sink: IndexedSeq[Option[T]], source: Map[Int, Option[T]], isInt: Boolean) = {
81    for(i <- 0 until sink.size) {
82      if(sink(i).nonEmpty) {
83        sink(i).get := source.map { case (portId, src) =>
84          if(hitWbPort(src, allExuParams(i), portId, isInt)) {
85            src.get.asTypeOf(sink(i).get).asUInt
86          } else {
87            0.U.asTypeOf(sink(i).get).asUInt
88          }
89        }.reduce(_ | _)
90      }
91    }
92  }
93
94
95
96  //per wbPort fuBusyTable
97  writeBusyTable(intWbBusyTable, intAllBusyTableWithParms, true)
98  writeBusyTable(vfWbBusyTable, vfAllBusyTableWithParms, false)
99  //per wbPort conflict
100  writeConflict(intConflict, intAllDeqRespSetWithParms, true)
101  writeConflict(vfConflict, vfAllDeqRespSetWithParms, false)
102  //read wbPort fuBusyTable to per exe
103  readRes(intAllRespRead, intWbBusyTable, true)
104  readRes(vfAllRespRead, vfWbBusyTable, false)
105  //read wbPort conflict to dataPath
106  readRes(intAllWbConflictFlag, intConflict, true)
107  readRes(vfAllWbConflictFlag, vfConflict, false)
108
109}
110
111class WbFuBusyTableIO(implicit p: Parameters, params: BackendParams) extends XSBundle {
112  val in = new Bundle {
113    val intSchdBusyTable = MixedVec(params.intSchdParams.get.issueBlockParams.map(x => Input(x.genWbFuBusyTableWriteBundle)))
114    val vfSchdBusyTable = MixedVec(params.vfSchdParams.get.issueBlockParams.map(x => Input(x.genWbFuBusyTableWriteBundle)))
115    val memSchdBusyTable = MixedVec(params.memSchdParams.get.issueBlockParams.map(x => Input(x.genWbFuBusyTableWriteBundle)))
116  }
117  val out = new Bundle {
118    val intRespRead = MixedVec(params.intSchdParams.get.issueBlockParams.map(x => Output(x.genWbFuBusyTableReadBundle)))
119    val vfRespRead = MixedVec(params.vfSchdParams.get.issueBlockParams.map(x => Output(x.genWbFuBusyTableReadBundle)))
120    val memRespRead = MixedVec(params.memSchdParams.get.issueBlockParams.map(x => Output(x.genWbFuBusyTableReadBundle)))
121    val wbConflictRead = MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => Output(x.genWbConflictBundle())))))
122  }
123}