1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3.Output 5import chisel3.util.{DecoupledIO, MixedVec, ValidIO, log2Up} 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.WriteBackBundle 8import xiangshan.backend.datapath.DataConfig.{FpData, IntData, VecData} 9import xiangshan.backend.datapath.WbConfig._ 10import xiangshan.backend.regfile.PregParams 11 12case class WbArbiterParams( 13 wbCfgs : Seq[PregWB], 14 pregParams: PregParams, 15 backendParams: BackendParams, 16) { 17 18 def numIn = wbCfgs.length 19 20 def numOut = wbCfgs.head match { 21 case _: WbConfig.IntWB => pregParams.numWrite.getOrElse(backendParams.getWbPortIndices(IntData()).size) 22 case _: WbConfig.FpWB => pregParams.numWrite.getOrElse(backendParams.getWbPortIndices(FpData()).size) 23 case _: WbConfig.VfWB => pregParams.numWrite.getOrElse(backendParams.getWbPortIndices(VecData()).size) 24 case x => 25 assert(assertion = false, s"the WbConfig in WbArbiterParams should be either IntWB or FpWB or VfWB, found ${x.getClass}") 26 0 27 } 28 29 def dataWidth = pregParams.dataCfg.dataWidth 30 31 def addrWidth = log2Up(pregParams.numEntries) 32 33 def genInput(implicit p: Parameters) = { 34 MixedVec(wbCfgs.map(x => DecoupledIO(new WriteBackBundle(x, backendParams)))) 35 } 36 37 def genOutput(implicit p: Parameters): MixedVec[ValidIO[WriteBackBundle]] = { 38 Output(MixedVec(Seq.tabulate(numOut) { 39 x => 40 ValidIO(new WriteBackBundle( 41 wbCfgs.head.dataCfg match { 42 case IntData() => IntWB(port = x) 43 case FpData() => FpWB(port = x) 44 case VecData() => VfWB(port = x) 45 case _ => ??? 46 }, 47 backendParams 48 ) 49 ) 50 } 51 ) 52 ) 53 } 54} 55