1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DiffFpWriteback, DiffIntWriteback, DifftestModule} 7import utils.XSError 8import xiangshan.backend.BackendParams 9import xiangshan.backend.Bundles.{ExuOutput, WriteBackBundle} 10import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 11import xiangshan.backend.regfile.RfWritePortWithConfig 12import xiangshan.{Redirect, XSBundle, XSModule} 13 14class WbArbiterDispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 15 val in = Flipped(DecoupledIO(gen)) 16 17 val out = Vec(n, DecoupledIO(gen)) 18} 19 20class WbArbiterDispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 21 (implicit p: Parameters) 22 extends Module { 23 24 val io = IO(new WbArbiterDispatcherIO(gen, n)) 25 26 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 27 28 XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 29 30 io.out.zipWithIndex.foreach { case (out, i) => 31 out.valid := acceptVec(i) && io.in.valid 32 out.bits := io.in.bits 33 } 34 35 io.in.ready := Cat(io.out.zip(acceptVec).map{ case(out, canAccept) => out.ready && canAccept}).orR 36} 37 38class WbArbiterIO()(implicit p: Parameters, params: WbArbiterParams) extends XSBundle { 39 val flush = Flipped(ValidIO(new Redirect)) 40 val in: MixedVec[DecoupledIO[WriteBackBundle]] = Flipped(params.genInput) 41 val out: MixedVec[ValidIO[WriteBackBundle]] = params.genOutput 42 43 def inGroup: Map[Int, Seq[DecoupledIO[WriteBackBundle]]] = in.groupBy(_.bits.params.port).map(x => (x._1, x._2.sortBy(_.bits.params.priority).toSeq)) 44} 45 46class WbArbiter(params: WbArbiterParams)(implicit p: Parameters) extends XSModule { 47 val io = IO(new WbArbiterIO()(p, params)) 48 49 private val inGroup: Map[Int, Seq[DecoupledIO[WriteBackBundle]]] = io.inGroup 50 51 private val arbiters: Seq[Option[Arbiter[WriteBackBundle]]] = Seq.tabulate(params.numOut) { x => { 52 if (inGroup.contains(x)) { 53 Some(Module(new Arbiter(new WriteBackBundle(inGroup.values.head.head.bits.params, backendParams), inGroup(x).length))) 54 } else { 55 None 56 } 57 }} 58 59 arbiters.zipWithIndex.foreach { case (arb, i) => 60 if (arb.nonEmpty) { 61 arb.get.io.in.zip(inGroup(i)).foreach { case (arbIn, wbIn) => 62 arbIn <> wbIn 63 } 64 } 65 } 66 67 io.out.zip(arbiters).foreach { case (wbOut, arb) => 68 if (arb.nonEmpty) { 69 val arbOut = arb.get.io.out 70 arbOut.ready := true.B 71 wbOut.valid := arbOut.valid 72 wbOut.bits := arbOut.bits 73 } else { 74 wbOut := 0.U.asTypeOf(wbOut) 75 } 76 } 77 78 def getInOutMap: Map[Int, Int] = { 79 (params.wbCfgs.indices zip params.wbCfgs.map(_.port)).toMap 80 } 81} 82 83class WbDataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 84 val flush = Flipped(ValidIO(new Redirect())) 85 86 val fromTop = new Bundle { 87 val hartId = Input(UInt(8.W)) 88 } 89 90 val fromIntExu: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = Flipped(params.intSchdParams.get.genExuOutputDecoupledBundle) 91 92 val fromVfExu: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = Flipped(params.vfSchdParams.get.genExuOutputDecoupledBundle) 93 94 val fromMemExu: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = Flipped(params.memSchdParams.get.genExuOutputDecoupledBundle) 95 96 val oldVdDataFromDataPath = Input(UInt(VLEN.W)) 97 98 val oldVdAddrToDataPath = Output(UInt(PhyRegIdxWidth.W)) 99 100 val toIntPreg = Flipped(MixedVec(Vec(params.numPregWb(IntData()), 101 new RfWritePortWithConfig(params.intPregParams.dataCfg, params.intPregParams.addrWidth)))) 102 103 val toVfPreg = Flipped(MixedVec(Vec(params.numPregWb(VecData()), 104 new RfWritePortWithConfig(params.vfPregParams.dataCfg, params.vfPregParams.addrWidth)))) 105 106 val toCtrlBlock = new Bundle { 107 val writeback: MixedVec[ValidIO[ExuOutput]] = params.genWrite2CtrlBundles 108 } 109} 110 111class WbDataPath(params: BackendParams)(implicit p: Parameters) extends XSModule { 112 val io = IO(new WbDataPathIO()(p, params)) 113 114 // split 115 val fromExuPre = (io.fromIntExu ++ io.fromVfExu ++ io.fromMemExu).flatten 116 val fromExuVld: Seq[DecoupledIO[ExuOutput]] = fromExuPre.filter(_.bits.params.hasVLoadFu).toSeq 117 require(fromExuVld.size == 1, "vldCnt should be 1") 118 val vldMgu = Module(new VldMergeUnit(fromExuVld.head.bits.params)) 119 vldMgu.io.flush := io.flush 120 vldMgu.io.writeback <> fromExuVld.head 121 vldMgu.io.oldVdReadData := io.oldVdDataFromDataPath 122 io.oldVdAddrToDataPath := vldMgu.io.oldVdReadAddr 123 val wbReplaceVld: Seq[DecoupledIO[ExuOutput]] = fromExuPre.updated(fromExuPre.indexWhere(_.bits.params.hasVLoadFu), vldMgu.io.writebackAfterMerge).toSeq 124 val fromExu: MixedVec[DecoupledIO[ExuOutput]] = MixedVecInit(wbReplaceVld) 125 126 // io.fromExuPre ------------------------------------------------------------> fromExu 127 // \ / 128 // -> vldMgu.io.writeback -> vldMgu.io.writebackAfterMerge / 129 (fromExu zip wbReplaceVld).foreach { case (sink, source) => source.ready := sink.ready } 130 131 // alias 132 // replace vldu write bundle with vldMdu output bundle 133 val intArbiterInputsWire = WireInit(fromExu) 134 val intArbiterInputsWireY = intArbiterInputsWire.filter(_.bits.params.writeIntRf) 135 val intArbiterInputsWireN = intArbiterInputsWire.filterNot(_.bits.params.writeIntRf) 136 val vfArbiterInputsWire = WireInit(fromExu) 137 val vfArbiterInputsWireY = vfArbiterInputsWire.filter(_.bits.params.writeVfRf) 138 val vfArbiterInputsWireN = vfArbiterInputsWire.filterNot(_.bits.params.writeVfRf) 139 140 def acceptCond(exuOutput: ExuOutput): Seq[Bool] = { 141 val intWen = if(exuOutput.intWen.isDefined) exuOutput.intWen.get else false.B 142 val fpwen = if(exuOutput.fpWen.isDefined) exuOutput.fpWen.get else false.B 143 val vecWen = if(exuOutput.vecWen.isDefined) exuOutput.vecWen.get else false.B 144 Seq(intWen, fpwen || vecWen) 145 } 146 147 fromExu.zip(intArbiterInputsWire.zip(vfArbiterInputsWire))map{ 148 case (exuOut, (intArbiterInput, vfArbiterInput)) => 149 val regfilesTypeNum = params.pregParams.size 150 val in1ToN = Module(new WbArbiterDispatcher(new ExuOutput(exuOut.bits.params), regfilesTypeNum, acceptCond)) 151 in1ToN.io.in.valid := exuOut.valid 152 in1ToN.io.in.bits := exuOut.bits 153 exuOut.ready := in1ToN.io.in.ready 154 in1ToN.io.out.zip(MixedVecInit(intArbiterInput, vfArbiterInput)).foreach { case (source, sink) => 155 sink.valid := source.valid 156 sink.bits := source.bits 157 source.ready := sink.ready 158 } 159 } 160 intArbiterInputsWireN.foreach(_.ready := false.B) 161 vfArbiterInputsWireN.foreach(_.ready := false.B) 162 163 println(s"[WbDataPath] write int preg: " + 164 s"IntExu(${io.fromIntExu.flatten.count(_.bits.params.writeIntRf)}) " + 165 s"VfExu(${io.fromVfExu.flatten.count(_.bits.params.writeIntRf)}) " + 166 s"MemExu(${io.fromMemExu.flatten.count(_.bits.params.writeIntRf)})" 167 ) 168 println(s"[WbDataPath] write vf preg: " + 169 s"IntExu(${io.fromIntExu.flatten.count(_.bits.params.writeVfRf)}) " + 170 s"VfExu(${io.fromVfExu.flatten.count(_.bits.params.writeVfRf)}) " + 171 s"MemExu(${io.fromMemExu.flatten.count(_.bits.params.writeVfRf)})" 172 ) 173 174 // modules 175 private val intWbArbiter = Module(new WbArbiter(params.getIntWbArbiterParams)) 176 private val vfWbArbiter = Module(new WbArbiter(params.getVfWbArbiterParams)) 177 println(s"[WbDataPath] int preg write back port num: ${intWbArbiter.io.out.size}, active port: ${intWbArbiter.io.inGroup.keys.toSeq.sorted}") 178 println(s"[WbDataPath] vf preg write back port num: ${vfWbArbiter.io.out.size}, active port: ${vfWbArbiter.io.inGroup.keys.toSeq.sorted}") 179 180 // module assign 181 intWbArbiter.io.flush <> io.flush 182 require(intWbArbiter.io.in.size == intArbiterInputsWireY.size, s"intWbArbiter input size: ${intWbArbiter.io.in.size}, all vf wb size: ${intArbiterInputsWireY.size}") 183 intWbArbiter.io.in.zip(intArbiterInputsWireY).foreach { case (arbiterIn, in) => 184 arbiterIn.valid := in.valid && in.bits.intWen.get 185 in.ready := arbiterIn.ready 186 arbiterIn.bits.fromExuOutput(in.bits) 187 } 188 private val intWbArbiterOut = intWbArbiter.io.out 189 190 vfWbArbiter.io.flush <> io.flush 191 require(vfWbArbiter.io.in.size == vfArbiterInputsWireY.size, s"vfWbArbiter input size: ${vfWbArbiter.io.in.size}, all vf wb size: ${vfArbiterInputsWireY.size}") 192 vfWbArbiter.io.in.zip(vfArbiterInputsWireY).foreach { case (arbiterIn, in) => 193 arbiterIn.valid := in.valid && (in.bits.fpWen.getOrElse(false.B) || in.bits.vecWen.getOrElse(false.B)) 194 in.ready := arbiterIn.ready 195 arbiterIn.bits.fromExuOutput(in.bits) 196 } 197 198 private val vfWbArbiterOut = vfWbArbiter.io.out 199 200 private val intExuInputs = io.fromIntExu.flatten.toSeq 201 private val intExuWBs = WireInit(MixedVecInit(intExuInputs)) 202 private val vfExuInputs = io.fromVfExu.flatten.toSeq 203 private val vfExuWBs = WireInit(MixedVecInit(vfExuInputs)) 204 private val memExuInputs = io.fromMemExu.flatten.toSeq 205 private val memExuWBs = WireInit(MixedVecInit(memExuInputs)) 206 207 // only fired port can write back to ctrl block 208 (intExuWBs zip intExuInputs).foreach { case (wb, input) => wb.valid := input.fire } 209 (vfExuWBs zip vfExuInputs).foreach { case (wb, input) => wb.valid := input.fire } 210 (memExuWBs zip memExuInputs).foreach { case (wb, input) => wb.valid := input.fire } 211 212 // the ports not writting back pregs are always ready 213 // the ports set highest priority are always ready 214 (fromExu).foreach( x => 215 if (x.bits.params.hasNoDataWB || x.bits.params.isHighestWBPriority) x.ready := true.B 216 ) 217 218 // io assign 219 private val toIntPreg: MixedVec[RfWritePortWithConfig] = MixedVecInit(intWbArbiterOut.map(x => x.bits.asIntRfWriteBundle(x.fire)).toSeq) 220 private val toVfPreg: MixedVec[RfWritePortWithConfig] = MixedVecInit(vfWbArbiterOut.map(x => x.bits.asVfRfWriteBundle(x.fire)).toSeq) 221 222 private val wb2Ctrl = intExuWBs ++ vfExuWBs ++ memExuWBs 223 224 io.toIntPreg := toIntPreg 225 io.toVfPreg := toVfPreg 226 io.toCtrlBlock.writeback.zip(wb2Ctrl).foreach { case (sink, source) => 227 sink.valid := source.valid 228 sink.bits := source.bits 229 source.ready := true.B 230 } 231 232 if (env.EnableDifftest || env.AlwaysBasicDiff) { 233 intWbArbiterOut.foreach(out => { 234 val difftest = DifftestModule(new DiffIntWriteback(IntPhyRegs)) 235 difftest.coreid := io.fromTop.hartId 236 difftest.valid := out.fire && out.bits.rfWen 237 difftest.address := out.bits.pdest 238 difftest.data := out.bits.data 239 }) 240 } 241 242 if (env.EnableDifftest || env.AlwaysBasicDiff) { 243 vfWbArbiterOut.foreach(out => { 244 val difftest = DifftestModule(new DiffFpWriteback(VfPhyRegs)) 245 difftest.coreid := io.fromTop.hartId 246 difftest.valid := out.fire // all fp instr will write fp rf 247 difftest.address := out.bits.pdest 248 difftest.data := out.bits.data 249 }) 250 } 251 252} 253 254 255 256 257