1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DiffFpWriteback, DiffIntWriteback, DifftestModule} 7import utils.XSError 8import xiangshan.backend.BackendParams 9import xiangshan.backend.Bundles.{ExuOutput, WriteBackBundle} 10import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 11import xiangshan.backend.regfile.RfWritePortWithConfig 12import xiangshan.{Redirect, XSBundle, XSModule} 13 14class WbArbiterDispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 15 val in = Flipped(DecoupledIO(gen)) 16 17 val out = Vec(n, DecoupledIO(gen)) 18} 19 20class WbArbiterDispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 21 (implicit p: Parameters) 22 extends Module { 23 24 val io = IO(new WbArbiterDispatcherIO(gen, n)) 25 26 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 27 28 XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 29 30 io.out.zipWithIndex.foreach { case (out, i) => 31 out.valid := acceptVec(i) && io.in.valid 32 out.bits := io.in.bits 33 } 34 35 io.in.ready := Cat(io.out.zip(acceptVec).map{ case(out, canAccept) => out.ready && canAccept}).orR 36} 37 38class WbArbiterIO()(implicit p: Parameters, params: WbArbiterParams) extends XSBundle { 39 val flush = Flipped(ValidIO(new Redirect)) 40 val in: MixedVec[DecoupledIO[WriteBackBundle]] = Flipped(params.genInput) 41 val out: MixedVec[ValidIO[WriteBackBundle]] = params.genOutput 42 43 def inGroup: Map[Int, Seq[DecoupledIO[WriteBackBundle]]] = in.groupBy(_.bits.params.port).map(x => (x._1, x._2.sortBy(_.bits.params.priority).toSeq)) 44} 45 46class WbArbiter(params: WbArbiterParams)(implicit p: Parameters) extends XSModule { 47 val io = IO(new WbArbiterIO()(p, params)) 48 49 private val inGroup: Map[Int, Seq[DecoupledIO[WriteBackBundle]]] = io.inGroup 50 51 private val arbiters: Seq[Option[Arbiter[WriteBackBundle]]] = Seq.tabulate(params.numOut) { x => { 52 if (inGroup.contains(x)) { 53 Some(Module(new Arbiter(new WriteBackBundle(inGroup.values.head.head.bits.params, backendParams), inGroup(x).length))) 54 } else { 55 None 56 } 57 }} 58 59 arbiters.zipWithIndex.foreach { case (arb, i) => 60 if (arb.nonEmpty) { 61 arb.get.io.in.zip(inGroup(i)).foreach { case (arbIn, wbIn) => 62 arbIn <> wbIn 63 } 64 } 65 } 66 67 io.out.zip(arbiters).foreach { case (wbOut, arb) => 68 if (arb.nonEmpty) { 69 val arbOut = arb.get.io.out 70 arbOut.ready := true.B 71 wbOut.valid := arbOut.valid 72 wbOut.bits := arbOut.bits 73 } else { 74 wbOut := 0.U.asTypeOf(wbOut) 75 } 76 } 77 78 def getInOutMap: Map[Int, Int] = { 79 (params.wbCfgs.indices zip params.wbCfgs.map(_.port)).toMap 80 } 81} 82 83class WbDataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 84 val flush = Flipped(ValidIO(new Redirect())) 85 86 val fromTop = new Bundle { 87 val hartId = Input(UInt(8.W)) 88 } 89 90 val fromIntExu: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = Flipped(params.intSchdParams.get.genExuOutputDecoupledBundle) 91 92 val fromVfExu: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = Flipped(params.vfSchdParams.get.genExuOutputDecoupledBundle) 93 94 val fromMemExu: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = Flipped(params.memSchdParams.get.genExuOutputDecoupledBundle) 95 96 val toIntPreg = Flipped(MixedVec(Vec(params.numPregWb(IntData()), 97 new RfWritePortWithConfig(params.intPregParams.dataCfg, params.intPregParams.addrWidth)))) 98 99 val toVfPreg = Flipped(MixedVec(Vec(params.numPregWb(VecData()), 100 new RfWritePortWithConfig(params.vfPregParams.dataCfg, params.vfPregParams.addrWidth)))) 101 102 val toCtrlBlock = new Bundle { 103 val writeback: MixedVec[ValidIO[ExuOutput]] = params.genWrite2CtrlBundles 104 } 105} 106 107class WbDataPath(params: BackendParams)(implicit p: Parameters) extends XSModule { 108 val io = IO(new WbDataPathIO()(p, params)) 109 110 // alias 111 val fromExu = (io.fromIntExu ++ io.fromVfExu ++ io.fromMemExu).flatten.toSeq 112 val intArbiterInputsWire = WireInit(MixedVecInit(fromExu)) 113 val intArbiterInputsWireY = intArbiterInputsWire.filter(_.bits.params.writeIntRf) 114 val intArbiterInputsWireN = intArbiterInputsWire.filterNot(_.bits.params.writeIntRf) 115 val vfArbiterInputsWire = WireInit(MixedVecInit(fromExu)) 116 val vfArbiterInputsWireY = vfArbiterInputsWire.filter(_.bits.params.writeVfRf) 117 val vfArbiterInputsWireN = vfArbiterInputsWire.filterNot(_.bits.params.writeVfRf) 118 119 def acceptCond(exuOutput: ExuOutput): Seq[Bool] = { 120 val intWen = if(exuOutput.intWen.isDefined) exuOutput.intWen.get else false.B 121 val fpwen = if(exuOutput.fpWen.isDefined) exuOutput.fpWen.get else false.B 122 val vecWen = if(exuOutput.vecWen.isDefined) exuOutput.vecWen.get else false.B 123 Seq(intWen, fpwen || vecWen) 124 } 125 126 fromExu.zip(intArbiterInputsWire.zip(vfArbiterInputsWire))map{ 127 case (exuOut, (intArbiterInput, vfArbiterInput)) => 128 val regfilesTypeNum = params.pregParams.size 129 val in1ToN = Module(new WbArbiterDispatcher(new ExuOutput(exuOut.bits.params), regfilesTypeNum, acceptCond)) 130 in1ToN.io.in.valid := exuOut.valid 131 in1ToN.io.in.bits := exuOut.bits 132 exuOut.ready := in1ToN.io.in.ready 133 in1ToN.io.out.zip(MixedVecInit(intArbiterInput, vfArbiterInput)).foreach { case (source, sink) => 134 sink.valid := source.valid 135 sink.bits := source.bits 136 source.ready := sink.ready 137 } 138 } 139 intArbiterInputsWireN.foreach(_.ready := false.B) 140 vfArbiterInputsWireN.foreach(_.ready := false.B) 141 142 println(s"[WbDataPath] write int preg: " + 143 s"IntExu(${io.fromIntExu.flatten.count(_.bits.params.writeIntRf)}) " + 144 s"VfExu(${io.fromVfExu.flatten.count(_.bits.params.writeIntRf)}) " + 145 s"MemExu(${io.fromMemExu.flatten.count(_.bits.params.writeIntRf)})" 146 ) 147 println(s"[WbDataPath] write vf preg: " + 148 s"IntExu(${io.fromIntExu.flatten.count(_.bits.params.writeVfRf)}) " + 149 s"VfExu(${io.fromVfExu.flatten.count(_.bits.params.writeVfRf)}) " + 150 s"MemExu(${io.fromMemExu.flatten.count(_.bits.params.writeVfRf)})" 151 ) 152 153 // modules 154 private val intWbArbiter = Module(new WbArbiter(params.getIntWbArbiterParams)) 155 private val vfWbArbiter = Module(new WbArbiter(params.getVfWbArbiterParams)) 156 println(s"[WbDataPath] int preg write back port num: ${intWbArbiter.io.out.size}, active port: ${intWbArbiter.io.inGroup.keys.toSeq.sorted}") 157 println(s"[WbDataPath] vf preg write back port num: ${vfWbArbiter.io.out.size}, active port: ${vfWbArbiter.io.inGroup.keys.toSeq.sorted}") 158 159 // module assign 160 intWbArbiter.io.flush <> io.flush 161 require(intWbArbiter.io.in.size == intArbiterInputsWireY.size, s"intWbArbiter input size: ${intWbArbiter.io.in.size}, all vf wb size: ${intArbiterInputsWireY.size}") 162 intWbArbiter.io.in.zip(intArbiterInputsWireY).foreach { case (arbiterIn, in) => 163 arbiterIn.valid := in.valid && in.bits.intWen.get 164 in.ready := arbiterIn.ready 165 arbiterIn.bits.fromExuOutput(in.bits) 166 } 167 private val intWbArbiterOut = intWbArbiter.io.out 168 169 vfWbArbiter.io.flush <> io.flush 170 require(vfWbArbiter.io.in.size == vfArbiterInputsWireY.size, s"vfWbArbiter input size: ${vfWbArbiter.io.in.size}, all vf wb size: ${vfArbiterInputsWireY.size}") 171 vfWbArbiter.io.in.zip(vfArbiterInputsWireY).foreach { case (arbiterIn, in) => 172 arbiterIn.valid := in.valid && (in.bits.fpWen.getOrElse(false.B) || in.bits.vecWen.getOrElse(false.B)) 173 in.ready := arbiterIn.ready 174 arbiterIn.bits.fromExuOutput(in.bits) 175 } 176 177 private val vfWbArbiterOut = vfWbArbiter.io.out 178 179 private val intExuInputs = io.fromIntExu.flatten.toSeq 180 private val intExuWBs = WireInit(MixedVecInit(intExuInputs)) 181 private val vfExuInputs = io.fromVfExu.flatten.toSeq 182 private val vfExuWBs = WireInit(MixedVecInit(vfExuInputs)) 183 private val memExuInputs = io.fromMemExu.flatten.toSeq 184 private val memExuWBs = WireInit(MixedVecInit(memExuInputs)) 185 186 // only fired port can write back to ctrl block 187 (intExuWBs zip intExuInputs).foreach { case (wb, input) => wb.valid := input.fire } 188 (vfExuWBs zip vfExuInputs).foreach { case (wb, input) => wb.valid := input.fire } 189 (memExuWBs zip memExuInputs).foreach { case (wb, input) => wb.valid := input.fire } 190 191 // the ports not writting back pregs are always ready 192 // the ports set highest priority are always ready 193 (intExuInputs ++ vfExuInputs ++ memExuInputs).foreach( x => 194 if (x.bits.params.hasNoDataWB || x.bits.params.isHighestWBPriority) x.ready := true.B 195 ) 196 197 // io assign 198 private val toIntPreg: MixedVec[RfWritePortWithConfig] = MixedVecInit(intWbArbiterOut.map(x => x.bits.asIntRfWriteBundle(x.fire)).toSeq) 199 private val toVfPreg: MixedVec[RfWritePortWithConfig] = MixedVecInit(vfWbArbiterOut.map(x => x.bits.asVfRfWriteBundle(x.fire)).toSeq) 200 201 private val wb2Ctrl = intExuWBs ++ vfExuWBs ++ memExuWBs 202 203 io.toIntPreg := toIntPreg 204 io.toVfPreg := toVfPreg 205 io.toCtrlBlock.writeback.zip(wb2Ctrl).foreach { case (sink, source) => 206 sink.valid := source.valid 207 sink.bits := source.bits 208 source.ready := true.B 209 } 210 211 if (env.EnableDifftest || env.AlwaysBasicDiff) { 212 intWbArbiterOut.foreach(out => { 213 val difftest = DifftestModule(new DiffIntWriteback) 214 difftest.coreid := io.fromTop.hartId 215 difftest.valid := out.fire && out.bits.rfWen 216 difftest.address := out.bits.pdest 217 difftest.data := out.bits.data 218 }) 219 } 220 221 if (env.EnableDifftest || env.AlwaysBasicDiff) { 222 vfWbArbiterOut.foreach(out => { 223 val difftest = DifftestModule(new DiffFpWriteback) 224 difftest.coreid := io.fromTop.hartId 225 difftest.valid := out.fire // all fp instr will write fp rf 226 difftest.address := out.bits.pdest 227 difftest.data := out.bits.data 228 }) 229 } 230 231} 232 233 234 235 236