xref: /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala (revision 4aa0028654716f3ef660f985eb6662c6c75b70d0)
1package xiangshan.backend.datapath
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import difftest.{DiffFpWriteback, DiffIntWriteback, DifftestModule}
7import utils.XSError
8import xiangshan.backend.BackendParams
9import xiangshan.backend.Bundles.{ExuOutput, WriteBackBundle}
10import xiangshan.backend.datapath.DataConfig.{IntData, VecData}
11import xiangshan.backend.regfile.RfWritePortWithConfig
12import xiangshan.{Redirect, XSBundle, XSModule}
13
14class WbArbiterDispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle {
15  val in = Flipped(DecoupledIO(gen))
16
17  val out = Vec(n, DecoupledIO(gen))
18}
19
20class WbArbiterDispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => (Seq[Bool], Bool))
21                           (implicit p: Parameters)
22  extends Module {
23
24  val io = IO(new WbArbiterDispatcherIO(gen, n))
25
26  private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)._1)
27
28  XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ")
29
30  io.out.zipWithIndex.foreach { case (out, i) =>
31    out.valid := acceptVec(i) && io.in.valid
32    out.bits := io.in.bits
33  }
34
35  io.in.ready := Cat(io.out.zip(acceptVec).map{ case(out, canAccept) => out.ready && canAccept}).orR || acceptCond(io.in.bits)._2
36}
37
38class WbArbiterIO()(implicit p: Parameters, params: WbArbiterParams) extends XSBundle {
39  val flush = Flipped(ValidIO(new Redirect))
40  val in: MixedVec[DecoupledIO[WriteBackBundle]] = Flipped(params.genInput)
41  val out: MixedVec[ValidIO[WriteBackBundle]] = params.genOutput
42
43  def inGroup: Map[Int, Seq[DecoupledIO[WriteBackBundle]]] = in.groupBy(_.bits.params.port).map(x => (x._1, x._2.sortBy(_.bits.params.priority).toSeq))
44}
45
46class WbArbiter(params: WbArbiterParams)(implicit p: Parameters) extends XSModule {
47  val io = IO(new WbArbiterIO()(p, params))
48
49  private val inGroup: Map[Int, Seq[DecoupledIO[WriteBackBundle]]] = io.inGroup
50
51  private val arbiters: Seq[Option[RealWBArbiter[WriteBackBundle]]] = Seq.tabulate(params.numOut) { x => {
52    if (inGroup.contains(x)) {
53      Some(Module(new RealWBArbiter(new WriteBackBundle(inGroup.values.head.head.bits.params, backendParams), inGroup(x).length)))
54    } else {
55      None
56    }
57  }}
58
59  arbiters.zipWithIndex.foreach { case (arb, i) =>
60    if (arb.nonEmpty) {
61      arb.get.io.in.zip(inGroup(i)).foreach { case (arbIn, wbIn) =>
62        arbIn <> wbIn
63      }
64    }
65  }
66
67  io.out.zip(arbiters).foreach { case (wbOut, arb) =>
68    if (arb.nonEmpty) {
69      val arbOut = arb.get.io.out
70      arbOut.ready := true.B
71      wbOut.valid := arbOut.valid
72      wbOut.bits := arbOut.bits
73    } else {
74      wbOut := 0.U.asTypeOf(wbOut)
75    }
76  }
77
78  def getInOutMap: Map[Int, Int] = {
79    (params.wbCfgs.indices zip params.wbCfgs.map(_.port)).toMap
80  }
81}
82
83class WbDataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle {
84  val flush = Flipped(ValidIO(new Redirect()))
85
86  val fromTop = new Bundle {
87    val hartId = Input(UInt(8.W))
88  }
89
90  val fromIntExu: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = Flipped(params.intSchdParams.get.genExuOutputDecoupledBundle)
91
92  val fromVfExu: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = Flipped(params.vfSchdParams.get.genExuOutputDecoupledBundle)
93
94  val fromMemExu: MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = Flipped(params.memSchdParams.get.genExuOutputDecoupledBundle)
95
96  val toIntPreg = Flipped(MixedVec(Vec(params.numPregWb(IntData()),
97    new RfWritePortWithConfig(params.intPregParams.dataCfg, params.intPregParams.addrWidth))))
98
99  val toVfPreg = Flipped(MixedVec(Vec(params.numPregWb(VecData()),
100    new RfWritePortWithConfig(params.vfPregParams.dataCfg, params.vfPregParams.addrWidth))))
101
102  val toCtrlBlock = new Bundle {
103    val writeback: MixedVec[ValidIO[ExuOutput]] = params.genWrite2CtrlBundles
104  }
105}
106
107class WbDataPath(params: BackendParams)(implicit p: Parameters) extends XSModule {
108  val io = IO(new WbDataPathIO()(p, params))
109
110  // split
111  val fromExuPre = collection.mutable.Seq() ++ (io.fromIntExu ++ io.fromVfExu ++ io.fromMemExu).flatten
112  val fromExuVld: Seq[DecoupledIO[ExuOutput]] = fromExuPre.filter(_.bits.params.hasVLoadFu).toSeq
113  val vldMgu: Seq[VldMergeUnit] = fromExuVld.map(x => Module(new VldMergeUnit(x.bits.params)))
114  vldMgu.zip(fromExuVld).foreach{ case (mgu, exu) =>
115    mgu.io.flush := io.flush
116    mgu.io.writeback <> exu
117  }
118  val wbReplaceVld = fromExuPre
119  val vldIdx: Seq[Int] = vldMgu.map(x => fromExuPre.indexWhere(_.bits.params == x.params))
120  println("vldIdx: " + vldIdx)
121  vldIdx.zip(vldMgu).foreach{ case (id, wb) =>
122    wbReplaceVld.update(id, wb.io.writebackAfterMerge)
123  }
124  val fromExu = Wire(chiselTypeOf(MixedVecInit(wbReplaceVld.toSeq)))
125
126  // io.fromExuPre ------------------------------------------------------------> fromExu
127  //               \                                                         /
128  //                -> vldMgu.io.writeback -> vldMgu.io.writebackAfterMerge /
129  (fromExu zip wbReplaceVld).foreach { case (sink, source) =>
130    sink.valid := source.valid
131    sink.bits := source.bits
132    source.ready := sink.ready
133  }
134
135  // fromExu -> ArbiterInput
136  val intArbiterInputsWire = Wire(chiselTypeOf(fromExu))
137  val intArbiterInputsWireY = intArbiterInputsWire.filter(_.bits.params.writeIntRf)
138  val intArbiterInputsWireN = intArbiterInputsWire.filterNot(_.bits.params.writeIntRf)
139
140  val vfArbiterInputsWire = Wire(chiselTypeOf(fromExu))
141  val vfArbiterInputsWireY = vfArbiterInputsWire.filter(_.bits.params.writeVfRf)
142  val vfArbiterInputsWireN = vfArbiterInputsWire.filterNot(_.bits.params.writeVfRf)
143
144  def acceptCond(exuOutput: ExuOutput): (Seq[Bool], Bool) = {
145    val intWen = if(exuOutput.intWen.isDefined) exuOutput.intWen.get else false.B
146    val fpwen  = if(exuOutput.fpWen.isDefined) exuOutput.fpWen.get else false.B
147    val vecWen = if(exuOutput.vecWen.isDefined) exuOutput.vecWen.get else false.B
148    (Seq(intWen, fpwen || vecWen), !intWen && !fpwen && !vecWen)
149  }
150
151  intArbiterInputsWire.zip(vfArbiterInputsWire).zip(fromExu).foreach {
152    case ((intArbiterInput, vfArbiterInput), exuOut) =>
153      val writeCond = acceptCond(exuOut.bits)
154      val intWrite = Wire(Bool())
155      val vfWrite = Wire(Bool())
156      val notWrite = Wire(Bool())
157
158      intWrite := exuOut.valid && writeCond._1(0)
159      vfWrite := exuOut.valid && writeCond._1(1)
160      notWrite := writeCond._2
161
162      intArbiterInput.valid := intWrite
163      intArbiterInput.bits := exuOut.bits
164      vfArbiterInput.valid := vfWrite
165      vfArbiterInput.bits := exuOut.bits
166
167      if (exuOut.bits.params.writeIntRf && exuOut.bits.params.isVfExeUnit) {
168        intWrite := RegNext(exuOut.valid && writeCond._1(0))
169        intArbiterInput.bits := RegEnable(exuOut.bits, exuOut.valid)
170      }
171
172      println(s"[WbDataPath] exu: ${exuOut.bits.params.exuIdx}, uncertain: ${exuOut.bits.params.hasUncertainLatency}, certain: ${exuOut.bits.params.latencyCertain}")
173
174      // only EXUs with uncertain latency need result of arbiter
175      // the result data can be maintained until getting success in arbiter
176      if (exuOut.bits.params.hasUncertainLatency) {
177        exuOut.ready := intArbiterInput.ready && intWrite || vfArbiterInput.ready && vfWrite || notWrite
178      } else {
179        exuOut.ready := true.B
180
181        // for EXUs with certain latency, if the request fails in arbiter, the result data will be permanently lost
182        when (intWrite) {
183          assert(intArbiterInput.ready, s"exu ${exuOut.bits.params.exuIdx} failed to write int regfile\n")
184        }
185        when (vfWrite) {
186          assert(vfArbiterInput.ready, s"exu ${exuOut.bits.params.exuIdx} failed to write vf regfile\n")
187        }
188      }
189      // the ports not writting back pregs are always ready
190      // the ports set highest priority are always ready
191      if (exuOut.bits.params.hasNoDataWB || exuOut.bits.params.isHighestWBPriority) {
192        exuOut.ready := true.B
193      }
194  }
195  intArbiterInputsWireN.foreach(_.ready := false.B)
196  vfArbiterInputsWireN.foreach(_.ready := false.B)
197
198  println(s"[WbDataPath] write int preg: " +
199    s"IntExu(${io.fromIntExu.flatten.count(_.bits.params.writeIntRf)}) " +
200    s"VfExu(${io.fromVfExu.flatten.count(_.bits.params.writeIntRf)}) " +
201    s"MemExu(${io.fromMemExu.flatten.count(_.bits.params.writeIntRf)})"
202  )
203  println(s"[WbDataPath] write vf preg: " +
204    s"IntExu(${io.fromIntExu.flatten.count(_.bits.params.writeVfRf)}) " +
205    s"VfExu(${io.fromVfExu.flatten.count(_.bits.params.writeVfRf)}) " +
206    s"MemExu(${io.fromMemExu.flatten.count(_.bits.params.writeVfRf)})"
207  )
208
209  // wb arbiter
210  private val intWbArbiter = Module(new WbArbiter(params.getIntWbArbiterParams))
211  private val vfWbArbiter = Module(new WbArbiter(params.getVfWbArbiterParams))
212  println(s"[WbDataPath] int preg write back port num: ${intWbArbiter.io.out.size}, active port: ${intWbArbiter.io.inGroup.keys.toSeq.sorted}")
213  println(s"[WbDataPath] vf preg write back port num: ${vfWbArbiter.io.out.size}, active port: ${vfWbArbiter.io.inGroup.keys.toSeq.sorted}")
214
215  // module assign
216  intWbArbiter.io.flush <> io.flush
217  require(intWbArbiter.io.in.size == intArbiterInputsWireY.size, s"intWbArbiter input size: ${intWbArbiter.io.in.size}, all vf wb size: ${intArbiterInputsWireY.size}")
218  intWbArbiter.io.in.zip(intArbiterInputsWireY).foreach { case (arbiterIn, in) =>
219    arbiterIn.valid := in.valid && in.bits.intWen.get
220    in.ready := arbiterIn.ready
221    arbiterIn.bits.fromExuOutput(in.bits)
222  }
223  private val intWbArbiterOut = intWbArbiter.io.out
224
225  vfWbArbiter.io.flush <> io.flush
226  require(vfWbArbiter.io.in.size == vfArbiterInputsWireY.size, s"vfWbArbiter input size: ${vfWbArbiter.io.in.size}, all vf wb size: ${vfArbiterInputsWireY.size}")
227  vfWbArbiter.io.in.zip(vfArbiterInputsWireY).foreach { case (arbiterIn, in) =>
228    arbiterIn.valid := in.valid && (in.bits.fpWen.getOrElse(false.B) || in.bits.vecWen.getOrElse(false.B))
229    in.ready := arbiterIn.ready
230    arbiterIn.bits.fromExuOutput(in.bits)
231  }
232  private val vfWbArbiterOut = vfWbArbiter.io.out
233
234  // WB -> CtrlBlock
235  private val intExuInputs = io.fromIntExu.flatten.toSeq
236  private val intExuWBs = WireInit(MixedVecInit(intExuInputs))
237  private val vfExuInputs = io.fromVfExu.flatten.toSeq
238  private val vfExuWBs = WireInit(MixedVecInit(vfExuInputs))
239  private val memExuInputs = io.fromMemExu.flatten.toSeq
240  private val memExuWBs = WireInit(MixedVecInit(memExuInputs))
241
242  // only fired port can write back to ctrl block
243  (intExuWBs zip intExuInputs).foreach { case (wb, input) => wb.valid := input.fire }
244  (vfExuWBs zip vfExuInputs).foreach { case (wb, input) => wb.valid := input.fire }
245  (memExuWBs zip memExuInputs).foreach { case (wb, input) => wb.valid := input.fire }
246
247  // io assign
248  private val toIntPreg: MixedVec[RfWritePortWithConfig] = MixedVecInit(intWbArbiterOut.map(x => x.bits.asIntRfWriteBundle(x.fire)).toSeq)
249  private val toVfPreg: MixedVec[RfWritePortWithConfig] = MixedVecInit(vfWbArbiterOut.map(x => x.bits.asVfRfWriteBundle(x.fire)).toSeq)
250
251  private val wb2Ctrl = intExuWBs ++ vfExuWBs ++ memExuWBs
252
253  io.toIntPreg := toIntPreg
254  io.toVfPreg := toVfPreg
255  io.toCtrlBlock.writeback.zip(wb2Ctrl).foreach { case (sink, source) =>
256    sink.valid := source.valid
257    sink.bits := source.bits
258    source.ready := true.B
259  }
260
261  // debug
262  if(backendParams.debugEn) {
263    dontTouch(intArbiterInputsWire)
264    dontTouch(vfArbiterInputsWire)
265  }
266
267  // difftest
268  if (env.EnableDifftest || env.AlwaysBasicDiff) {
269    intWbArbiterOut.foreach(out => {
270      val difftest = DifftestModule(new DiffIntWriteback(IntPhyRegs))
271      difftest.coreid := io.fromTop.hartId
272      difftest.valid := out.fire && out.bits.rfWen
273      difftest.address := out.bits.pdest
274      difftest.data := out.bits.data
275    })
276  }
277
278  if (env.EnableDifftest || env.AlwaysBasicDiff) {
279    vfWbArbiterOut.foreach(out => {
280      val difftest = DifftestModule(new DiffFpWriteback(VfPhyRegs))
281      difftest.coreid := io.fromTop.hartId
282      difftest.valid := out.fire // all fp instr will write fp rf
283      difftest.address := out.bits.pdest
284      difftest.data := out.bits.data
285    })
286  }
287
288}
289
290
291
292
293