1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan._ 7import xiangshan.backend.Bundles.{ExuOutput, MemExuOutput} 8import xiangshan.backend.exu.ExeUnitParams 9import xiangshan.backend.fu.vector.{ByteMaskTailGen, Mgu, VecInfo} 10import yunsuan.vector.SewOH 11 12class VldMergeUnit(val params: ExeUnitParams)(implicit p: Parameters) extends XSModule { 13 val io = IO(new VldMergeUnitIO(params)) 14 15 io.writeback.ready := io.writebackAfterMerge.ready 16 // [WARNING] MemBlock cannot provide oldVdPsrc!!! 17 io.oldVdReadAddr := io.writeback.bits.vls.get.oldVdPsrc 18 val wbReg = Reg(Valid(new ExuOutput(params))) 19 val mgu = Module(new Mgu(VLEN)) 20 val vdAfterMerge = Wire(UInt(VLEN.W)) 21 22 val wbFire = !io.writeback.bits.robIdx.needFlush(io.flush) && io.writeback.fire 23 wbReg.bits := Mux(wbFire, io.writeback.bits, wbReg.bits) 24 wbReg.valid := wbFire 25 mgu.io.in.vd := wbReg.bits.data 26 // oldVd is contained in data and is already masked with new data 27 mgu.io.in.oldVd := wbReg.bits.data 28 mgu.io.in.mask := wbReg.bits.vls.get.vpu.vmask 29 mgu.io.in.info.valid := wbReg.valid 30 mgu.io.in.info.ta := wbReg.bits.vls.get.vpu.vta 31 mgu.io.in.info.ma := wbReg.bits.vls.get.vpu.vma 32 mgu.io.in.info.vl := wbReg.bits.vls.get.vpu.vl 33 mgu.io.in.info.vstart := wbReg.bits.vls.get.vpu.vstart 34 mgu.io.in.info.eew := wbReg.bits.vls.get.vpu.veew 35 mgu.io.in.info.vsew := wbReg.bits.vls.get.vpu.vsew 36 mgu.io.in.info.vdIdx := wbReg.bits.vls.get.vdIdxInField 37 mgu.io.in.info.vlmul := wbReg.bits.vls.get.vpu.vlmul 38 mgu.io.in.info.narrow := false.B // never narrow 39 mgu.io.in.info.dstMask := false.B // vlm need not mask 40 mgu.io.in.isIndexedVls := wbReg.bits.vls.get.isIndexed 41 42 vdAfterMerge := mgu.io.out.vd 43 44 io.writebackAfterMerge.valid := wbReg.valid 45 io.writebackAfterMerge.bits := wbReg.bits 46 io.writebackAfterMerge.bits.vecWen.foreach(_ := wbReg.bits.vecWen.get) 47 io.writebackAfterMerge.bits.data := vdAfterMerge 48} 49 50class VldMergeUnitIO(param: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 51 val flush = Flipped(ValidIO(new Redirect)) 52 val writeback = Flipped(DecoupledIO(new ExuOutput(param))) 53 val oldVdReadData = Input(UInt(VLEN.W)) 54 val oldVdReadAddr = Output(UInt(PhyRegIdxWidth.W)) 55 val writebackAfterMerge = DecoupledIO(new ExuOutput(param)) 56}