xref: /XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala (revision 83ba63b34cf09b33c0a9e1b3203138e51af4491b) 
1package xiangshan.backend.datapath
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utils.OptionWrapper
7import utils.SeqUtils.MixedVec2
8import xiangshan.backend.BackendParams
9import xiangshan.backend.datapath.DataConfig.{IntData, VecData}
10import xiangshan.backend.datapath.WbConfig.{NoWB, PregWB}
11import xiangshan.backend.regfile.PregParams
12
13case class RFWBCollideCheckerParams (
14  inWbCfgs: Seq[Seq[Set[PregWB]]],
15  pregParams: PregParams,
16) {
17  def genInputBundle: MixedVec2[DecoupledIO[RFWBCollideCheckerBundle]] = {
18    val pregWidth = pregParams.addrWidth
19    utils.SeqUtils.mapToMixedVec2(this.filteredCfgs, (wb: PregWB) => DecoupledIO(new RFWBCollideCheckerBundle(wb, pregWidth)))
20  }
21
22  def filteredCfgs: Seq[Seq[PregWB]] = inWbCfgs.map(_.map(x =>
23    if (x.map(_.dataCfg).contains(pregParams.dataCfg))
24      x.find(x => x.dataCfg == pregParams.dataCfg).get
25    else
26      NoWB()
27  ))
28
29  def portMax = filteredCfgs.flatten.map(_.port).max
30}
31
32class RFWBCollideCheckerBundle(var wbCfg: Option[PregWB], pregWidth: Int) extends Bundle {
33
34  def this(wbCfg_ : PregWB, pregWidth_ : Int) = this(Some(wbCfg_), pregWidth_)
35
36  def this(pregWidth_ : Int) = this(None, pregWidth_)
37}
38
39class RFWBCollideCheckerIO(val params: RFWBCollideCheckerParams)(implicit p: Parameters) extends Bundle {
40  private val pregWidth = params.pregParams.addrWidth
41  val in: MixedVec2[DecoupledIO[RFWBCollideCheckerBundle]] = Flipped(params.genInputBundle)
42  val out = Vec(params.portMax + 1, Valid(new RFWBCollideCheckerBundle(pregWidth)))
43}
44
45abstract class RFWBCollideCheckerBase(params: RFWBCollideCheckerParams)(implicit p: Parameters) extends Module {
46  protected def portRange: Range
47
48  val io = IO(new RFWBCollideCheckerIO(params))
49  dontTouch(io)
50
51  protected val pregParams = params.pregParams
52  protected val pregWidth = pregParams.addrWidth
53
54  protected val inGroup = io.in
55    .flatten
56    .groupBy(_.bits.wbCfg.get.port)
57    .map(x => (x._1, x._2.sortBy(_.bits.wbCfg.get.priority)))
58
59  protected val arbiters: Seq[Option[Arbiter[RFWBCollideCheckerBundle]]] = portRange.map { portIdx =>
60    OptionWrapper(
61      inGroup.isDefinedAt(portIdx),
62      Module(new Arbiter(
63        new RFWBCollideCheckerBundle(pregWidth),
64        inGroup(portIdx).size
65      ))
66    )
67  }
68
69  // connection of IntWB or VfWB
70  arbiters.zipWithIndex.foreach { case (arb, portIdx) =>
71    if (arb.nonEmpty) {
72      arb.get.io.in.zip(inGroup(portIdx)).foreach { case (arbiterIn, ioIn) =>
73        arbiterIn <> ioIn
74      }
75    }
76  }
77
78  // connection of NoWB
79  io.in.map(_.map(x =>
80    if (x.bits.wbCfg.get.isInstanceOf[NoWB]) {
81      x.ready := true.B
82    }
83  ))
84
85  io.out.zip(arbiters).foreach { case (out, arb) =>
86    if (arb.nonEmpty) {
87      val arbOut = arb.get.io.out
88      arbOut.ready := true.B
89      out.valid := arbOut.valid
90      out.bits := arbOut.bits
91    } else {
92      out := 0.U.asTypeOf(out)
93    }
94  }
95}
96
97class IntRFWBCollideChecker(
98  backendParams: BackendParams
99)(implicit
100  p:Parameters
101) extends RFWBCollideCheckerBase(RFWBCollideCheckerParams(backendParams.getAllWbCfgs, backendParams.intPregParams)) {
102  override protected def portRange: Range = 0 to backendParams.getWbPortIndices(IntData()).max
103}
104
105class VfRFWBCollideChecker(
106  backendParams: BackendParams
107)(implicit
108  p:Parameters
109) extends RFWBCollideCheckerBase(RFWBCollideCheckerParams(backendParams.getAllWbCfgs, backendParams.vfPregParams)) {
110  override protected def portRange: Range = 0 to backendParams.getWbPortIndices(VecData()).max
111}
112