xref: /XiangShan/src/main/scala/xiangshan/backend/datapath/Og2ForVector.scala (revision bb2f3f51dd67f6e16e0cc1ffe43368c9fc7e4aef) 
1package xiangshan.backend.datapath
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility._
7import xiangshan._
8import xiangshan.backend.BackendParams
9import xiangshan.backend.Bundles._
10import xiangshan.backend.issue.EntryBundles.{EntryDeqRespBundle, RespType}
11import xiangshan.backend.issue.VfScheduler
12
13
14class Og2ForVector(params: BackendParams)(implicit p: Parameters) extends XSModule {
15  val io = IO(new Og2ForVectorIO(params))
16
17  private val s1_validVec2        = io.fromOg1NoReg.map(_.map(_.valid))
18  private val s1_dataVec2         = io.fromOg1NoReg.map(_.map(_.bits))
19  private val s1_readyVec2        = io.fromOg1NoReg.map(_.map(_.ready))
20  private val toVfExuFire         = io.toVfExu.map(_.map(_.fire))
21  private val toVfExuReady        = io.toVfExu.map(_.map(_.ready))
22  private val vfIQNum: Int        = io.fromOg1NoReg.size
23  private val vfIQPerExuNum       = io.fromOg1NoReg.map(_.size).toSeq
24
25  val s2_toVfExuValid             = Reg(MixedVec(
26    s1_validVec2.map(x => MixedVec(x.map(_.cloneType).toSeq)).toSeq
27  ))
28  val s2_toVfExuData              = Reg(MixedVec(
29    s1_dataVec2.map(x => MixedVec(x.map(_.cloneType).toSeq)).toSeq
30  ))
31
32  for(i <- 0 until vfIQNum) {
33    for (j <- 0 until vfIQPerExuNum(i)) {
34      val s2_flush = s1_dataVec2(i)(j).robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush)))
35      val og2Failed = s2_toVfExuValid(i)(j) && !toVfExuFire(i)(j)
36      val s1_ldCancel = LoadShouldCancel(s1_dataVec2(i)(j).loadDependency, io.ldCancel)
37      when(s1_validVec2(i)(j) && s1_readyVec2(i)(j) && !s2_flush && !og2Failed && !s1_ldCancel) {
38        s2_toVfExuValid(i)(j) := s1_validVec2(i)(j)
39        s2_toVfExuData(i)(j) := s1_dataVec2(i)(j)
40        s2_toVfExuData(i)(j).loadDependency.foreach(_ := s1_dataVec2(i)(j).loadDependency.get.map(_ << 1))
41      }.otherwise {
42        s2_toVfExuValid(i)(j) := false.B
43      }
44      s1_readyVec2(i)(j) := (toVfExuReady(i)(j) || !s1_validVec2(i)(j)) && !og2Failed && !s1_ldCancel
45      io.toVfExu(i)(j).valid := s2_toVfExuValid(i)(j)
46      io.toVfExu(i)(j).bits := s2_toVfExuData(i)(j)
47    }
48  }
49  io.toVfIQ.zipWithIndex.foreach {
50    case (toVfExu, iqId) =>
51      toVfExu.zipWithIndex.foreach {
52        case (og2Resp, exuId) =>
53          val og2Failed = s2_toVfExuValid(iqId)(exuId) && !toVfExuFire(iqId)(exuId)
54          og2Resp.valid := s2_toVfExuValid(iqId)(exuId)
55          og2Resp.bits.robIdx := s2_toVfExuData(iqId)(exuId).robIdx
56          og2Resp.bits.uopIdx.foreach(_ := s2_toVfExuData(iqId)(exuId).vpu.get.vuopIdx)
57          og2Resp.bits.resp := Mux(og2Failed, RespType.block, RespType.success)
58          og2Resp.bits.fuType := s2_toVfExuData(iqId)(exuId).fuType
59      }
60  }
61  io.toVfImmInfo := io.fromOg1ImmInfo.zip(s1_validVec2.flatten).map{
62    case (imm, valid) => RegEnable(imm, valid)
63  }
64}
65
66class Og2ForVectorIO(params: BackendParams)(implicit p: Parameters) extends XSBundle {
67  private val vfSchdParams = params.schdParams(VfScheduler())
68
69  val flush: ValidIO[Redirect]                                    = Flipped(ValidIO(new Redirect))
70  val ldCancel                                                    = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
71  val fromOg1NoReg: MixedVec[MixedVec[DecoupledIO[ExuInput]]]     = Flipped(vfSchdParams.genExuInputBundle)
72  val fromOg1ImmInfo: Vec[ImmInfo]                                = Input(Vec(params.allExuParams.filter(_.isVfExeUnit).size, new ImmInfo))
73  val toVfExu                                                     = MixedVec(vfSchdParams.genExuInputBundle)
74  val toVfIQ                                                      = MixedVec(vfSchdParams.issueBlockParams.map(_.genOG2RespBundle))
75  val toVfImmInfo: Vec[ImmInfo]                                   = Output(Vec(params.allExuParams.filter(_.isVfExeUnit).size, new ImmInfo))
76}