1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule} 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility._ 9import utils.SeqUtils._ 10import utils._ 11import xiangshan._ 12import xiangshan.backend.BackendParams 13import xiangshan.backend.Bundles._ 14import xiangshan.backend.decode.ImmUnion 15import xiangshan.backend.datapath.DataConfig._ 16import xiangshan.backend.datapath.RdConfig._ 17import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler, FpScheduler} 18import xiangshan.backend.issue.EntryBundles._ 19import xiangshan.backend.regfile._ 20import xiangshan.backend.PcToDataPathIO 21import xiangshan.backend.fu.FuType.is0latency 22 23class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { 24 override def shouldBeInlined: Boolean = false 25 26 private implicit val dpParams: BackendParams = params 27 lazy val module = new DataPathImp(this) 28 29 println(s"[DataPath] Preg Params: ") 30 println(s"[DataPath] Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ") 31 println(s"[DataPath] Fp R(${params.getRfReadSize(FpData())}), W(${params.getRfWriteSize(FpData())}) ") 32 println(s"[DataPath] Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ") 33 println(s"[DataPath] V0 R(${params.getRfReadSize(V0Data())}), W(${params.getRfWriteSize(V0Data())}) ") 34 println(s"[DataPath] Vl R(${params.getRfReadSize(VlData())}), W(${params.getRfWriteSize(VlData())}) ") 35} 36 37class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams) 38 extends LazyModuleImp(wrapper) with HasXSParameter { 39 40 val io = IO(new DataPathIO()) 41 42 private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu) 43 private val (fromFpIQ, toFpIQ, toFpExu) = (io.fromFpIQ, io.toFpIQ, io.toFpExu) 44 private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu) 45 private val (fromVfIQ, toVfIQ, toVfExu ) = (io.fromVfIQ, io.toVfIQ, io.toVecExu) 46 47 println(s"[DataPath] IntIQ(${fromIntIQ.size}), FpIQ(${fromFpIQ.size}), VecIQ(${fromVfIQ.size}), MemIQ(${fromMemIQ.size})") 48 println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), FpExu(${fromFpIQ.map(_.size).sum}), VecExu(${fromVfIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})") 49 50 // just refences for convience 51 private val fromIQ: Seq[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = (fromIntIQ ++ fromFpIQ ++ fromVfIQ ++ fromMemIQ).toSeq 52 53 private val toIQs = toIntIQ ++ toFpIQ ++ toVfIQ ++ toMemIQ 54 55 private val toExu: Seq[MixedVec[DecoupledIO[ExuInput]]] = (toIntExu ++ toFpExu ++ toVfExu ++ toMemExu).toSeq 56 57 private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten 58 59 private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten 60 61 private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams)) 62 private val fpWbBusyArbiter = Module(new FpRFWBCollideChecker(backendParams)) 63 private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams)) 64 private val v0WbBusyArbiter = Module(new V0RFWBCollideChecker(backendParams)) 65 private val vlWbBusyArbiter = Module(new VlRFWBCollideChecker(backendParams)) 66 67 private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams)) 68 private val fpRFReadArbiter = Module(new FpRFReadArbiter(backendParams)) 69 private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams)) 70 private val v0RFReadArbiter = Module(new V0RFReadArbiter(backendParams)) 71 private val vlRFReadArbiter = Module(new VlRFReadArbiter(backendParams)) 72 73 private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 74 private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 75 76 // port -> win 77 private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 78 private val fpRdArbWinner: Seq2[MixedVec[Bool]] = fpRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 79 private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 80 private val v0RdArbWinner: Seq2[MixedVec[Bool]] = v0RFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 81 private val vlRdArbWinner: Seq2[MixedVec[Bool]] = vlRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 82 83 private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 84 private val fpWbNotBlock: Seq[MixedVec[Bool]] = fpWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 85 private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 86 private val v0WbNotBlock: Seq[MixedVec[Bool]] = v0WbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 87 private val vlWbNotBlock: Seq[MixedVec[Bool]] = vlWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 88 89 private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR)) 90 private val fpRdNotBlock: Seq2[Bool] = fpRdArbWinner.map(_.map(_.asUInt.andR)) 91 private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR)) 92 private val v0RdNotBlock: Seq2[Bool] = v0RdArbWinner.map(_.map(_.asUInt.andR)) 93 private val vlRdNotBlock: Seq2[Bool] = vlRdArbWinner.map(_.map(_.asUInt.andR)) 94 95 private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 96 private val fpRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 97 private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 98 private val v0RFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 99 private val vlRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 100 101 private val allDataSources: Seq[Seq[Vec[DataSource]]] = fromIQ.map(x => x.map(xx => xx.bits.common.dataSources).toSeq) 102 private val allNumRegSrcs: Seq[Seq[Int]] = fromIQ.map(x => x.map(xx => xx.bits.exuParams.numRegSrc).toSeq) 103 104 intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 105 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 106 val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData()) 107 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 108 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 109 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 110 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 111// if (allNumRegSrcs(iqIdx)(exuIdx) == 2) { 112// val src0Req = inRFReadReqSeq(0).valid && allDataSources(iqIdx)(exuIdx)(0).readReg 113// val src1Req = inRFReadReqSeq(1).valid && allDataSources(iqIdx)(exuIdx)(1).readReg 114// if (srcIdx == 0) { 115// arbInSeq(srcIdx).valid := src0Req || src1Req 116// arbInSeq(srcIdx).bits.addr := Mux(src1Req && !src0Req, inRFReadReqSeq(1).bits.addr,inRFReadReqSeq(0).bits.addr) 117// } else { 118// arbInSeq(srcIdx).valid := src0Req && src1Req 119// arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 120// } 121// } else { 122// arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 123// arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 124// } 125 } else { 126 arbInSeq(srcIdx).valid := false.B 127 arbInSeq(srcIdx).bits.addr := 0.U 128 } 129 } 130 } 131 } 132 fpRFReadArbiter.io.in.zip(fpRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 133 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 134 val srcIndices: Seq[Int] = FpRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 135 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 136 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 137 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 138 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 139 } else { 140 arbInSeq(srcIdx).valid := false.B 141 arbInSeq(srcIdx).bits.addr := 0.U 142 } 143 } 144 } 145 } 146 147 vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 148 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 149 val srcIndices: Seq[Int] = VecRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 150 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 151 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 152 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 153 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 154 } else { 155 arbInSeq(srcIdx).valid := false.B 156 arbInSeq(srcIdx).bits.addr := 0.U 157 } 158 } 159 } 160 } 161 162 v0RFReadArbiter.io.in.zip(v0RFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 163 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 164 val srcIndices: Seq[Int] = V0RegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 165 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 166 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 167 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 168 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 169 } else { 170 arbInSeq(srcIdx).valid := false.B 171 arbInSeq(srcIdx).bits.addr := 0.U 172 } 173 } 174 } 175 } 176 177 vlRFReadArbiter.io.in.zip(vlRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 178 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 179 val srcIndices: Seq[Int] = VlRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 180 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 181 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 182 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 183 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 184 } else { 185 arbInSeq(srcIdx).valid := false.B 186 arbInSeq(srcIdx).bits.addr := 0.U 187 } 188 } 189 } 190 } 191 192 private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B)).toSeq).toSeq 193 private val fpRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.fpWen.getOrElse(false.B)).toSeq).toSeq 194 private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.vecWen.getOrElse(false.B)).toSeq).toSeq 195 private val v0RFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.v0Wen.getOrElse(false.B)).toSeq).toSeq 196 private val vlRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.vlWen.getOrElse(false.B)).toSeq).toSeq 197 198 intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 199 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 200 arbIn.valid := inRFWriteReq 201 } 202 } 203 204 fpWbBusyArbiter.io.in.zip(fpRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 205 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 206 arbIn.valid := inRFWriteReq 207 } 208 } 209 210 vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 211 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 212 arbIn.valid := inRFWriteReq 213 } 214 } 215 216 v0WbBusyArbiter.io.in.zip(v0RFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 217 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 218 arbIn.valid := inRFWriteReq 219 } 220 } 221 222 vlWbBusyArbiter.io.in.zip(vlRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 223 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 224 arbIn.valid := inRFWriteReq 225 } 226 } 227 228 private val intSchdParams = params.schdParams(IntScheduler()) 229 private val fpSchdParams = params.schdParams(FpScheduler()) 230 private val vfSchdParams = params.schdParams(VfScheduler()) 231 private val memSchdParams = params.schdParams(MemScheduler()) 232 233 private val schdParams = params.allSchdParams 234 235 private val pcReadValid = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathValid)) 236 private val pcReadFtqPtr = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqPtr)) 237 private val pcReadFtqOffset = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqOffset)) 238 private val targetPCRdata = io.fromPcTargetMem.toDataPathTargetPC 239 private val pcRdata = io.fromPcTargetMem.toDataPathPC 240 private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W))) 241 private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W))) 242 private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool())) 243 private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W))) 244 private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W))) 245 246 private val fpRfRaddr = Wire(Vec(params.numPregRd(FpData()), UInt(fpSchdParams.pregIdxWidth.W))) 247 private val fpRfRdata = Wire(Vec(params.numPregRd(FpData()), UInt(fpSchdParams.rfDataWidth.W))) 248 private val fpRfWen = Wire(Vec(io.fromFpWb.length, Bool())) 249 private val fpRfWaddr = Wire(Vec(io.fromFpWb.length, UInt(fpSchdParams.pregIdxWidth.W))) 250 private val fpRfWdata = Wire(Vec(io.fromFpWb.length, UInt(fpSchdParams.rfDataWidth.W))) 251 252 private val vfRfSplitNum = VLEN / XLEN 253 private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W))) 254 private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W))) 255 private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool()))) 256 private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W))) 257 private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W))) 258 259 private val v0RfSplitNum = VLEN / XLEN 260 private val v0RfRaddr = Wire(Vec(params.numPregRd(V0Data()), UInt(log2Up(V0PhyRegs).W))) 261 private val v0RfRdata = Wire(Vec(params.numPregRd(V0Data()), UInt(V0Data().dataWidth.W))) 262 private val v0RfWen = Wire(Vec(v0RfSplitNum, Vec(io.fromV0Wb.length, Bool()))) 263 private val v0RfWaddr = Wire(Vec(io.fromV0Wb.length, UInt(log2Up(V0PhyRegs).W))) 264 private val v0RfWdata = Wire(Vec(io.fromV0Wb.length, UInt(V0Data().dataWidth.W))) 265 266 private val vlRfRaddr = Wire(Vec(params.numPregRd(VlData()), UInt(log2Up(VlPhyRegs).W))) 267 private val vlRfRdata = Wire(Vec(params.numPregRd(VlData()), UInt(VlData().dataWidth.W))) 268 private val vlRfWen = Wire(Vec(io.fromVlWb.length, Bool())) 269 private val vlRfWaddr = Wire(Vec(io.fromVlWb.length, UInt(log2Up(VlPhyRegs).W))) 270 private val vlRfWdata = Wire(Vec(io.fromVlWb.length, UInt(VlData().dataWidth.W))) 271 272 val pcReadFtqPtrFormIQ = fromIntIQ.flatten.filter(x => x.bits.exuParams.needPc) 273 assert(pcReadFtqPtrFormIQ.size == pcReadFtqPtr.size, s"pcReadFtqPtrFormIQ.size ${pcReadFtqPtrFormIQ.size} not equal pcReadFtqPtr.size ${pcReadFtqPtr.size}") 274 pcReadValid.zip(pcReadFtqPtrFormIQ.map(_.valid)).map(x => x._1 := x._2) 275 pcReadFtqPtr.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqIdx.get)).map(x => x._1 := x._2) 276 pcReadFtqOffset.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqOffset.get)).map(x => x._1 := x._2) 277 io.fromPcTargetMem.fromDataPathValid := pcReadValid 278 io.fromPcTargetMem.fromDataPathFtqPtr := pcReadFtqPtr 279 io.fromPcTargetMem.fromDataPathFtqOffset := pcReadFtqOffset 280 281 private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] = 282 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W))))) 283 private val fpDebugRead: Option[(Vec[UInt], Vec[UInt])] = 284 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(32, UInt(fpSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W))))) 285 private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] = 286 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(31, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(31, UInt(VLEN.W))))) 287 private val v0DebugRead: Option[(Vec[UInt], Vec[UInt])] = 288 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(1, UInt(log2Up(V0PhyRegs).W))), Wire(Vec(1, UInt(V0Data().dataWidth.W))))) 289 private val vlDebugRead: Option[(Vec[UInt], Vec[UInt])] = 290 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(1, UInt(log2Up(VlPhyRegs).W))), Wire(Vec(1, UInt(VlData().dataWidth.W))))) 291 292 private val fpDebugReadData: Option[Vec[UInt]] = 293 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, Wire(Vec(32, UInt(XLEN.W)))) 294 private val vecDebugReadData: Option[Vec[UInt]] = 295 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0)) 296 private val vlDebugReadData: Option[UInt] = 297 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, Wire(UInt(VlData().dataWidth.W))) 298 299 300 fpDebugReadData.foreach(_ := fpDebugRead 301 .get._2 302 .slice(0, 32) 303 .map(_(63, 0)) 304 ) // fp only used [63, 0] 305 vecDebugReadData.foreach(_ := 306 v0DebugRead 307 .get._2 308 .slice(0, 1) 309 .map(x => Seq(x(63, 0), x(127, 64))).flatten ++ 310 vfDebugRead 311 .get._2 312 .slice(0, 31) 313 .map(x => Seq(x(63, 0), x(127, 64))).flatten 314 ) 315 vlDebugReadData.foreach(_ := vlDebugRead 316 .get._2(0) 317 ) 318 319 io.debugVl.foreach(_ := vlDebugReadData.get) 320 321 IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata, 322 bankNum = 1, 323 debugReadAddr = intDebugRead.map(_._1), 324 debugReadData = intDebugRead.map(_._2) 325 ) 326 FpRegFile("FpRegFile", fpSchdParams.numPregs, fpRfRaddr, fpRfRdata, fpRfWen, fpRfWaddr, fpRfWdata, 327 bankNum = 1, 328 debugReadAddr = fpDebugRead.map(_._1), 329 debugReadData = fpDebugRead.map(_._2) 330 ) 331 VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata, 332 debugReadAddr = vfDebugRead.map(_._1), 333 debugReadData = vfDebugRead.map(_._2) 334 ) 335 VfRegFile("V0RegFile", V0PhyRegs, v0RfSplitNum, v0RfRaddr, v0RfRdata, v0RfWen, v0RfWaddr, v0RfWdata, 336 debugReadAddr = v0DebugRead.map(_._1), 337 debugReadData = v0DebugRead.map(_._2) 338 ) 339 FpRegFile("VlRegFile", VlPhyRegs, vlRfRaddr, vlRfRdata, vlRfWen, vlRfWaddr, vlRfWdata, 340 bankNum = 1, 341 debugReadAddr = vlDebugRead.map(_._1), 342 debugReadData = vlDebugRead.map(_._2) 343 ) 344 345 intRfWaddr := io.fromIntWb.map(x => RegEnable(x.addr, x.wen)).toSeq 346 intRfWdata := io.fromIntWb.map(x => RegEnable(x.data, x.wen)).toSeq 347 intRfWen := RegNext(VecInit(io.fromIntWb.map(_.wen).toSeq)) 348 349 for (portIdx <- intRfRaddr.indices) { 350 if (intRFReadArbiter.io.out.isDefinedAt(portIdx)) 351 intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr 352 else 353 intRfRaddr(portIdx) := 0.U 354 } 355 356 fpRfWaddr := io.fromFpWb.map(x => RegEnable(x.addr, x.wen)).toSeq 357 fpRfWdata := io.fromFpWb.map(x => RegEnable(x.data, x.wen)).toSeq 358 fpRfWen := RegNext(VecInit(io.fromFpWb.map(_.wen).toSeq)) 359 360 for (portIdx <- fpRfRaddr.indices) { 361 if (fpRFReadArbiter.io.out.isDefinedAt(portIdx)) 362 fpRfRaddr(portIdx) := fpRFReadArbiter.io.out(portIdx).bits.addr 363 else 364 fpRfRaddr(portIdx) := 0.U 365 } 366 367 vfRfWaddr := io.fromVfWb.map(x => RegEnable(x.addr, x.wen)).toSeq 368 vfRfWdata := io.fromVfWb.map(x => RegEnable(x.data, x.wen)).toSeq 369 vfRfWen.foreach(_.zip(io.fromVfWb.map(x => RegNext(x.wen))).foreach { case (wenSink, wenSource) => wenSink := wenSource } ) 370 371 for (portIdx <- vfRfRaddr.indices) { 372 if (vfRFReadArbiter.io.out.isDefinedAt(portIdx)) 373 vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr 374 else 375 vfRfRaddr(portIdx) := 0.U 376 } 377 378 v0RfWaddr := io.fromV0Wb.map(_.addr).toSeq 379 v0RfWdata := io.fromV0Wb.map(_.data).toSeq 380 v0RfWen.foreach(_.zip(io.fromV0Wb.map(_.wen)).foreach { case (wenSink, wenSource) => wenSink := wenSource } ) 381 382 for (portIdx <- v0RfRaddr.indices) { 383 if (v0RFReadArbiter.io.out.isDefinedAt(portIdx)) 384 v0RfRaddr(portIdx) := v0RFReadArbiter.io.out(portIdx).bits.addr 385 else 386 v0RfRaddr(portIdx) := 0.U 387 } 388 389 vlRfWaddr := io.fromVlWb.map(_.addr).toSeq 390 vlRfWdata := io.fromVlWb.map(_.data).toSeq 391 vlRfWen := io.fromVlWb.map(_.wen).toSeq 392 393 for (portIdx <- vlRfRaddr.indices) { 394 if (vlRFReadArbiter.io.out.isDefinedAt(portIdx)) 395 vlRfRaddr(portIdx) := vlRFReadArbiter.io.out(portIdx).bits.addr 396 else 397 vlRfRaddr(portIdx) := 0.U 398 } 399 400 401 intDebugRead.foreach { case (addr, _) => 402 addr := io.debugIntRat.get 403 } 404 405 fpDebugRead.foreach { case (addr, _) => 406 addr := io.debugFpRat.get 407 } 408 409 vfDebugRead.foreach { case (addr, _) => 410 addr := io.debugVecRat.get 411 } 412 v0DebugRead.foreach { case (addr, _) => 413 addr := VecInit(io.debugV0Rat.get) 414 } 415 vlDebugRead.foreach { case (addr, _) => 416 addr := VecInit(io.debugVlRat.get) 417 } 418 419 println(s"[DataPath] " + 420 s"has intDebugRead: ${intDebugRead.nonEmpty}, " + 421 s"has fpDebugRead: ${fpDebugRead.nonEmpty}, " + 422 s"has vecDebugRead: ${vfDebugRead.nonEmpty}, " + 423 s"has v0DebugRead: ${v0DebugRead.nonEmpty}, " + 424 s"has vlDebugRead: ${vlDebugRead.nonEmpty}") 425 426 val s1_addrOHs = Reg(MixedVec( 427 fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType).toSeq)).toSeq 428 )) 429 val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec( 430 toExu.map(x => MixedVec(x.map(_.valid.cloneType).toSeq)).toSeq 431 )) 432 val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType).toSeq)).toSeq)) 433 val s1_immInfo = Reg(MixedVec(toExu.map(x => MixedVec(x.map(x => new ImmInfo).toSeq)).toSeq)) 434 s1_immInfo.zip(fromIQ).map { case (s1Vec, s0Vec) => 435 s1Vec.zip(s0Vec).map { case (s1, s0) => 436 s1.imm := Mux(s0.valid, s0.bits.common.imm, s1.imm) 437 s1.immType := Mux(s0.valid, s0.bits.immType, s1.immType) 438 } 439 } 440 io.og1ImmInfo.zip(s1_immInfo.flatten).map{ case(out, reg) => 441 out := reg 442 } 443 val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType).toSeq)))) 444 val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire)).toSeq))) 445 446 val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 447 val s1_fpPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 448 val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 449 val s1_v0PregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 450 val s1_vlPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 451 452 val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs)) 453 454 println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}") 455 s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 456 s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 457 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 458 val realIuCfg = iuCfg.map(x => x.filter(_.isInstanceOf[IntRD])).flatten 459 iuRdata.zip(realIuCfg) 460 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[IntRD] } 461 .foreach { case (sink, cfg) => sink := intRfRdata(cfg.port) } 462 } 463 } 464 465 println(s"[DataPath] s1_fpPregRData.flatten.flatten.size: ${s1_fpPregRData.flatten.flatten.size}, fpRfRdata.size: ${fpRfRdata.size}") 466 s1_fpPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 467 s1_fpPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 468 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 469 val realIuCfg = iuCfg.map(x => x.filter(_.isInstanceOf[FpRD])).flatten 470 iuRdata.zip(realIuCfg) 471 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[FpRD] } 472 .foreach { case (sink, cfg) => sink := fpRfRdata(cfg.port) } 473 } 474 } 475 476 println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}") 477 s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 478 s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 479 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 480 val realIuCfg = iuCfg.map(x => x.filter(_.isInstanceOf[VfRD])).flatten 481 iuRdata.zip(realIuCfg) 482 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VfRD] } 483 .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.port) } 484 } 485 } 486 487 println(s"[DataPath] s1_v0PregRData.flatten.flatten.size: ${s1_v0PregRData.flatten.flatten.size}, v0RfRdata.size: ${v0RfRdata.size}") 488 s1_v0PregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 489 s1_v0PregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 490 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 491 val realIuCfg = iuCfg.map(x => x.filter(_.isInstanceOf[V0RD])).flatten 492 iuRdata.zip(realIuCfg) 493 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[V0RD] } 494 .foreach { case (sink, cfg) => sink := v0RfRdata(cfg.port) } 495 } 496 } 497 498 println(s"[DataPath] s1_vlPregRData.flatten.flatten.size: ${s1_vlPregRData.flatten.flatten.size}, vlRfRdata.size: ${vlRfRdata.size}") 499 s1_vlPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 500 s1_vlPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 501 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 502 val realIuCfg = iuCfg.map(x => x.filter(_.isInstanceOf[VlRD])).flatten 503 iuRdata.zip(realIuCfg) 504 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VlRD] } 505 .foreach { case (sink, cfg) => sink := vlRfRdata(cfg.port) } 506 } 507 } 508 509 val og0_cancel_no_load = VecInit(og0FailedVec2.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1).toSeq) 510 val exuParamsNoLoad = fromIQ.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu) 511 val is_0latency = Wire(Vec(og0_cancel_no_load.size, Bool())) 512 is_0latency := exuParamsNoLoad.map(x => is0latency(x._1.bits.common.fuType)) 513 val og0_cancel_delay = RegNext(VecInit(og0_cancel_no_load.zip(is_0latency).map(x => x._1 && x._2))) 514 val isVfScheduler = VecInit(exuParamsNoLoad.map(x => x._2.schdType.isInstanceOf[VfScheduler].B)) 515 val og0_cancel_delay_for_mem = VecInit(og0_cancel_delay.zip(isVfScheduler).map(x => x._1 && !x._2)) 516 for (i <- fromIQ.indices) { 517 for (j <- fromIQ(i).indices) { 518 // IQ(s0) --[Ctrl]--> s1Reg ---------- begin 519 // refs 520 val s1_valid = s1_toExuValid(i)(j) 521 val s1_ready = s1_toExuReady(i)(j) 522 val s1_data = s1_toExuData(i)(j) 523 val s1_addrOH = s1_addrOHs(i)(j) 524 val s0 = fromIQ(i)(j) // s0 525 526 val srcNotBlock = Wire(Bool()) 527 srcNotBlock := s0.bits.common.dataSources.zip(intRdArbWinner(i)(j) zip fpRdArbWinner(i)(j) zip vfRdArbWinner(i)(j) zip v0RdArbWinner(i)(j) zip vlRdArbWinner(i)(j)).map { 528 case (source, ((((win_int, win_fp), win_vf), win_v0), win_vl)) => 529 !source.readReg || win_int && win_fp && win_vf && win_v0 && win_vl 530 }.fold(true.B)(_ && _) 531// if (fromIQ(i)(j).bits.exuParams.schdType.isInstanceOf[IntScheduler] && (fromIQ(i)(j).bits.exuParams.numRegSrc == 2)) { 532// val src0VfBlock = s0.bits.common.dataSources(0).readReg && !vfRdArbWinner(i)(j)(0) 533// val src1VfBlock = s0.bits.common.dataSources(1).readReg && !vfRdArbWinner(i)(j)(1) 534// val src1IntBlock = s0.bits.common.dataSources(0).readReg && s0.bits.common.dataSources(1).readReg && !intRdArbWinner(i)(j)(1) 535// val src0IntBlock = (s0.bits.common.dataSources(0).readReg || s0.bits.common.dataSources(1).readReg) && !intRdArbWinner(i)(j)(0) 536// srcNotBlock := !src0VfBlock && !src1VfBlock && !src1IntBlock && !src0IntBlock 537// } 538 val notBlock = srcNotBlock && intWbNotBlock(i)(j) && fpWbNotBlock(i)(j) && vfWbNotBlock(i)(j) && v0WbNotBlock(i)(j) && vlWbNotBlock(i)(j) 539 val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush))) 540 val s1_cancel = og1FailedVec2(i)(j) 541 val s0_cancel = Wire(Bool()) 542 val og0_cancel_delay_need = if (s0.bits.exuParams.schdType.isInstanceOf[MemScheduler]) og0_cancel_delay_for_mem else og0_cancel_delay 543 if (s0.bits.exuParams.isIQWakeUpSink) { 544 val exuOHNoLoad = s0.bits.common.l1ExuOH.get.map(x => x.asTypeOf(Vec(x.getWidth, Bool())).zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1)) 545 s0_cancel := exuOHNoLoad.zip(s0.bits.common.dataSources).map{ 546 case (exuOH, dataSource) => (VecInit(exuOH).asUInt & og0_cancel_delay_need.asUInt).orR && dataSource.readForward 547 }.reduce(_ || _) && s0.valid 548 } else s0_cancel := false.B 549 val s0_ldCancel = LoadShouldCancel(s0.bits.common.loadDependency, io.ldCancel) 550 when (s0.fire && !s1_flush && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel) { 551 s1_valid := s0.valid 552 s1_data.fromIssueBundle(s0.bits) // no src data here 553// if (fromIQ(i)(j).bits.exuParams.schdType.isInstanceOf[IntScheduler] && (fromIQ(i)(j).bits.exuParams.numRegSrc == 2)) { 554// s1_data.dataSources(1).value := Mux(!s0.bits.common.dataSources(0).readReg && s0.bits.common.dataSources(1).readReg, DataSource.anotherReg, s0.bits.common.dataSources(1).value) 555// } 556 s1_addrOH := s0.bits.addrOH 557 }.otherwise { 558 s1_valid := false.B 559 } 560 s0.ready := (s1_ready || !s1_valid) && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel 561 // IQ(s0) --[Ctrl]--> s1Reg ---------- end 562 } 563 } 564 565 private val fromIQFire = fromIQ.map(_.map(_.fire)) 566 private val toExuFire = toExu.map(_.map(_.fire)) 567 toIQs.zipWithIndex.foreach { 568 case(toIQ, iqIdx) => 569 toIQ.zipWithIndex.foreach { 570 case (toIU, iuIdx) => 571 // IU: issue unit 572 val og0resp = toIU.og0resp 573 og0FailedVec2(iqIdx)(iuIdx) := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx)) 574 og0resp.valid := og0FailedVec2(iqIdx)(iuIdx) 575 og0resp.bits.robIdx := fromIQ(iqIdx)(iuIdx).bits.common.robIdx 576 og0resp.bits.uopIdx.foreach(_ := fromIQ(iqIdx)(iuIdx).bits.common.vpu.get.vuopIdx) 577 og0resp.bits.resp := RespType.block 578 og0resp.bits.fuType := fromIQ(iqIdx)(iuIdx).bits.common.fuType 579 580 val og1resp = toIU.og1resp 581 og1FailedVec2(iqIdx)(iuIdx) := s1_toExuValid(iqIdx)(iuIdx) && !toExuFire(iqIdx)(iuIdx) 582 og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) 583 og1resp.bits.robIdx := s1_toExuData(iqIdx)(iuIdx).robIdx 584 og1resp.bits.uopIdx.foreach(_ := s1_toExuData(iqIdx)(iuIdx).vpu.get.vuopIdx) 585 // respType: fuIdle ->IQ entry clear 586 // fuUncertain ->IQ entry no action 587 // fuBusy ->IQ entry issued set false, then re-issue 588 // hyu, lda and sta are fuUncertain at OG1 stage 589 // and all vector arith exu should check success in og2 stage 590 og1resp.bits.resp := Mux(og1FailedVec2(iqIdx)(iuIdx), 591 RespType.block, 592 if (toIU.issueQueueParams match { case x => x.isLdAddrIQ || x.isStAddrIQ || x.isHyAddrIQ || x.isVecLduIQ || x.isVecStuIQ || x.inVfSchd}) 593 RespType.uncertain 594 else 595 RespType.success, 596 ) 597 og1resp.bits.fuType := s1_toExuData(iqIdx)(iuIdx).fuType 598 } 599 } 600 601 io.og0CancelOH := VecInit(fromFlattenIQ.map(x => x.valid && !x.fire)).asUInt 602 io.og1CancelOH := VecInit(toFlattenExu.map(x => x.valid && !x.fire)).asUInt 603 604 io.cancelToBusyTable.zipWithIndex.foreach { case (cancel, i) => 605 cancel.valid := fromFlattenIQ(i).valid && !fromFlattenIQ(i).fire 606 cancel.bits.rfWen := fromFlattenIQ(i).bits.common.rfWen.getOrElse(false.B) 607 cancel.bits.fpWen := fromFlattenIQ(i).bits.common.fpWen.getOrElse(false.B) 608 cancel.bits.vecWen := fromFlattenIQ(i).bits.common.vecWen.getOrElse(false.B) 609 cancel.bits.v0Wen := fromFlattenIQ(i).bits.common.v0Wen.getOrElse(false.B) 610 cancel.bits.vlWen := fromFlattenIQ(i).bits.common.vlWen.getOrElse(false.B) 611 cancel.bits.pdest := fromFlattenIQ(i).bits.common.pdest 612 } 613 614 if (backendParams.debugEn){ 615 dontTouch(og0_cancel_no_load) 616 dontTouch(is_0latency) 617 dontTouch(og0_cancel_delay) 618 dontTouch(isVfScheduler) 619 dontTouch(og0_cancel_delay_for_mem) 620 } 621 for (i <- toExu.indices) { 622 for (j <- toExu(i).indices) { 623 // s1Reg --[Ctrl]--> exu(s1) ---------- begin 624 // refs 625 val sinkData = toExu(i)(j).bits 626 // assign 627 toExu(i)(j).valid := s1_toExuValid(i)(j) 628 s1_toExuReady(i)(j) := toExu(i)(j).ready 629 sinkData := s1_toExuData(i)(j) 630 // s1Reg --[Ctrl]--> exu(s1) ---------- end 631 632 // s1Reg --[Data]--> exu(s1) ---------- begin 633 // data source1: preg read data 634 for (k <- sinkData.src.indices) { 635 val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k) 636 val readRfMap: Seq[(Bool, UInt)] = ( 637 if (k == 3) {( 638 Seq(None) 639 :+ 640 OptionWrapper(s1_v0PregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(V0RegSrcDataSet).nonEmpty, 641 (SrcType.isV0(s1_srcType(i)(j)(k)) -> s1_v0PregRData(i)(j)(k))) 642 )} 643 else if (k == 4) {( 644 Seq(None) 645 :+ 646 OptionWrapper(s1_vlPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VlRegSrcDataSet).nonEmpty, 647 (SrcType.isVp(s1_srcType(i)(j)(k)) -> s1_vlPregRData(i)(j)(k))) 648 )} 649 else {( 650 Seq(None) 651 :+ 652 OptionWrapper(s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty, 653 (SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k))) 654 :+ 655 OptionWrapper(s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VecRegSrcDataSet).nonEmpty, 656 (SrcType.isVp(s1_srcType(i)(j)(k)) -> s1_vfPregRData(i)(j)(k))) 657 :+ 658 OptionWrapper(s1_fpPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(FpRegSrcDataSet).nonEmpty, 659 (SrcType.isFp(s1_srcType(i)(j)(k)) -> s1_fpPregRData(i)(j)(k))) 660 )} 661 ).filter(_.nonEmpty).map(_.get) 662 663 if (readRfMap.nonEmpty) 664 sinkData.src(k) := Mux1H(readRfMap) 665 } 666 if (sinkData.params.hasJmpFu) { 667 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 668 sinkData.pc.get := pcRdata(index) 669 } 670 if (sinkData.params.needTarget) { 671 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 672 sinkData.predictInfo.get.target := targetPCRdata(index) 673 } 674 } 675 } 676 677 if (env.AlwaysBasicDiff || env.EnableDifftest) { 678 val delayedCnt = 2 679 val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt) 680 difftestArchIntRegState.coreid := io.hartId 681 difftestArchIntRegState.value := intDebugRead.get._2 682 683 val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt) 684 difftestArchFpRegState.coreid := io.hartId 685 difftestArchFpRegState.value := fpDebugReadData.get 686 687 val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt) 688 difftestArchVecRegState.coreid := io.hartId 689 difftestArchVecRegState.value := vecDebugReadData.get 690 } 691 692 val int_regcache_size = 48 693 val int_regcache_tag = RegInit(VecInit(Seq.fill(int_regcache_size)(0.U(intSchdParams.pregIdxWidth.W)))) 694 val int_regcache_enqPtr = RegInit(0.U(log2Up(int_regcache_size).W)) 695 int_regcache_enqPtr := int_regcache_enqPtr + PopCount(intRfWen) 696 for (i <- intRfWen.indices) { 697 when (intRfWen(i)) { 698 int_regcache_tag(int_regcache_enqPtr + PopCount(intRfWen.take(i))) := intRfWaddr(i) 699 } 700 } 701 702 val vf_regcache_size = 48 703 val vf_regcache_tag = RegInit(VecInit(Seq.fill(vf_regcache_size)(0.U(vfSchdParams.pregIdxWidth.W)))) 704 val vf_regcache_enqPtr = RegInit(0.U(log2Up(vf_regcache_size).W)) 705 vf_regcache_enqPtr := vf_regcache_enqPtr + PopCount(vfRfWen.head) 706 for (i <- vfRfWen.indices) { 707 when (vfRfWen.head(i)) { 708 vf_regcache_tag(vf_regcache_enqPtr + PopCount(vfRfWen.head.take(i))) := vfRfWaddr(i) 709 } 710 } 711 712 XSPerfHistogram(s"IntRegFileRead_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 713 XSPerfHistogram(s"FpRegFileRead_hist", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 714 XSPerfHistogram(s"VfRegFileRead_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 715 XSPerfHistogram(s"IntRegFileWrite_hist", PopCount(intRFWriteReq.flatten), true.B, 0, 20, 1) 716 XSPerfHistogram(s"FpRegFileWrite_hist", PopCount(fpRFWriteReq.flatten), true.B, 0, 20, 1) 717 XSPerfHistogram(s"VfRegFileWrite_hist", PopCount(vfRFWriteReq.flatten), true.B, 0, 20, 1) 718 719 val int_regcache_part32 = (1 until 33).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 720 val int_regcache_part24 = (1 until 24).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 721 val int_regcache_part16 = (1 until 17).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 722 val int_regcache_part8 = (1 until 9).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 723 724 val int_regcache_48_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_tag.map(_ === x.bits.addr).reduce(_ || _)) 725 val int_regcache_8_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part8.map(_ === x.bits.addr).reduce(_ || _)) 726 val int_regcache_16_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part16.map(_ === x.bits.addr).reduce(_ || _)) 727 val int_regcache_24_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part24.map(_ === x.bits.addr).reduce(_ || _)) 728 val int_regcache_32_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part32.map(_ === x.bits.addr).reduce(_ || _)) 729 XSPerfAccumulate("IntRegCache48Hit", PopCount(int_regcache_48_hit_vec)) 730 XSPerfAccumulate("IntRegCache8Hit", PopCount(int_regcache_8_hit_vec)) 731 XSPerfAccumulate("IntRegCache16Hit", PopCount(int_regcache_16_hit_vec)) 732 XSPerfAccumulate("IntRegCache24Hit", PopCount(int_regcache_24_hit_vec)) 733 XSPerfAccumulate("IntRegCache32Hit", PopCount(int_regcache_32_hit_vec)) 734 XSPerfHistogram("IntRegCache48Hit_hist", PopCount(int_regcache_48_hit_vec), true.B, 0, 16, 2) 735 736 XSPerfAccumulate(s"IntRFReadBeforeArb", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 737 XSPerfAccumulate(s"IntRFReadAfterArb", PopCount(intRFReadArbiter.io.out.map(_.valid))) 738 XSPerfAccumulate(s"FpRFReadBeforeArb", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 739 XSPerfAccumulate(s"FpRFReadAfterArb", PopCount(fpRFReadArbiter.io.out.map(_.valid))) 740 XSPerfAccumulate(s"VfRFReadBeforeArb", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 741 XSPerfAccumulate(s"VfRFReadAfterArb", PopCount(vfRFReadArbiter.io.out.map(_.valid))) 742 XSPerfAccumulate(s"IntUopBeforeArb", PopCount(fromIntIQ.flatten.map(_.valid))) 743 XSPerfAccumulate(s"IntUopAfterArb", PopCount(fromIntIQ.flatten.map(_.fire))) 744 XSPerfAccumulate(s"MemUopBeforeArb", PopCount(fromMemIQ.flatten.map(_.valid))) 745 XSPerfAccumulate(s"MemUopAfterArb", PopCount(fromMemIQ.flatten.map(_.fire))) 746 XSPerfAccumulate(s"VfUopBeforeArb", PopCount(fromVfIQ.flatten.map(_.valid))) 747 XSPerfAccumulate(s"VfUopAfterArb", PopCount(fromVfIQ.flatten.map(_.fire))) 748 749 XSPerfHistogram(s"IntRFReadBeforeArb_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 750 XSPerfHistogram(s"IntRFReadAfterArb_hist", PopCount(intRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 751 XSPerfHistogram(s"FpRFReadBeforeArb_hist", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 752 XSPerfHistogram(s"FpRFReadAfterArb_hist", PopCount(fpRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 753 XSPerfHistogram(s"VfRFReadBeforeArb_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 754 XSPerfHistogram(s"VfRFReadAfterArb_hist", PopCount(vfRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 755 XSPerfHistogram(s"IntUopBeforeArb_hist", PopCount(fromIntIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 756 XSPerfHistogram(s"IntUopAfterArb_hist", PopCount(fromIntIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 757 XSPerfHistogram(s"MemUopBeforeArb_hist", PopCount(fromMemIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 758 XSPerfHistogram(s"MemUopAfterArb_hist", PopCount(fromMemIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 759 XSPerfHistogram(s"VfUopBeforeArb_hist", PopCount(fromVfIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 760 XSPerfHistogram(s"VfUopAfterArb_hist", PopCount(fromVfIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 761} 762 763class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 764 // params 765 private val intSchdParams = params.schdParams(IntScheduler()) 766 private val fpSchdParams = params.schdParams(FpScheduler()) 767 private val vfSchdParams = params.schdParams(VfScheduler()) 768 private val memSchdParams = params.schdParams(MemScheduler()) 769 // bundles 770 val hartId = Input(UInt(8.W)) 771 772 val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect)) 773 774 val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle()))))) 775 776 val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 777 Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 778 779 val fromFpIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 780 Flipped(MixedVec(fpSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 781 782 val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 783 Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 784 785 val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 786 787 val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle)) 788 789 val toFpIQ = MixedVec(fpSchdParams.issueBlockParams.map(_.genOGRespBundle)) 790 791 val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle)) 792 793 val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) 794 795 val og0CancelOH = Output(ExuOH(backendParams.numExu)) 796 797 val og1CancelOH = Output(ExuOH(backendParams.numExu)) 798 799 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 800 801 val cancelToBusyTable = Vec(backendParams.numExu, ValidIO(new CancelSignal)) 802 803 val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle 804 805 val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(fpSchdParams.genExuInputBundle) 806 807 val toVecExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle) 808 809 val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle 810 811 val og1ImmInfo: Vec[ImmInfo] = Output(Vec(params.allExuParams.size, new ImmInfo)) 812 813 val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle) 814 815 val fromFpWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genFpWriteBackBundle) 816 817 val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle) 818 819 val fromV0Wb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genV0WriteBackBundle) 820 821 val fromVlWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVlWriteBackBundle) 822 823 val fromPcTargetMem = Flipped(new PcToDataPathIO(params)) 824 825 val debugIntRat = if (params.debugEn) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None 826 val debugFpRat = if (params.debugEn) Some(Input(Vec(32, UInt(fpSchdParams.pregIdxWidth.W)))) else None 827 val debugVecRat = if (params.debugEn) Some(Input(Vec(31, UInt(vfSchdParams.pregIdxWidth.W)))) else None 828 val debugV0Rat = if (params.debugEn) Some(Input(UInt(log2Up(V0PhyRegs).W))) else None 829 val debugVlRat = if (params.debugEn) Some(Input(UInt(log2Up(VlPhyRegs).W))) else None 830 val debugVl = if (params.debugEn) Some(Output(UInt(VlData().dataWidth.W))) else None 831} 832