1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule} 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility._ 9import utils.SeqUtils._ 10import utils._ 11import xiangshan._ 12import xiangshan.backend.BackendParams 13import xiangshan.backend.Bundles._ 14import xiangshan.backend.decode.ImmUnion 15import xiangshan.backend.datapath.DataConfig._ 16import xiangshan.backend.datapath.RdConfig._ 17import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler, FpScheduler} 18import xiangshan.backend.issue.EntryBundles._ 19import xiangshan.backend.regfile._ 20import xiangshan.backend.PcToDataPathIO 21import xiangshan.backend.fu.FuType.is0latency 22 23class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { 24 override def shouldBeInlined: Boolean = false 25 26 private implicit val dpParams: BackendParams = params 27 lazy val module = new DataPathImp(this) 28 29 println(s"[DataPath] Preg Params: ") 30 println(s"[DataPath] Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ") 31 println(s"[DataPath] Fp R(${params.getRfReadSize(FpData())}), W(${params.getRfWriteSize(FpData())}) ") 32 println(s"[DataPath] Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ") 33 println(s"[DataPath] V0 R(${params.getRfReadSize(V0Data())}), W(${params.getRfWriteSize(V0Data())}) ") 34 println(s"[DataPath] Vl R(${params.getRfReadSize(VlData())}), W(${params.getRfWriteSize(VlData())}) ") 35} 36 37class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams) 38 extends LazyModuleImp(wrapper) with HasXSParameter { 39 40 val io = IO(new DataPathIO()) 41 42 private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu) 43 private val (fromFpIQ, toFpIQ, toFpExu) = (io.fromFpIQ, io.toFpIQ, io.toFpExu) 44 private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu) 45 private val (fromVfIQ, toVfIQ, toVfExu ) = (io.fromVfIQ, io.toVfIQ, io.toVecExu) 46 47 println(s"[DataPath] IntIQ(${fromIntIQ.size}), FpIQ(${fromFpIQ.size}), VecIQ(${fromVfIQ.size}), MemIQ(${fromMemIQ.size})") 48 println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), FpExu(${fromFpIQ.map(_.size).sum}), VecExu(${fromVfIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})") 49 50 // just refences for convience 51 private val fromIQ: Seq[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = (fromIntIQ ++ fromFpIQ ++ fromVfIQ ++ fromMemIQ).toSeq 52 53 private val toIQs = toIntIQ ++ toFpIQ ++ toVfIQ ++ toMemIQ 54 55 private val toExu: Seq[MixedVec[DecoupledIO[ExuInput]]] = (toIntExu ++ toFpExu ++ toVfExu ++ toMemExu).toSeq 56 57 private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten 58 59 private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten 60 61 private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams)) 62 private val fpWbBusyArbiter = Module(new FpRFWBCollideChecker(backendParams)) 63 private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams)) 64 private val v0WbBusyArbiter = Module(new V0RFWBCollideChecker(backendParams)) 65 private val vlWbBusyArbiter = Module(new VlRFWBCollideChecker(backendParams)) 66 67 private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams)) 68 private val fpRFReadArbiter = Module(new FpRFReadArbiter(backendParams)) 69 private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams)) 70 private val v0RFReadArbiter = Module(new V0RFReadArbiter(backendParams)) 71 private val vlRFReadArbiter = Module(new VlRFReadArbiter(backendParams)) 72 73 private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 74 private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 75 76 // port -> win 77 private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 78 private val fpRdArbWinner: Seq2[MixedVec[Bool]] = fpRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 79 private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 80 private val v0RdArbWinner: Seq2[MixedVec[Bool]] = v0RFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 81 private val vlRdArbWinner: Seq2[MixedVec[Bool]] = vlRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 82 83 private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 84 private val fpWbNotBlock: Seq[MixedVec[Bool]] = fpWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 85 private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 86 private val v0WbNotBlock: Seq[MixedVec[Bool]] = v0WbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 87 private val vlWbNotBlock: Seq[MixedVec[Bool]] = vlWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 88 89 private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR)) 90 private val fpRdNotBlock: Seq2[Bool] = fpRdArbWinner.map(_.map(_.asUInt.andR)) 91 private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR)) 92 private val v0RdNotBlock: Seq2[Bool] = v0RdArbWinner.map(_.map(_.asUInt.andR)) 93 private val vlRdNotBlock: Seq2[Bool] = vlRdArbWinner.map(_.map(_.asUInt.andR)) 94 95 private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 96 private val fpRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 97 private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 98 private val v0RFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 99 private val vlRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 100 101 private val allDataSources: Seq[Seq[Vec[DataSource]]] = fromIQ.map(x => x.map(xx => xx.bits.common.dataSources).toSeq) 102 private val allNumRegSrcs: Seq[Seq[Int]] = fromIQ.map(x => x.map(xx => xx.bits.exuParams.numRegSrc).toSeq) 103 104 intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 105 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 106 val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData()) 107 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 108 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 109 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 110 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 111 } else { 112 arbInSeq(srcIdx).valid := false.B 113 arbInSeq(srcIdx).bits.addr := 0.U 114 } 115 } 116 } 117 } 118 fpRFReadArbiter.io.in.zip(fpRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 119 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 120 val srcIndices: Seq[Int] = FpRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 121 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 122 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 123 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 124 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 125 } else { 126 arbInSeq(srcIdx).valid := false.B 127 arbInSeq(srcIdx).bits.addr := 0.U 128 } 129 } 130 } 131 } 132 133 vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 134 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 135 val srcIndices: Seq[Int] = VecRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 136 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 137 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 138 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 139 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 140 } else { 141 arbInSeq(srcIdx).valid := false.B 142 arbInSeq(srcIdx).bits.addr := 0.U 143 } 144 } 145 } 146 } 147 148 v0RFReadArbiter.io.in.zip(v0RFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 149 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 150 val srcIndices: Seq[Int] = V0RegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 151 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 152 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 153 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 154 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 155 } else { 156 arbInSeq(srcIdx).valid := false.B 157 arbInSeq(srcIdx).bits.addr := 0.U 158 } 159 } 160 } 161 } 162 163 vlRFReadArbiter.io.in.zip(vlRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 164 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 165 val srcIndices: Seq[Int] = VlRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 166 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 167 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 168 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 169 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 170 } else { 171 arbInSeq(srcIdx).valid := false.B 172 arbInSeq(srcIdx).bits.addr := 0.U 173 } 174 } 175 } 176 } 177 178 private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B)).toSeq).toSeq 179 private val fpRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.fpWen.getOrElse(false.B)).toSeq).toSeq 180 private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.vecWen.getOrElse(false.B)).toSeq).toSeq 181 private val v0RFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.v0Wen.getOrElse(false.B)).toSeq).toSeq 182 private val vlRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.vlWen.getOrElse(false.B)).toSeq).toSeq 183 184 intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 185 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 186 arbIn.valid := inRFWriteReq 187 } 188 } 189 190 fpWbBusyArbiter.io.in.zip(fpRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 191 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 192 arbIn.valid := inRFWriteReq 193 } 194 } 195 196 vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 197 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 198 arbIn.valid := inRFWriteReq 199 } 200 } 201 202 v0WbBusyArbiter.io.in.zip(v0RFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 203 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 204 arbIn.valid := inRFWriteReq 205 } 206 } 207 208 vlWbBusyArbiter.io.in.zip(vlRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 209 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 210 arbIn.valid := inRFWriteReq 211 } 212 } 213 214 private val intSchdParams = params.schdParams(IntScheduler()) 215 private val fpSchdParams = params.schdParams(FpScheduler()) 216 private val vfSchdParams = params.schdParams(VfScheduler()) 217 private val memSchdParams = params.schdParams(MemScheduler()) 218 219 private val schdParams = params.allSchdParams 220 221 private val pcReadValid = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathValid)) 222 private val pcReadFtqPtr = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqPtr)) 223 private val pcReadFtqOffset = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqOffset)) 224 private val targetPCRdata = io.fromPcTargetMem.toDataPathTargetPC 225 private val pcRdata = io.fromPcTargetMem.toDataPathPC 226 private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W))) 227 private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W))) 228 private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool())) 229 private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W))) 230 private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W))) 231 232 private val fpRfRaddr = Wire(Vec(params.numPregRd(FpData()), UInt(fpSchdParams.pregIdxWidth.W))) 233 private val fpRfRdata = Wire(Vec(params.numPregRd(FpData()), UInt(fpSchdParams.rfDataWidth.W))) 234 private val fpRfWen = Wire(Vec(io.fromFpWb.length, Bool())) 235 private val fpRfWaddr = Wire(Vec(io.fromFpWb.length, UInt(fpSchdParams.pregIdxWidth.W))) 236 private val fpRfWdata = Wire(Vec(io.fromFpWb.length, UInt(fpSchdParams.rfDataWidth.W))) 237 238 private val vfRfSplitNum = VLEN / XLEN 239 private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W))) 240 private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W))) 241 private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool()))) 242 private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W))) 243 private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W))) 244 245 private val v0RfSplitNum = VLEN / XLEN 246 private val v0RfRaddr = Wire(Vec(params.numPregRd(V0Data()), UInt(log2Up(V0PhyRegs).W))) 247 private val v0RfRdata = Wire(Vec(params.numPregRd(V0Data()), UInt(V0Data().dataWidth.W))) 248 private val v0RfWen = Wire(Vec(v0RfSplitNum, Vec(io.fromV0Wb.length, Bool()))) 249 private val v0RfWaddr = Wire(Vec(io.fromV0Wb.length, UInt(log2Up(V0PhyRegs).W))) 250 private val v0RfWdata = Wire(Vec(io.fromV0Wb.length, UInt(V0Data().dataWidth.W))) 251 252 private val vlRfRaddr = Wire(Vec(params.numPregRd(VlData()), UInt(log2Up(VlPhyRegs).W))) 253 private val vlRfRdata = Wire(Vec(params.numPregRd(VlData()), UInt(VlData().dataWidth.W))) 254 private val vlRfWen = Wire(Vec(io.fromVlWb.length, Bool())) 255 private val vlRfWaddr = Wire(Vec(io.fromVlWb.length, UInt(log2Up(VlPhyRegs).W))) 256 private val vlRfWdata = Wire(Vec(io.fromVlWb.length, UInt(VlData().dataWidth.W))) 257 258 val pcReadFtqPtrFormIQ = fromIntIQ.flatten.filter(x => x.bits.exuParams.needPc) 259 assert(pcReadFtqPtrFormIQ.size == pcReadFtqPtr.size, s"pcReadFtqPtrFormIQ.size ${pcReadFtqPtrFormIQ.size} not equal pcReadFtqPtr.size ${pcReadFtqPtr.size}") 260 pcReadValid.zip(pcReadFtqPtrFormIQ.map(_.valid)).map(x => x._1 := x._2) 261 pcReadFtqPtr.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqIdx.get)).map(x => x._1 := x._2) 262 pcReadFtqOffset.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqOffset.get)).map(x => x._1 := x._2) 263 io.fromPcTargetMem.fromDataPathValid := pcReadValid 264 io.fromPcTargetMem.fromDataPathFtqPtr := pcReadFtqPtr 265 io.fromPcTargetMem.fromDataPathFtqOffset := pcReadFtqOffset 266 267 private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] = 268 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W))))) 269 private val fpDebugRead: Option[(Vec[UInt], Vec[UInt])] = 270 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(32, UInt(fpSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W))))) 271 private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] = 272 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(31, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(31, UInt(VLEN.W))))) 273 private val v0DebugRead: Option[(Vec[UInt], Vec[UInt])] = 274 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(1, UInt(log2Up(V0PhyRegs).W))), Wire(Vec(1, UInt(V0Data().dataWidth.W))))) 275 private val vlDebugRead: Option[(Vec[UInt], Vec[UInt])] = 276 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(1, UInt(log2Up(VlPhyRegs).W))), Wire(Vec(1, UInt(VlData().dataWidth.W))))) 277 278 private val fpDebugReadData: Option[Vec[UInt]] = 279 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, Wire(Vec(32, UInt(XLEN.W)))) 280 private val vecDebugReadData: Option[Vec[UInt]] = 281 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0)) 282 private val vlDebugReadData: Option[UInt] = 283 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, Wire(UInt(VlData().dataWidth.W))) 284 285 286 fpDebugReadData.foreach(_ := fpDebugRead 287 .get._2 288 .slice(0, 32) 289 .map(_(63, 0)) 290 ) // fp only used [63, 0] 291 vecDebugReadData.foreach(_ := 292 v0DebugRead 293 .get._2 294 .slice(0, 1) 295 .map(x => Seq(x(63, 0), x(127, 64))).flatten ++ 296 vfDebugRead 297 .get._2 298 .slice(0, 31) 299 .map(x => Seq(x(63, 0), x(127, 64))).flatten 300 ) 301 vlDebugReadData.foreach(_ := vlDebugRead 302 .get._2(0) 303 ) 304 305 io.debugVl.foreach(_ := vlDebugReadData.get) 306 307 IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata, 308 bankNum = 1, 309 debugReadAddr = intDebugRead.map(_._1), 310 debugReadData = intDebugRead.map(_._2) 311 ) 312 FpRegFile("FpRegFile", fpSchdParams.numPregs, fpRfRaddr, fpRfRdata, fpRfWen, fpRfWaddr, fpRfWdata, 313 bankNum = 1, 314 debugReadAddr = fpDebugRead.map(_._1), 315 debugReadData = fpDebugRead.map(_._2) 316 ) 317 VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata, 318 debugReadAddr = vfDebugRead.map(_._1), 319 debugReadData = vfDebugRead.map(_._2) 320 ) 321 VfRegFile("V0RegFile", V0PhyRegs, v0RfSplitNum, v0RfRaddr, v0RfRdata, v0RfWen, v0RfWaddr, v0RfWdata, 322 debugReadAddr = v0DebugRead.map(_._1), 323 debugReadData = v0DebugRead.map(_._2) 324 ) 325 FpRegFile("VlRegFile", VlPhyRegs, vlRfRaddr, vlRfRdata, vlRfWen, vlRfWaddr, vlRfWdata, 326 bankNum = 1, 327 debugReadAddr = vlDebugRead.map(_._1), 328 debugReadData = vlDebugRead.map(_._2) 329 ) 330 331 intRfWaddr := io.fromIntWb.map(x => RegEnable(x.addr, x.wen)).toSeq 332 intRfWdata := io.fromIntWb.map(x => RegEnable(x.data, x.wen)).toSeq 333 intRfWen := RegNext(VecInit(io.fromIntWb.map(_.wen).toSeq)) 334 335 for (portIdx <- intRfRaddr.indices) { 336 if (intRFReadArbiter.io.out.isDefinedAt(portIdx)) 337 intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr 338 else 339 intRfRaddr(portIdx) := 0.U 340 } 341 342 fpRfWaddr := io.fromFpWb.map(x => RegEnable(x.addr, x.wen)).toSeq 343 fpRfWdata := io.fromFpWb.map(x => RegEnable(x.data, x.wen)).toSeq 344 fpRfWen := RegNext(VecInit(io.fromFpWb.map(_.wen).toSeq)) 345 346 for (portIdx <- fpRfRaddr.indices) { 347 if (fpRFReadArbiter.io.out.isDefinedAt(portIdx)) 348 fpRfRaddr(portIdx) := fpRFReadArbiter.io.out(portIdx).bits.addr 349 else 350 fpRfRaddr(portIdx) := 0.U 351 } 352 353 vfRfWaddr := io.fromVfWb.map(x => RegEnable(x.addr, x.wen)).toSeq 354 vfRfWdata := io.fromVfWb.map(x => RegEnable(x.data, x.wen)).toSeq 355 vfRfWen.foreach(_.zip(io.fromVfWb.map(x => RegNext(x.wen))).foreach { case (wenSink, wenSource) => wenSink := wenSource } ) 356 357 for (portIdx <- vfRfRaddr.indices) { 358 if (vfRFReadArbiter.io.out.isDefinedAt(portIdx)) 359 vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr 360 else 361 vfRfRaddr(portIdx) := 0.U 362 } 363 364 v0RfWaddr := io.fromV0Wb.map(_.addr).toSeq 365 v0RfWdata := io.fromV0Wb.map(_.data).toSeq 366 v0RfWen.foreach(_.zip(io.fromV0Wb.map(_.wen)).foreach { case (wenSink, wenSource) => wenSink := wenSource } ) 367 368 for (portIdx <- v0RfRaddr.indices) { 369 if (v0RFReadArbiter.io.out.isDefinedAt(portIdx)) 370 v0RfRaddr(portIdx) := v0RFReadArbiter.io.out(portIdx).bits.addr 371 else 372 v0RfRaddr(portIdx) := 0.U 373 } 374 375 vlRfWaddr := io.fromVlWb.map(_.addr).toSeq 376 vlRfWdata := io.fromVlWb.map(_.data).toSeq 377 vlRfWen := io.fromVlWb.map(_.wen).toSeq 378 379 for (portIdx <- vlRfRaddr.indices) { 380 if (vlRFReadArbiter.io.out.isDefinedAt(portIdx)) 381 vlRfRaddr(portIdx) := vlRFReadArbiter.io.out(portIdx).bits.addr 382 else 383 vlRfRaddr(portIdx) := 0.U 384 } 385 386 387 intDebugRead.foreach { case (addr, _) => 388 addr := io.debugIntRat.get 389 } 390 391 fpDebugRead.foreach { case (addr, _) => 392 addr := io.debugFpRat.get 393 } 394 395 vfDebugRead.foreach { case (addr, _) => 396 addr := io.debugVecRat.get 397 } 398 v0DebugRead.foreach { case (addr, _) => 399 addr := io.debugV0Rat.get 400 } 401 vlDebugRead.foreach { case (addr, _) => 402 addr := io.debugVlRat.get 403 } 404 405 println(s"[DataPath] " + 406 s"has intDebugRead: ${intDebugRead.nonEmpty}, " + 407 s"has fpDebugRead: ${fpDebugRead.nonEmpty}, " + 408 s"has vecDebugRead: ${vfDebugRead.nonEmpty}, " + 409 s"has v0DebugRead: ${v0DebugRead.nonEmpty}, " + 410 s"has vlDebugRead: ${vlDebugRead.nonEmpty}") 411 412 val s1_addrOHs = Reg(MixedVec( 413 fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType).toSeq)).toSeq 414 )) 415 val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec( 416 toExu.map(x => MixedVec(x.map(_.valid.cloneType).toSeq)).toSeq 417 )) 418 val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType).toSeq)).toSeq)) 419 val s1_immInfo = Reg(MixedVec(toExu.map(x => MixedVec(x.map(x => new ImmInfo).toSeq)).toSeq)) 420 s1_immInfo.zip(fromIQ).map { case (s1Vec, s0Vec) => 421 s1Vec.zip(s0Vec).map { case (s1, s0) => 422 s1.imm := Mux(s0.valid, s0.bits.common.imm, s1.imm) 423 s1.immType := Mux(s0.valid, s0.bits.immType, s1.immType) 424 } 425 } 426 io.og1ImmInfo.zip(s1_immInfo.flatten).map{ case(out, reg) => 427 out := reg 428 } 429 val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType).toSeq)))) 430 val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire)).toSeq))) 431 432 val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 433 val s1_fpPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 434 val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 435 val s1_v0PregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 436 val s1_vlPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 437 438 val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs)) 439 440 println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}") 441 s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 442 s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 443 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 444 val realIuCfg = iuCfg.map(x => x.filter(_.isInstanceOf[IntRD])).flatten 445 iuRdata.zip(realIuCfg) 446 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[IntRD] } 447 .foreach { case (sink, cfg) => sink := intRfRdata(cfg.port) } 448 } 449 } 450 451 println(s"[DataPath] s1_fpPregRData.flatten.flatten.size: ${s1_fpPregRData.flatten.flatten.size}, fpRfRdata.size: ${fpRfRdata.size}") 452 s1_fpPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 453 s1_fpPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 454 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 455 val realIuCfg = iuCfg.map(x => x.filter(_.isInstanceOf[FpRD])).flatten 456 iuRdata.zip(realIuCfg) 457 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[FpRD] } 458 .foreach { case (sink, cfg) => sink := fpRfRdata(cfg.port) } 459 } 460 } 461 462 println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}") 463 s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 464 s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 465 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 466 val realIuCfg = iuCfg.map(x => x.filter(_.isInstanceOf[VfRD])).flatten 467 iuRdata.zip(realIuCfg) 468 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VfRD] } 469 .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.port) } 470 } 471 } 472 473 println(s"[DataPath] s1_v0PregRData.flatten.flatten.size: ${s1_v0PregRData.flatten.flatten.size}, v0RfRdata.size: ${v0RfRdata.size}") 474 s1_v0PregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 475 s1_v0PregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 476 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 477 val realIuCfg = iuCfg.map(x => x.filter(_.isInstanceOf[V0RD])).flatten 478 iuRdata.zip(realIuCfg) 479 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[V0RD] } 480 .foreach { case (sink, cfg) => sink := v0RfRdata(cfg.port) } 481 } 482 } 483 484 println(s"[DataPath] s1_vlPregRData.flatten.flatten.size: ${s1_vlPregRData.flatten.flatten.size}, vlRfRdata.size: ${vlRfRdata.size}") 485 s1_vlPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 486 s1_vlPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 487 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 488 val realIuCfg = iuCfg.map(x => x.filter(_.isInstanceOf[VlRD])).flatten 489 iuRdata.zip(realIuCfg) 490 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VlRD] } 491 .foreach { case (sink, cfg) => sink := vlRfRdata(cfg.port) } 492 } 493 } 494 495 val og0_cancel_no_load = VecInit(og0FailedVec2.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1).toSeq) 496 val exuParamsNoLoad = fromIQ.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu) 497 val is_0latency = Wire(Vec(og0_cancel_no_load.size, Bool())) 498 is_0latency := exuParamsNoLoad.map(x => is0latency(x._1.bits.common.fuType)) 499 val og0_cancel_delay = RegNext(VecInit(og0_cancel_no_load.zip(is_0latency).map(x => x._1 && x._2))) 500 val isVfScheduler = VecInit(exuParamsNoLoad.map(x => x._2.schdType.isInstanceOf[VfScheduler].B)) 501 val og0_cancel_delay_for_mem = VecInit(og0_cancel_delay.zip(isVfScheduler).map(x => x._1 && !x._2)) 502 for (i <- fromIQ.indices) { 503 for (j <- fromIQ(i).indices) { 504 // IQ(s0) --[Ctrl]--> s1Reg ---------- begin 505 // refs 506 val s1_valid = s1_toExuValid(i)(j) 507 val s1_ready = s1_toExuReady(i)(j) 508 val s1_data = s1_toExuData(i)(j) 509 val s1_addrOH = s1_addrOHs(i)(j) 510 val s0 = fromIQ(i)(j) // s0 511 512 val srcNotBlock = Wire(Bool()) 513 srcNotBlock := s0.bits.common.dataSources.zip(intRdArbWinner(i)(j) zip fpRdArbWinner(i)(j) zip vfRdArbWinner(i)(j) zip v0RdArbWinner(i)(j) zip vlRdArbWinner(i)(j)).map { 514 case (source, ((((win_int, win_fp), win_vf), win_v0), win_vl)) => 515 !source.readReg || win_int && win_fp && win_vf && win_v0 && win_vl 516 }.fold(true.B)(_ && _) 517 val notBlock = srcNotBlock && intWbNotBlock(i)(j) && fpWbNotBlock(i)(j) && vfWbNotBlock(i)(j) && v0WbNotBlock(i)(j) && vlWbNotBlock(i)(j) 518 val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush))) 519 val s1_cancel = og1FailedVec2(i)(j) 520 val s0_cancel = Wire(Bool()) 521 val og0_cancel_delay_need = if (s0.bits.exuParams.schdType.isInstanceOf[MemScheduler]) og0_cancel_delay_for_mem else og0_cancel_delay 522 if (s0.bits.exuParams.isIQWakeUpSink) { 523 val exuOHNoLoad = s0.bits.common.l1ExuOH.get.map(x => x.asTypeOf(Vec(x.getWidth, Bool())).zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1)) 524 s0_cancel := exuOHNoLoad.zip(s0.bits.common.dataSources).map{ 525 case (exuOH, dataSource) => (VecInit(exuOH).asUInt & og0_cancel_delay_need.asUInt).orR && dataSource.readForward 526 }.reduce(_ || _) && s0.valid 527 } else s0_cancel := false.B 528 val s0_ldCancel = LoadShouldCancel(s0.bits.common.loadDependency, io.ldCancel) 529 when (s0.fire && !s1_flush && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel) { 530 s1_valid := s0.valid 531 s1_data.fromIssueBundle(s0.bits) // no src data here 532 s1_addrOH := s0.bits.addrOH 533 }.otherwise { 534 s1_valid := false.B 535 } 536 s0.ready := (s1_ready || !s1_valid) && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel 537 // IQ(s0) --[Ctrl]--> s1Reg ---------- end 538 } 539 } 540 541 private val fromIQFire = fromIQ.map(_.map(_.fire)) 542 private val toExuFire = toExu.map(_.map(_.fire)) 543 toIQs.zipWithIndex.foreach { 544 case(toIQ, iqIdx) => 545 toIQ.zipWithIndex.foreach { 546 case (toIU, iuIdx) => 547 // IU: issue unit 548 val og0resp = toIU.og0resp 549 og0FailedVec2(iqIdx)(iuIdx) := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx)) 550 og0resp.valid := og0FailedVec2(iqIdx)(iuIdx) 551 og0resp.bits.robIdx := fromIQ(iqIdx)(iuIdx).bits.common.robIdx 552 og0resp.bits.uopIdx.foreach(_ := fromIQ(iqIdx)(iuIdx).bits.common.vpu.get.vuopIdx) 553 og0resp.bits.resp := RespType.block 554 og0resp.bits.fuType := fromIQ(iqIdx)(iuIdx).bits.common.fuType 555 556 val og1resp = toIU.og1resp 557 og1FailedVec2(iqIdx)(iuIdx) := s1_toExuValid(iqIdx)(iuIdx) && !toExuFire(iqIdx)(iuIdx) 558 og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) 559 og1resp.bits.robIdx := s1_toExuData(iqIdx)(iuIdx).robIdx 560 og1resp.bits.uopIdx.foreach(_ := s1_toExuData(iqIdx)(iuIdx).vpu.get.vuopIdx) 561 // respType: fuIdle ->IQ entry clear 562 // fuUncertain ->IQ entry no action 563 // fuBusy ->IQ entry issued set false, then re-issue 564 // hyu, lda and sta are fuUncertain at OG1 stage 565 // and all vector arith exu should check success in og2 stage 566 og1resp.bits.resp := Mux(og1FailedVec2(iqIdx)(iuIdx), 567 RespType.block, 568 if (toIU.issueQueueParams match { case x => x.isLdAddrIQ || x.isStAddrIQ || x.isHyAddrIQ || x.isVecLduIQ || x.isVecStuIQ || x.inVfSchd}) 569 RespType.uncertain 570 else 571 RespType.success, 572 ) 573 og1resp.bits.fuType := s1_toExuData(iqIdx)(iuIdx).fuType 574 } 575 } 576 577 io.og0CancelOH := VecInit(fromFlattenIQ.map(x => x.valid && !x.fire)).asUInt 578 io.og1CancelOH := VecInit(toFlattenExu.map(x => x.valid && !x.fire)).asUInt 579 580 io.cancelToBusyTable.zipWithIndex.foreach { case (cancel, i) => 581 cancel.valid := fromFlattenIQ(i).valid && !fromFlattenIQ(i).fire 582 cancel.bits.rfWen := fromFlattenIQ(i).bits.common.rfWen.getOrElse(false.B) 583 cancel.bits.fpWen := fromFlattenIQ(i).bits.common.fpWen.getOrElse(false.B) 584 cancel.bits.vecWen := fromFlattenIQ(i).bits.common.vecWen.getOrElse(false.B) 585 cancel.bits.v0Wen := fromFlattenIQ(i).bits.common.v0Wen.getOrElse(false.B) 586 cancel.bits.vlWen := fromFlattenIQ(i).bits.common.vlWen.getOrElse(false.B) 587 cancel.bits.pdest := fromFlattenIQ(i).bits.common.pdest 588 } 589 590 if (backendParams.debugEn){ 591 dontTouch(og0_cancel_no_load) 592 dontTouch(is_0latency) 593 dontTouch(og0_cancel_delay) 594 dontTouch(isVfScheduler) 595 dontTouch(og0_cancel_delay_for_mem) 596 } 597 for (i <- toExu.indices) { 598 for (j <- toExu(i).indices) { 599 // s1Reg --[Ctrl]--> exu(s1) ---------- begin 600 // refs 601 val sinkData = toExu(i)(j).bits 602 // assign 603 toExu(i)(j).valid := s1_toExuValid(i)(j) 604 s1_toExuReady(i)(j) := toExu(i)(j).ready 605 sinkData := s1_toExuData(i)(j) 606 // s1Reg --[Ctrl]--> exu(s1) ---------- end 607 608 // s1Reg --[Data]--> exu(s1) ---------- begin 609 // data source1: preg read data 610 for (k <- sinkData.src.indices) { 611 val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k) 612 val readRfMap: Seq[(Bool, UInt)] = ( 613 if (k == 3) {( 614 Seq(None) 615 :+ 616 OptionWrapper(s1_v0PregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(V0RegSrcDataSet).nonEmpty, 617 (SrcType.isV0(s1_srcType(i)(j)(k)) -> s1_v0PregRData(i)(j)(k))) 618 )} 619 else if (k == 4) {( 620 Seq(None) 621 :+ 622 OptionWrapper(s1_vlPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VlRegSrcDataSet).nonEmpty, 623 (SrcType.isVp(s1_srcType(i)(j)(k)) -> s1_vlPregRData(i)(j)(k))) 624 )} 625 else {( 626 Seq(None) 627 :+ 628 OptionWrapper(s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty, 629 (SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k))) 630 :+ 631 OptionWrapper(s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VecRegSrcDataSet).nonEmpty, 632 (SrcType.isVp(s1_srcType(i)(j)(k)) -> s1_vfPregRData(i)(j)(k))) 633 :+ 634 OptionWrapper(s1_fpPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(FpRegSrcDataSet).nonEmpty, 635 (SrcType.isFp(s1_srcType(i)(j)(k)) -> s1_fpPregRData(i)(j)(k))) 636 )} 637 ).filter(_.nonEmpty).map(_.get) 638 639 if (readRfMap.nonEmpty) 640 sinkData.src(k) := Mux1H(readRfMap) 641 } 642 if (sinkData.params.hasJmpFu) { 643 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 644 sinkData.pc.get := pcRdata(index) 645 } 646 if (sinkData.params.needTarget) { 647 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 648 sinkData.predictInfo.get.target := targetPCRdata(index) 649 } 650 } 651 } 652 653 if (env.AlwaysBasicDiff || env.EnableDifftest) { 654 val delayedCnt = 2 655 val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt) 656 difftestArchIntRegState.coreid := io.hartId 657 difftestArchIntRegState.value := intDebugRead.get._2 658 659 val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt) 660 difftestArchFpRegState.coreid := io.hartId 661 difftestArchFpRegState.value := fpDebugReadData.get 662 663 val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt) 664 difftestArchVecRegState.coreid := io.hartId 665 difftestArchVecRegState.value := vecDebugReadData.get 666 } 667 668 val int_regcache_size = 48 669 val int_regcache_tag = RegInit(VecInit(Seq.fill(int_regcache_size)(0.U(intSchdParams.pregIdxWidth.W)))) 670 val int_regcache_enqPtr = RegInit(0.U(log2Up(int_regcache_size).W)) 671 int_regcache_enqPtr := int_regcache_enqPtr + PopCount(intRfWen) 672 for (i <- intRfWen.indices) { 673 when (intRfWen(i)) { 674 int_regcache_tag(int_regcache_enqPtr + PopCount(intRfWen.take(i))) := intRfWaddr(i) 675 } 676 } 677 678 val vf_regcache_size = 48 679 val vf_regcache_tag = RegInit(VecInit(Seq.fill(vf_regcache_size)(0.U(vfSchdParams.pregIdxWidth.W)))) 680 val vf_regcache_enqPtr = RegInit(0.U(log2Up(vf_regcache_size).W)) 681 vf_regcache_enqPtr := vf_regcache_enqPtr + PopCount(vfRfWen.head) 682 for (i <- vfRfWen.indices) { 683 when (vfRfWen.head(i)) { 684 vf_regcache_tag(vf_regcache_enqPtr + PopCount(vfRfWen.head.take(i))) := vfRfWaddr(i) 685 } 686 } 687 688 XSPerfHistogram(s"IntRegFileRead_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 689 XSPerfHistogram(s"FpRegFileRead_hist", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 690 XSPerfHistogram(s"VfRegFileRead_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 691 XSPerfHistogram(s"IntRegFileWrite_hist", PopCount(intRFWriteReq.flatten), true.B, 0, 20, 1) 692 XSPerfHistogram(s"FpRegFileWrite_hist", PopCount(fpRFWriteReq.flatten), true.B, 0, 20, 1) 693 XSPerfHistogram(s"VfRegFileWrite_hist", PopCount(vfRFWriteReq.flatten), true.B, 0, 20, 1) 694 695 val int_regcache_part32 = (1 until 33).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 696 val int_regcache_part24 = (1 until 24).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 697 val int_regcache_part16 = (1 until 17).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 698 val int_regcache_part8 = (1 until 9).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 699 700 val int_regcache_48_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_tag.map(_ === x.bits.addr).reduce(_ || _)) 701 val int_regcache_8_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part8.map(_ === x.bits.addr).reduce(_ || _)) 702 val int_regcache_16_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part16.map(_ === x.bits.addr).reduce(_ || _)) 703 val int_regcache_24_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part24.map(_ === x.bits.addr).reduce(_ || _)) 704 val int_regcache_32_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part32.map(_ === x.bits.addr).reduce(_ || _)) 705 XSPerfAccumulate("IntRegCache48Hit", PopCount(int_regcache_48_hit_vec)) 706 XSPerfAccumulate("IntRegCache8Hit", PopCount(int_regcache_8_hit_vec)) 707 XSPerfAccumulate("IntRegCache16Hit", PopCount(int_regcache_16_hit_vec)) 708 XSPerfAccumulate("IntRegCache24Hit", PopCount(int_regcache_24_hit_vec)) 709 XSPerfAccumulate("IntRegCache32Hit", PopCount(int_regcache_32_hit_vec)) 710 XSPerfHistogram("IntRegCache48Hit_hist", PopCount(int_regcache_48_hit_vec), true.B, 0, 16, 2) 711 712 XSPerfAccumulate(s"IntRFReadBeforeArb", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 713 XSPerfAccumulate(s"IntRFReadAfterArb", PopCount(intRFReadArbiter.io.out.map(_.valid))) 714 XSPerfAccumulate(s"FpRFReadBeforeArb", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 715 XSPerfAccumulate(s"FpRFReadAfterArb", PopCount(fpRFReadArbiter.io.out.map(_.valid))) 716 XSPerfAccumulate(s"VfRFReadBeforeArb", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 717 XSPerfAccumulate(s"VfRFReadAfterArb", PopCount(vfRFReadArbiter.io.out.map(_.valid))) 718 XSPerfAccumulate(s"IntUopBeforeArb", PopCount(fromIntIQ.flatten.map(_.valid))) 719 XSPerfAccumulate(s"IntUopAfterArb", PopCount(fromIntIQ.flatten.map(_.fire))) 720 XSPerfAccumulate(s"MemUopBeforeArb", PopCount(fromMemIQ.flatten.map(_.valid))) 721 XSPerfAccumulate(s"MemUopAfterArb", PopCount(fromMemIQ.flatten.map(_.fire))) 722 XSPerfAccumulate(s"VfUopBeforeArb", PopCount(fromVfIQ.flatten.map(_.valid))) 723 XSPerfAccumulate(s"VfUopAfterArb", PopCount(fromVfIQ.flatten.map(_.fire))) 724 725 XSPerfHistogram(s"IntRFReadBeforeArb_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 726 XSPerfHistogram(s"IntRFReadAfterArb_hist", PopCount(intRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 727 XSPerfHistogram(s"FpRFReadBeforeArb_hist", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 728 XSPerfHistogram(s"FpRFReadAfterArb_hist", PopCount(fpRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 729 XSPerfHistogram(s"VfRFReadBeforeArb_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 730 XSPerfHistogram(s"VfRFReadAfterArb_hist", PopCount(vfRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 731 XSPerfHistogram(s"IntUopBeforeArb_hist", PopCount(fromIntIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 732 XSPerfHistogram(s"IntUopAfterArb_hist", PopCount(fromIntIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 733 XSPerfHistogram(s"MemUopBeforeArb_hist", PopCount(fromMemIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 734 XSPerfHistogram(s"MemUopAfterArb_hist", PopCount(fromMemIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 735 XSPerfHistogram(s"VfUopBeforeArb_hist", PopCount(fromVfIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 736 XSPerfHistogram(s"VfUopAfterArb_hist", PopCount(fromVfIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 737} 738 739class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 740 // params 741 private val intSchdParams = params.schdParams(IntScheduler()) 742 private val fpSchdParams = params.schdParams(FpScheduler()) 743 private val vfSchdParams = params.schdParams(VfScheduler()) 744 private val memSchdParams = params.schdParams(MemScheduler()) 745 // bundles 746 val hartId = Input(UInt(8.W)) 747 748 val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect)) 749 750 val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle()))))) 751 752 val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 753 Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 754 755 val fromFpIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 756 Flipped(MixedVec(fpSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 757 758 val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 759 Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 760 761 val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 762 763 val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle)) 764 765 val toFpIQ = MixedVec(fpSchdParams.issueBlockParams.map(_.genOGRespBundle)) 766 767 val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle)) 768 769 val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) 770 771 val og0CancelOH = Output(ExuOH(backendParams.numExu)) 772 773 val og1CancelOH = Output(ExuOH(backendParams.numExu)) 774 775 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 776 777 val cancelToBusyTable = Vec(backendParams.numExu, ValidIO(new CancelSignal)) 778 779 val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle 780 781 val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(fpSchdParams.genExuInputBundle) 782 783 val toVecExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle) 784 785 val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle 786 787 val og1ImmInfo: Vec[ImmInfo] = Output(Vec(params.allExuParams.size, new ImmInfo)) 788 789 val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle) 790 791 val fromFpWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genFpWriteBackBundle) 792 793 val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle) 794 795 val fromV0Wb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genV0WriteBackBundle) 796 797 val fromVlWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVlWriteBackBundle) 798 799 val fromPcTargetMem = Flipped(new PcToDataPathIO(params)) 800 801 val debugIntRat = if (params.debugEn) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None 802 val debugFpRat = if (params.debugEn) Some(Input(Vec(32, UInt(fpSchdParams.pregIdxWidth.W)))) else None 803 val debugVecRat = if (params.debugEn) Some(Input(Vec(31, UInt(vfSchdParams.pregIdxWidth.W)))) else None 804 val debugV0Rat = if (params.debugEn) Some(Input(Vec(1, UInt(log2Up(V0PhyRegs).W)))) else None 805 val debugVlRat = if (params.debugEn) Some(Input(Vec(1, UInt(log2Up(VlPhyRegs).W)))) else None 806 val debugVl = if (params.debugEn) Some(Output(UInt(VlData().dataWidth.W))) else None 807} 808