1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule} 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility._ 9import utils.SeqUtils._ 10import utils.{XSPerfAccumulate, XSPerfHistogram} 11import xiangshan._ 12import xiangshan.backend.BackendParams 13import xiangshan.backend.Bundles._ 14import xiangshan.backend.decode.ImmUnion 15import xiangshan.backend.datapath.DataConfig._ 16import xiangshan.backend.datapath.RdConfig._ 17import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler, FpScheduler} 18import xiangshan.backend.issue.EntryBundles._ 19import xiangshan.backend.regfile._ 20import xiangshan.backend.PcToDataPathIO 21import xiangshan.backend.fu.FuType.is0latency 22 23class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { 24 override def shouldBeInlined: Boolean = false 25 26 private implicit val dpParams: BackendParams = params 27 lazy val module = new DataPathImp(this) 28 29 println(s"[DataPath] Preg Params: ") 30 println(s"[DataPath] Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ") 31 println(s"[DataPath] Fp R(${params.getRfReadSize(FpData())}), W(${params.getRfWriteSize(FpData())}) ") 32 println(s"[DataPath] Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ") 33} 34 35class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams) 36 extends LazyModuleImp(wrapper) with HasXSParameter { 37 38 val io = IO(new DataPathIO()) 39 40 private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu) 41 private val (fromFpIQ, toFpIQ, toFpExu) = (io.fromFpIQ, io.toFpIQ, io.toFpExu) 42 private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu) 43 private val (fromVfIQ , toVfIQ , toVfExu ) = (io.fromVfIQ , io.toVfIQ , io.toVecExu) 44 45 println(s"[DataPath] IntIQ(${fromIntIQ.size}), MemIQ(${fromFpIQ.size}), MemIQ(${fromMemIQ.size})") 46 println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), FpExu(${fromFpIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})") 47 48 // just refences for convience 49 private val fromIQ: Seq[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = (fromIntIQ ++ fromFpIQ ++ fromVfIQ ++ fromMemIQ).toSeq 50 51 private val toIQs = toIntIQ ++ toFpIQ ++ toVfIQ ++ toMemIQ 52 53 private val toExu: Seq[MixedVec[DecoupledIO[ExuInput]]] = (toIntExu ++ toFpExu ++ toVfExu ++ toMemExu).toSeq 54 55 private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten 56 57 private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten 58 59 private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams)) 60 private val fpWbBusyArbiter = Module(new FpRFWBCollideChecker(backendParams)) 61 private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams)) 62 private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams)) 63 private val fpRFReadArbiter = Module(new FpRFReadArbiter(backendParams)) 64 private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams)) 65 66 private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 67 private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 68 69 // port -> win 70 private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 71 private val fpRdArbWinner: Seq2[MixedVec[Bool]] = fpRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 72 private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 73 private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 74 private val fpWbNotBlock: Seq[MixedVec[Bool]] = fpWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 75 private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 76 77 private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR)) 78 private val fpRdNotBlock: Seq2[Bool] = fpRdArbWinner.map(_.map(_.asUInt.andR)) 79 private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR)) 80 81 private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 82 private val fpRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 83 private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 84 private val allDataSources: Seq[Seq[Vec[DataSource]]] = fromIQ.map(x => x.map(xx => xx.bits.common.dataSources).toSeq) 85 private val allNumRegSrcs: Seq[Seq[Int]] = fromIQ.map(x => x.map(xx => xx.bits.exuParams.numRegSrc).toSeq) 86 87 intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 88 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 89 val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData()) 90 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 91 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 92 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 93 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 94// if (allNumRegSrcs(iqIdx)(exuIdx) == 2) { 95// val src0Req = inRFReadReqSeq(0).valid && allDataSources(iqIdx)(exuIdx)(0).readReg 96// val src1Req = inRFReadReqSeq(1).valid && allDataSources(iqIdx)(exuIdx)(1).readReg 97// if (srcIdx == 0) { 98// arbInSeq(srcIdx).valid := src0Req || src1Req 99// arbInSeq(srcIdx).bits.addr := Mux(src1Req && !src0Req, inRFReadReqSeq(1).bits.addr,inRFReadReqSeq(0).bits.addr) 100// } else { 101// arbInSeq(srcIdx).valid := src0Req && src1Req 102// arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 103// } 104// } else { 105// arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 106// arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 107// } 108 } else { 109 arbInSeq(srcIdx).valid := false.B 110 arbInSeq(srcIdx).bits.addr := 0.U 111 } 112 } 113 } 114 } 115 fpRFReadArbiter.io.in.zip(fpRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 116 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 117 val srcIndices: Seq[Int] = FpRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 118 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 119 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 120 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 121 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 122 } else { 123 arbInSeq(srcIdx).valid := false.B 124 arbInSeq(srcIdx).bits.addr := 0.U 125 } 126 } 127 } 128 } 129 130 vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 131 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 132 val srcIndices: Seq[Int] = VfRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 133 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 134 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 135 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 136 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 137 } else { 138 arbInSeq(srcIdx).valid := false.B 139 arbInSeq(srcIdx).bits.addr := 0.U 140 } 141 } 142 } 143 } 144 145 private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B)).toSeq).toSeq 146 private val fpRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.fpWen.getOrElse(false.B)).toSeq).toSeq 147 private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.vecWen.getOrElse(false.B)).toSeq).toSeq 148 149 intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 150 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 151 arbIn.valid := inRFWriteReq 152 } 153 } 154 155 fpWbBusyArbiter.io.in.zip(fpRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 156 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 157 arbIn.valid := inRFWriteReq 158 } 159 } 160 161 vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 162 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 163 arbIn.valid := inRFWriteReq 164 } 165 } 166 167 private val intSchdParams = params.schdParams(IntScheduler()) 168 private val fpSchdParams = params.schdParams(FpScheduler()) 169 private val vfSchdParams = params.schdParams(VfScheduler()) 170 private val memSchdParams = params.schdParams(MemScheduler()) 171 172 private val schdParams = params.allSchdParams 173 174 private val pcReadValid = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathValid)) 175 private val pcReadFtqPtr = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqPtr)) 176 private val pcReadFtqOffset = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqOffset)) 177 private val targetPCRdata = io.fromPcTargetMem.toDataPathTargetPC 178 private val pcRdata = io.fromPcTargetMem.toDataPathPC 179 private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W))) 180 private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W))) 181 private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool())) 182 private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W))) 183 private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W))) 184 185 private val fpRfRaddr = Wire(Vec(params.numPregRd(FpData()), UInt(fpSchdParams.pregIdxWidth.W))) 186 private val fpRfRdata = Wire(Vec(params.numPregRd(FpData()), UInt(fpSchdParams.rfDataWidth.W))) 187 private val fpRfWen = Wire(Vec(io.fromFpWb.length, Bool())) 188 private val fpRfWaddr = Wire(Vec(io.fromFpWb.length, UInt(fpSchdParams.pregIdxWidth.W))) 189 private val fpRfWdata = Wire(Vec(io.fromFpWb.length, UInt(fpSchdParams.rfDataWidth.W))) 190 191 private val vfRfSplitNum = VLEN / XLEN 192 private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W))) 193 private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W))) 194 private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool()))) 195 private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W))) 196 private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W))) 197 198 val pcReadFtqPtrFormIQ = fromIntIQ.flatten.filter(x => x.bits.exuParams.needPc) 199 assert(pcReadFtqPtrFormIQ.size == pcReadFtqPtr.size, s"pcReadFtqPtrFormIQ.size ${pcReadFtqPtrFormIQ.size} not equal pcReadFtqPtr.size ${pcReadFtqPtr.size}") 200 pcReadValid.zip(pcReadFtqPtrFormIQ.map(_.valid)).map(x => x._1 := x._2) 201 pcReadFtqPtr.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqIdx.get)).map(x => x._1 := x._2) 202 pcReadFtqOffset.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqOffset.get)).map(x => x._1 := x._2) 203 io.fromPcTargetMem.fromDataPathValid := pcReadValid 204 io.fromPcTargetMem.fromDataPathFtqPtr := pcReadFtqPtr 205 io.fromPcTargetMem.fromDataPathFtqOffset := pcReadFtqOffset 206 207 private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] = 208 if (env.AlwaysBasicDiff || env.EnableDifftest) { 209 Some(Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))) 210 } else { None } 211 private val fpDebugRead: Option[(Vec[UInt], Vec[UInt])] = 212 if (env.AlwaysBasicDiff || env.EnableDifftest) { 213 Some(Wire(Vec(32, UInt(fpSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))) 214 } else { None } 215 private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] = 216 if (env.AlwaysBasicDiff || env.EnableDifftest) { 217 Some(Wire(Vec(32 + 1, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(32 + 1, UInt(VLEN.W)))) 218 } else { None } 219 220 private val fpDebugReadData: Option[Vec[UInt]] = 221 if (env.AlwaysBasicDiff || env.EnableDifftest) { 222 Some(Wire(Vec(32, UInt(XLEN.W)))) 223 } else { None } 224 private val vecDebugReadData: Option[Vec[UInt]] = 225 if (env.AlwaysBasicDiff || env.EnableDifftest) { 226 Some(Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0)) 227 } else { None } 228 private val vconfigDebugReadData: Option[UInt] = 229 if (env.AlwaysBasicDiff || env.EnableDifftest) { 230 Some(Wire(UInt(64.W))) 231 } else { None } 232 233 234 fpDebugReadData.foreach(_ := fpDebugRead 235 .get._2 236 .slice(0, 32) 237 .map(_(63, 0)) 238 ) // fp only used [63, 0] 239 vecDebugReadData.foreach(_ := vfDebugRead 240 .get._2 241 .slice(0, 32) 242 .map(x => Seq(x(63, 0), x(127, 64))).flatten 243 ) 244 vconfigDebugReadData.foreach(_ := vfDebugRead 245 .get._2(32)(63, 0) 246 ) 247 248 io.debugVconfig.foreach(_ := vconfigDebugReadData.get) 249 250 IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata, 251 bankNum = 1, 252 debugReadAddr = intDebugRead.map(_._1), 253 debugReadData = intDebugRead.map(_._2)) 254 FpRegFile("FpRegFile", fpSchdParams.numPregs, fpRfRaddr, fpRfRdata, fpRfWen, fpRfWaddr, fpRfWdata, 255 bankNum = 1, 256 debugReadAddr = fpDebugRead.map(_._1), 257 debugReadData = fpDebugRead.map(_._2)) 258 VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata, 259 debugReadAddr = vfDebugRead.map(_._1), 260 debugReadData = vfDebugRead.map(_._2)) 261 262 intRfWaddr := io.fromIntWb.map(x => RegEnable(x.addr, x.wen)).toSeq 263 intRfWdata := io.fromIntWb.map(x => RegEnable(x.data, x.wen)).toSeq 264 intRfWen := RegNext(VecInit(io.fromIntWb.map(_.wen).toSeq)) 265 266 for (portIdx <- intRfRaddr.indices) { 267 if (intRFReadArbiter.io.out.isDefinedAt(portIdx)) 268 intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr 269 else 270 intRfRaddr(portIdx) := 0.U 271 } 272 273 fpRfWaddr := io.fromFpWb.map(x => RegEnable(x.addr, x.wen)).toSeq 274 fpRfWdata := io.fromFpWb.map(x => RegEnable(x.data, x.wen)).toSeq 275 fpRfWen := RegNext(VecInit(io.fromFpWb.map(_.wen).toSeq)) 276 277 for (portIdx <- fpRfRaddr.indices) { 278 if (fpRFReadArbiter.io.out.isDefinedAt(portIdx)) 279 fpRfRaddr(portIdx) := fpRFReadArbiter.io.out(portIdx).bits.addr 280 else 281 fpRfRaddr(portIdx) := 0.U 282 } 283 284 vfRfWaddr := io.fromVfWb.map(x => RegEnable(x.addr, x.wen)).toSeq 285 vfRfWdata := io.fromVfWb.map(x => RegEnable(x.data, x.wen)).toSeq 286 vfRfWen.foreach(_.zip(io.fromVfWb.map(x => RegNext(x.wen))).foreach { case (wenSink, wenSource) => wenSink := wenSource } )// Todo: support fp multi-write 287 288 for (portIdx <- vfRfRaddr.indices) { 289 if (vfRFReadArbiter.io.out.isDefinedAt(portIdx)) 290 vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr 291 else 292 vfRfRaddr(portIdx) := 0.U 293 } 294 295 296 intDebugRead.foreach { case (addr, _) => 297 addr := io.debugIntRat.get 298 } 299 300 fpDebugRead.foreach { case (addr, _) => 301 addr := io.debugFpRat.get 302 } 303 304 vfDebugRead.foreach { case (addr, _) => 305 addr := io.debugVecRat.get :+ io.debugVconfigRat.get 306 } 307 println(s"[DataPath] " + 308 s"has intDebugRead: ${intDebugRead.nonEmpty}, " + 309 s"has vfDebugRead: ${vfDebugRead.nonEmpty}") 310 311 val s1_addrOHs = Reg(MixedVec( 312 fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType).toSeq)).toSeq 313 )) 314 val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec( 315 toExu.map(x => MixedVec(x.map(_.valid.cloneType).toSeq)).toSeq 316 )) 317 val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType).toSeq)).toSeq)) 318 val s1_immInfo = Reg(MixedVec(toExu.map(x => MixedVec(x.map(x => new ImmInfo).toSeq)).toSeq)) 319 s1_immInfo.zip(fromIQ).map { case (s1Vec, s0Vec) => 320 s1Vec.zip(s0Vec).map { case (s1, s0) => 321 s1.imm := Mux(s0.valid, s0.bits.common.imm, s1.imm) 322 s1.immType := Mux(s0.valid, s0.bits.immType, s1.immType) 323 } 324 } 325 io.og1ImmInfo.zip(s1_immInfo.flatten).map{ case(out, reg) => 326 out := reg 327 } 328 val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType).toSeq)))) 329 val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire)).toSeq))) 330 331 val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 332 val s1_fpPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 333 val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 334 335 val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs)) 336 337 println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}") 338 s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 339 s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 340 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 341 val realIuCfg = iuCfg.map(x => x.filter(_.isInstanceOf[IntRD])).flatten 342 iuRdata.zip(realIuCfg) 343 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[IntRD] } 344 .foreach { case (sink, cfg) => sink := intRfRdata(cfg.port) } 345 } 346 } 347 348 println(s"[DataPath] s1_fpPregRData.flatten.flatten.size: ${s1_fpPregRData.flatten.flatten.size}, fpRfRdata.size: ${fpRfRdata.size}") 349 s1_fpPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 350 s1_fpPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 351 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 352 val realIuCfg = iuCfg.map(x => x.filter(_.isInstanceOf[FpRD])).flatten 353 iuRdata.zip(realIuCfg) 354 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[FpRD] } 355 .foreach { case (sink, cfg) => sink := fpRfRdata(cfg.port) } 356 } 357 } 358 359 println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}") 360 s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 361 s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 362 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 363 val realIuCfg = iuCfg.map(x => x.filter(_.isInstanceOf[VfRD])).flatten 364 iuRdata.zip(realIuCfg) 365 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VfRD] } 366 .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.port) } 367 } 368 } 369 370 val og0_cancel_no_load = VecInit(og0FailedVec2.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1).toSeq) 371 val exuParamsNoLoad = fromIQ.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu) 372 val is_0latency = Wire(Vec(og0_cancel_no_load.size, Bool())) 373 is_0latency := exuParamsNoLoad.map(x => is0latency(x._1.bits.common.fuType)) 374 val og0_cancel_delay = RegNext(VecInit(og0_cancel_no_load.zip(is_0latency).map(x => x._1 && x._2))) 375 val isVfScheduler = VecInit(exuParamsNoLoad.map(x => x._2.schdType.isInstanceOf[VfScheduler].B)) 376 val og0_cancel_delay_for_mem = VecInit(og0_cancel_delay.zip(isVfScheduler).map(x => x._1 && !x._2)) 377 for (i <- fromIQ.indices) { 378 for (j <- fromIQ(i).indices) { 379 // IQ(s0) --[Ctrl]--> s1Reg ---------- begin 380 // refs 381 val s1_valid = s1_toExuValid(i)(j) 382 val s1_ready = s1_toExuReady(i)(j) 383 val s1_data = s1_toExuData(i)(j) 384 val s1_addrOH = s1_addrOHs(i)(j) 385 val s0 = fromIQ(i)(j) // s0 386 387 val srcNotBlock = Wire(Bool()) 388 srcNotBlock := s0.bits.common.dataSources.zip(intRdArbWinner(i)(j) zip fpRdArbWinner(i)(j) zip vfRdArbWinner(i)(j)).map { 389 case (source, ((win_int, win_fp),win_vf)) => 390 !source.readReg || win_int && win_fp && win_vf 391 }.fold(true.B)(_ && _) 392// if (fromIQ(i)(j).bits.exuParams.schdType.isInstanceOf[IntScheduler] && (fromIQ(i)(j).bits.exuParams.numRegSrc == 2)) { 393// val src0VfBlock = s0.bits.common.dataSources(0).readReg && !vfRdArbWinner(i)(j)(0) 394// val src1VfBlock = s0.bits.common.dataSources(1).readReg && !vfRdArbWinner(i)(j)(1) 395// val src1IntBlock = s0.bits.common.dataSources(0).readReg && s0.bits.common.dataSources(1).readReg && !intRdArbWinner(i)(j)(1) 396// val src0IntBlock = (s0.bits.common.dataSources(0).readReg || s0.bits.common.dataSources(1).readReg) && !intRdArbWinner(i)(j)(0) 397// srcNotBlock := !src0VfBlock && !src1VfBlock && !src1IntBlock && !src0IntBlock 398// } 399 val notBlock = srcNotBlock && intWbNotBlock(i)(j) && fpWbNotBlock(i)(j) && vfWbNotBlock(i)(j) 400 val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush))) 401 val s1_cancel = og1FailedVec2(i)(j) 402 val s0_cancel = Wire(Bool()) 403 val og0_cancel_delay_need = if (s0.bits.exuParams.schdType.isInstanceOf[MemScheduler]) og0_cancel_delay_for_mem else og0_cancel_delay 404 if (s0.bits.exuParams.isIQWakeUpSink) { 405 val exuOHNoLoad = s0.bits.common.l1ExuOH.get.map(x => x.asTypeOf(Vec(x.getWidth, Bool())).zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1)) 406 s0_cancel := exuOHNoLoad.zip(s0.bits.common.dataSources).map{ 407 case (exuOH, dataSource) => (VecInit(exuOH).asUInt & og0_cancel_delay_need.asUInt).orR && dataSource.readForward 408 }.reduce(_ || _) && s0.valid 409 } else s0_cancel := false.B 410 val s0_ldCancel = LoadShouldCancel(s0.bits.common.loadDependency, io.ldCancel) 411 when (s0.fire && !s1_flush && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel) { 412 s1_valid := s0.valid 413 s1_data.fromIssueBundle(s0.bits) // no src data here 414// if (fromIQ(i)(j).bits.exuParams.schdType.isInstanceOf[IntScheduler] && (fromIQ(i)(j).bits.exuParams.numRegSrc == 2)) { 415// s1_data.dataSources(1).value := Mux(!s0.bits.common.dataSources(0).readReg && s0.bits.common.dataSources(1).readReg, DataSource.anotherReg, s0.bits.common.dataSources(1).value) 416// } 417 s1_addrOH := s0.bits.addrOH 418 }.otherwise { 419 s1_valid := false.B 420 } 421 s0.ready := (s1_ready || !s1_valid) && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel 422 // IQ(s0) --[Ctrl]--> s1Reg ---------- end 423 } 424 } 425 426 private val fromIQFire = fromIQ.map(_.map(_.fire)) 427 private val toExuFire = toExu.map(_.map(_.fire)) 428 toIQs.zipWithIndex.foreach { 429 case(toIQ, iqIdx) => 430 toIQ.zipWithIndex.foreach { 431 case (toIU, iuIdx) => 432 // IU: issue unit 433 val og0resp = toIU.og0resp 434 og0FailedVec2(iqIdx)(iuIdx) := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx)) 435 og0resp.valid := og0FailedVec2(iqIdx)(iuIdx) 436 og0resp.bits.robIdx := fromIQ(iqIdx)(iuIdx).bits.common.robIdx 437 og0resp.bits.uopIdx.foreach(_ := fromIQ(iqIdx)(iuIdx).bits.common.vpu.get.vuopIdx) 438 og0resp.bits.resp := RespType.block 439 og0resp.bits.fuType := fromIQ(iqIdx)(iuIdx).bits.common.fuType 440 441 val og1resp = toIU.og1resp 442 og1FailedVec2(iqIdx)(iuIdx) := s1_toExuValid(iqIdx)(iuIdx) && !toExuFire(iqIdx)(iuIdx) 443 og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) 444 og1resp.bits.robIdx := s1_toExuData(iqIdx)(iuIdx).robIdx 445 og1resp.bits.uopIdx.foreach(_ := s1_toExuData(iqIdx)(iuIdx).vpu.get.vuopIdx) 446 // respType: fuIdle ->IQ entry clear 447 // fuUncertain ->IQ entry no action 448 // fuBusy ->IQ entry issued set false, then re-issue 449 // hyu, lda and sta are fuUncertain at OG1 stage 450 // and all vector arith exu should check success in og2 stage 451 og1resp.bits.resp := Mux(og1FailedVec2(iqIdx)(iuIdx), 452 RespType.block, 453 if (toIU.issueQueueParams match { case x => x.isLdAddrIQ || x.isStAddrIQ || x.isHyAddrIQ || x.isVecLduIQ || x.isVecStuIQ || x.inVfSchd}) 454 RespType.uncertain 455 else 456 RespType.success, 457 ) 458 og1resp.bits.fuType := s1_toExuData(iqIdx)(iuIdx).fuType 459 } 460 } 461 462 io.og0CancelOH := VecInit(fromFlattenIQ.map(x => x.valid && !x.fire)).asUInt 463 io.og1CancelOH := VecInit(toFlattenExu.map(x => x.valid && !x.fire)).asUInt 464 465 io.cancelToBusyTable.zipWithIndex.foreach { case (cancel, i) => 466 cancel.valid := fromFlattenIQ(i).valid && !fromFlattenIQ(i).fire 467 cancel.bits.rfWen := fromFlattenIQ(i).bits.common.rfWen.getOrElse(false.B) 468 cancel.bits.fpWen := fromFlattenIQ(i).bits.common.fpWen.getOrElse(false.B) 469 cancel.bits.vecWen := fromFlattenIQ(i).bits.common.vecWen.getOrElse(false.B) 470 cancel.bits.pdest := fromFlattenIQ(i).bits.common.pdest 471 } 472 473 if (backendParams.debugEn){ 474 dontTouch(og0_cancel_no_load) 475 dontTouch(is_0latency) 476 dontTouch(og0_cancel_delay) 477 dontTouch(isVfScheduler) 478 dontTouch(og0_cancel_delay_for_mem) 479 } 480 for (i <- toExu.indices) { 481 for (j <- toExu(i).indices) { 482 // s1Reg --[Ctrl]--> exu(s1) ---------- begin 483 // refs 484 val sinkData = toExu(i)(j).bits 485 // assign 486 toExu(i)(j).valid := s1_toExuValid(i)(j) 487 s1_toExuReady(i)(j) := toExu(i)(j).ready 488 sinkData := s1_toExuData(i)(j) 489 // s1Reg --[Ctrl]--> exu(s1) ---------- end 490 491 // s1Reg --[Data]--> exu(s1) ---------- begin 492 // data source1: preg read data 493 for (k <- sinkData.src.indices) { 494 val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k) 495 496 val readRfMap: Seq[(Bool, UInt)] = (Seq(None) :+ 497 (if (s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty) 498 Some(SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k)) 499 else None) :+ 500 (if (s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VfRegSrcDataSet).nonEmpty) 501 Some(SrcType.isVp(s1_srcType(i)(j)(k))-> s1_vfPregRData(i)(j)(k)) 502 else None) :+ 503 (if (s1_fpPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(FpRegSrcDataSet).nonEmpty) 504 Some(SrcType.isFp(s1_srcType(i)(j)(k)) -> s1_fpPregRData(i)(j)(k)) 505 else None) 506 ).filter(_.nonEmpty).map(_.get) 507 if (readRfMap.nonEmpty) 508 sinkData.src(k) := Mux1H(readRfMap) 509 } 510 if (sinkData.params.hasJmpFu) { 511 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 512 sinkData.pc.get := pcRdata(index) 513 } 514 if (sinkData.params.needTarget) { 515 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 516 sinkData.predictInfo.get.target := targetPCRdata(index) 517 } 518 } 519 } 520 521 if (env.AlwaysBasicDiff || env.EnableDifftest) { 522 val delayedCnt = 2 523 val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt) 524 difftestArchIntRegState.coreid := io.hartId 525 difftestArchIntRegState.value := intDebugRead.get._2 526 527 val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt) 528 difftestArchFpRegState.coreid := io.hartId 529 difftestArchFpRegState.value := fpDebugReadData.get 530 531 val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt) 532 difftestArchVecRegState.coreid := io.hartId 533 difftestArchVecRegState.value := vecDebugReadData.get 534 } 535 536 val int_regcache_size = 48 537 val int_regcache_tag = RegInit(VecInit(Seq.fill(int_regcache_size)(0.U(intSchdParams.pregIdxWidth.W)))) 538 val int_regcache_enqPtr = RegInit(0.U(log2Up(int_regcache_size).W)) 539 int_regcache_enqPtr := int_regcache_enqPtr + PopCount(intRfWen) 540 for (i <- intRfWen.indices) { 541 when (intRfWen(i)) { 542 int_regcache_tag(int_regcache_enqPtr + PopCount(intRfWen.take(i))) := intRfWaddr(i) 543 } 544 } 545 546 val vf_regcache_size = 48 547 val vf_regcache_tag = RegInit(VecInit(Seq.fill(vf_regcache_size)(0.U(vfSchdParams.pregIdxWidth.W)))) 548 val vf_regcache_enqPtr = RegInit(0.U(log2Up(vf_regcache_size).W)) 549 vf_regcache_enqPtr := vf_regcache_enqPtr + PopCount(vfRfWen.head) 550 for (i <- vfRfWen.indices) { 551 when (vfRfWen.head(i)) { 552 vf_regcache_tag(vf_regcache_enqPtr + PopCount(vfRfWen.head.take(i))) := vfRfWaddr(i) 553 } 554 } 555 556 XSPerfHistogram(s"IntRegFileRead_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 557 XSPerfHistogram(s"FpRegFileRead_hist", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 558 XSPerfHistogram(s"VfRegFileRead_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 559 XSPerfHistogram(s"IntRegFileWrite_hist", PopCount(intRFWriteReq.flatten), true.B, 0, 20, 1) 560 XSPerfHistogram(s"FpRegFileWrite_hist", PopCount(fpRFWriteReq.flatten), true.B, 0, 20, 1) 561 XSPerfHistogram(s"VfRegFileWrite_hist", PopCount(vfRFWriteReq.flatten), true.B, 0, 20, 1) 562 563 val int_regcache_part32 = (1 until 33).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 564 val int_regcache_part24 = (1 until 24).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 565 val int_regcache_part16 = (1 until 17).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 566 val int_regcache_part8 = (1 until 9).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 567 568 val int_regcache_48_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_tag.map(_ === x.bits.addr).reduce(_ || _)) 569 val int_regcache_8_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part8.map(_ === x.bits.addr).reduce(_ || _)) 570 val int_regcache_16_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part16.map(_ === x.bits.addr).reduce(_ || _)) 571 val int_regcache_24_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part24.map(_ === x.bits.addr).reduce(_ || _)) 572 val int_regcache_32_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part32.map(_ === x.bits.addr).reduce(_ || _)) 573 XSPerfAccumulate("IntRegCache48Hit", PopCount(int_regcache_48_hit_vec)) 574 XSPerfAccumulate("IntRegCache8Hit", PopCount(int_regcache_8_hit_vec)) 575 XSPerfAccumulate("IntRegCache16Hit", PopCount(int_regcache_16_hit_vec)) 576 XSPerfAccumulate("IntRegCache24Hit", PopCount(int_regcache_24_hit_vec)) 577 XSPerfAccumulate("IntRegCache32Hit", PopCount(int_regcache_32_hit_vec)) 578 XSPerfHistogram("IntRegCache48Hit_hist", PopCount(int_regcache_48_hit_vec), true.B, 0, 16, 2) 579 580 XSPerfAccumulate(s"IntRFReadBeforeArb", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 581 XSPerfAccumulate(s"IntRFReadAfterArb", PopCount(intRFReadArbiter.io.out.map(_.valid))) 582 XSPerfAccumulate(s"FpRFReadBeforeArb", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 583 XSPerfAccumulate(s"FpRFReadAfterArb", PopCount(fpRFReadArbiter.io.out.map(_.valid))) 584 XSPerfAccumulate(s"VfRFReadBeforeArb", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 585 XSPerfAccumulate(s"VfRFReadAfterArb", PopCount(vfRFReadArbiter.io.out.map(_.valid))) 586 XSPerfAccumulate(s"IntUopBeforeArb", PopCount(fromIntIQ.flatten.map(_.valid))) 587 XSPerfAccumulate(s"IntUopAfterArb", PopCount(fromIntIQ.flatten.map(_.fire))) 588 XSPerfAccumulate(s"MemUopBeforeArb", PopCount(fromMemIQ.flatten.map(_.valid))) 589 XSPerfAccumulate(s"MemUopAfterArb", PopCount(fromMemIQ.flatten.map(_.fire))) 590 XSPerfAccumulate(s"VfUopBeforeArb", PopCount(fromVfIQ.flatten.map(_.valid))) 591 XSPerfAccumulate(s"VfUopAfterArb", PopCount(fromVfIQ.flatten.map(_.fire))) 592 593 XSPerfHistogram(s"IntRFReadBeforeArb_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 594 XSPerfHistogram(s"IntRFReadAfterArb_hist", PopCount(intRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 595 XSPerfHistogram(s"FpRFReadBeforeArb_hist", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 596 XSPerfHistogram(s"FpRFReadAfterArb_hist", PopCount(fpRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 597 XSPerfHistogram(s"VfRFReadBeforeArb_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 598 XSPerfHistogram(s"VfRFReadAfterArb_hist", PopCount(vfRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 599 XSPerfHistogram(s"IntUopBeforeArb_hist", PopCount(fromIntIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 600 XSPerfHistogram(s"IntUopAfterArb_hist", PopCount(fromIntIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 601 XSPerfHistogram(s"MemUopBeforeArb_hist", PopCount(fromMemIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 602 XSPerfHistogram(s"MemUopAfterArb_hist", PopCount(fromMemIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 603 XSPerfHistogram(s"VfUopBeforeArb_hist", PopCount(fromVfIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 604 XSPerfHistogram(s"VfUopAfterArb_hist", PopCount(fromVfIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 605} 606 607class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 608 // params 609 private val intSchdParams = params.schdParams(IntScheduler()) 610 private val fpSchdParams = params.schdParams(FpScheduler()) 611 private val vfSchdParams = params.schdParams(VfScheduler()) 612 private val memSchdParams = params.schdParams(MemScheduler()) 613 // bundles 614 val hartId = Input(UInt(8.W)) 615 616 val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect)) 617 618 val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle()))))) 619 620 val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 621 Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 622 623 val fromFpIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 624 Flipped(MixedVec(fpSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 625 626 val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 627 Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 628 629 val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 630 631 val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle)) 632 633 val toFpIQ = MixedVec(fpSchdParams.issueBlockParams.map(_.genOGRespBundle)) 634 635 val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle)) 636 637 val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) 638 639 val og0CancelOH = Output(ExuOH(backendParams.numExu)) 640 641 val og1CancelOH = Output(ExuOH(backendParams.numExu)) 642 643 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 644 645 val cancelToBusyTable = Vec(backendParams.numExu, ValidIO(new CancelSignal)) 646 647 val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle 648 649 val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(fpSchdParams.genExuInputBundle) 650 651 val toVecExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle) 652 653 val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle 654 655 val og1ImmInfo: Vec[ImmInfo] = Output(Vec(params.allExuParams.size, new ImmInfo)) 656 657 val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle) 658 659 val fromFpWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genFpWriteBackBundle) 660 661 val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle) 662 663 val fromPcTargetMem = Flipped(new PcToDataPathIO(params)) 664 665 val debugIntRat = if (params.debugEn) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None 666 val debugFpRat = if (params.debugEn) Some(Input(Vec(32, UInt(fpSchdParams.pregIdxWidth.W)))) else None 667 val debugVecRat = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None 668 val debugVconfigRat = if (params.debugEn) Some(Input(UInt(vfSchdParams.pregIdxWidth.W))) else None 669 val debugVconfig = if (params.debugEn) Some(Output(UInt(XLEN.W))) else None 670} 671