xref: /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala (revision 8f1fa9b1f65ffa29fe1bf75176395cb8ecde6aa5) 
1package xiangshan.backend.datapath
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule}
7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
8import utility._
9import utils.SeqUtils._
10import xiangshan._
11import xiangshan.backend.BackendParams
12import xiangshan.backend.Bundles._
13import xiangshan.backend.decode.ImmUnion
14import xiangshan.backend.datapath.DataConfig._
15import xiangshan.backend.datapath.RdConfig._
16import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler}
17import xiangshan.backend.implicitCast._
18import xiangshan.backend.regfile._
19
20class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule {
21  override def shouldBeInlined: Boolean = false
22
23  private implicit val dpParams: BackendParams = params
24  lazy val module = new DataPathImp(this)
25
26  println(s"[DataPath] Preg Params: ")
27  println(s"[DataPath]   Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ")
28  println(s"[DataPath]   Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ")
29}
30
31class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams)
32  extends LazyModuleImp(wrapper) with HasXSParameter {
33
34  private val VCONFIG_PORT = params.vconfigPort
35
36  val io = IO(new DataPathIO())
37
38  private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu)
39  private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu)
40  private val (fromVfIQ , toVfIQ , toVfExu ) = (io.fromVfIQ , io.toVfIQ , io.toFpExu)
41
42  println(s"[DataPath] IntIQ(${fromIntIQ.size}), MemIQ(${fromMemIQ.size})")
43  println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})")
44
45  // just refences for convience
46  private val fromIQ: Seq[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = fromIntIQ ++ fromVfIQ ++ fromMemIQ
47
48  private val toIQs = toIntIQ ++ toVfIQ ++ toMemIQ
49
50  private val toExu: Seq[MixedVec[DecoupledIO[ExuInput]]] = toIntExu ++ toVfExu ++ toMemExu
51
52  private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten
53
54  private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten
55
56  private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams))
57  private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams))
58  private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams))
59  private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams))
60
61  private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq))
62  private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq))
63
64  // port -> win
65  private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq
66  private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq
67  private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq
68  private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq
69
70  private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR))
71  private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR))
72
73  private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getIntRfReadValidBundle(xx.valid)).toSeq).toSeq
74  private val intDataSources: Seq[Seq[Vec[DataSource]]] = fromIQ.map(x => x.map(xx => xx.bits.common.dataSources))
75
76  intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) =>
77    arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) =>
78      val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData())
79      for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) {
80        if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) {
81          arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && intDataSources(iqIdx)(exuIdx)(srcIdx).readReg
82          arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr
83        } else {
84          arbInSeq(srcIdx).valid := false.B
85          arbInSeq(srcIdx).bits.addr := 0.U
86        }
87      }
88    }
89  }
90
91  private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getVfRfReadValidBundle(xx.valid)).toSeq).toSeq
92
93  vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) =>
94    arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) =>
95      val srcIndices: Seq[Int] = VfRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted
96      for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) {
97        if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) {
98          arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid
99          arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr
100        } else {
101          arbInSeq(srcIdx).valid := false.B
102          arbInSeq(srcIdx).bits.addr := 0.U
103        }
104      }
105    }
106  }
107
108  private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B)).toSeq).toSeq
109  private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.getVfWen.getOrElse(false.B)).toSeq).toSeq
110
111  intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) =>
112    arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) =>
113      arbIn.valid := inRFWriteReq
114    }
115  }
116
117  vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) =>
118    arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) =>
119      arbIn.valid := inRFWriteReq
120    }
121  }
122
123  private val intSchdParams = params.schdParams(IntScheduler())
124  private val vfSchdParams = params.schdParams(VfScheduler())
125  private val memSchdParams = params.schdParams(MemScheduler())
126
127  private val numIntRfReadByExu = intSchdParams.numIntRfReadByExu + memSchdParams.numIntRfReadByExu
128  private val numVfRfReadByExu = vfSchdParams.numVfRfReadByExu + memSchdParams.numVfRfReadByExu
129  // Todo: limit read port
130  private val numIntR = numIntRfReadByExu
131  private val numVfR = numVfRfReadByExu
132  println(s"[DataPath] RegFile read req needed by Exu: Int(${numIntRfReadByExu}), Vf(${numVfRfReadByExu})")
133  println(s"[DataPath] RegFile read port: Int(${numIntR}), Vf(${numVfR})")
134
135  private val schdParams = params.allSchdParams
136
137  private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W)))
138  private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W)))
139  private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool()))
140  private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W)))
141  private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W)))
142
143  private val vfRfSplitNum = VLEN / XLEN
144  private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W)))
145  private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W)))
146  private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool())))
147  private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W)))
148  private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W)))
149
150  private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] =
151    if (env.AlwaysBasicDiff || env.EnableDifftest) {
152      Some(Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W))))
153    } else { None }
154  private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] =
155    if (env.AlwaysBasicDiff || env.EnableDifftest) {
156      Some(Wire(Vec(32 + 32 + 1, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(32 + 32 + 1, UInt(VLEN.W))))
157    } else { None }
158
159  private val fpDebugReadData: Option[Vec[UInt]] =
160    if (env.AlwaysBasicDiff || env.EnableDifftest) {
161      Some(Wire(Vec(32, UInt(XLEN.W))))
162    } else { None }
163  private val vecDebugReadData: Option[Vec[UInt]] =
164    if (env.AlwaysBasicDiff || env.EnableDifftest) {
165      Some(Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0))
166    } else { None }
167  private val vconfigDebugReadData: Option[UInt] =
168    if (env.AlwaysBasicDiff || env.EnableDifftest) {
169      Some(Wire(UInt(64.W)))
170    } else { None }
171
172
173  fpDebugReadData.foreach(_ := vfDebugRead
174    .get._2
175    .slice(0, 32)
176    .map(_(63, 0))
177  ) // fp only used [63, 0]
178  vecDebugReadData.foreach(_ := vfDebugRead
179    .get._2
180    .slice(32, 64)
181    .map(x => Seq(x(63, 0), x(127, 64))).flatten
182  )
183  vconfigDebugReadData.foreach(_ := vfDebugRead
184    .get._2(64)(63, 0)
185  )
186
187  io.debugVconfig.foreach(_ := vconfigDebugReadData.get)
188
189  IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata,
190    debugReadAddr = intDebugRead.map(_._1),
191    debugReadData = intDebugRead.map(_._2))
192  VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata,
193    debugReadAddr = vfDebugRead.map(_._1),
194    debugReadData = vfDebugRead.map(_._2))
195
196  intRfWaddr := io.fromIntWb.map(_.addr).toSeq
197  intRfWdata := io.fromIntWb.map(_.data).toSeq
198  intRfWen := io.fromIntWb.map(_.wen).toSeq
199
200  for (portIdx <- intRfRaddr.indices) {
201    if (intRFReadArbiter.io.out.isDefinedAt(portIdx))
202      intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr
203    else
204      intRfRaddr(portIdx) := 0.U
205  }
206
207  vfRfWaddr := io.fromVfWb.map(_.addr).toSeq
208  vfRfWdata := io.fromVfWb.map(_.data).toSeq
209  vfRfWen.foreach(_.zip(io.fromVfWb.map(_.wen)).foreach { case (wenSink, wenSource) => wenSink := wenSource } )// Todo: support fp multi-write
210
211  for (portIdx <- vfRfRaddr.indices) {
212    if (vfRFReadArbiter.io.out.isDefinedAt(portIdx))
213      vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr
214    else
215      vfRfRaddr(portIdx) := 0.U
216  }
217
218  vfRfRaddr(VCONFIG_PORT) := io.vconfigReadPort.addr
219  io.vconfigReadPort.data := vfRfRdata(VCONFIG_PORT)
220
221  intDebugRead.foreach { case (addr, _) =>
222    addr := io.debugIntRat.get
223  }
224
225  vfDebugRead.foreach { case (addr, _) =>
226    addr := io.debugFpRat.get ++ io.debugVecRat.get :+ io.debugVconfigRat.get
227  }
228  println(s"[DataPath] " +
229    s"has intDebugRead: ${intDebugRead.nonEmpty}, " +
230    s"has vfDebugRead: ${vfDebugRead.nonEmpty}")
231
232  val s1_addrOHs = Reg(MixedVec(
233    fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType).toSeq)).toSeq
234  ))
235  val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec(
236    toExu.map(x => MixedVec(x.map(_.valid.cloneType).toSeq)).toSeq
237  ))
238  val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType).toSeq)).toSeq))
239  val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType))))) // Todo
240  val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire)))))
241
242  val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType)))))
243  val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType)))))
244
245  val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs))
246
247  println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}")
248  s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U)))
249  s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) =>
250      iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) =>
251        val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[IntRD]) else x).flatten
252        assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size")
253        iuRdata.zip(realIuCfg)
254          .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[IntRD] }
255          .foreach { case (sink, cfg) => sink := intRfRdata(cfg.port) }
256      }
257  }
258
259  println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}")
260  s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U)))
261  s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) =>
262      iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) =>
263        val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[VfRD]) else x).flatten
264        assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size")
265        iuRdata.zip(realIuCfg)
266          .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VfRD] }
267          .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.port) }
268      }
269  }
270
271  for (i <- fromIQ.indices) {
272    for (j <- fromIQ(i).indices) {
273      // IQ(s0) --[Ctrl]--> s1Reg ---------- begin
274      // refs
275      val s1_valid = s1_toExuValid(i)(j)
276      val s1_ready = s1_toExuReady(i)(j)
277      val s1_data = s1_toExuData(i)(j)
278      val s1_addrOH = s1_addrOHs(i)(j)
279      val s0 = fromIQ(i)(j) // s0
280      val srcNotBlock = s0.bits.common.dataSources.zip(intRdArbWinner(i)(j) zip vfRdArbWinner(i)(j)).map { case (source, win) =>
281        !source.readReg || win._1 && win._2
282      }.reduce(_ && _)
283      val notBlock = srcNotBlock && intWbNotBlock(i)(j) && vfWbNotBlock(i)(j)
284      val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush)))
285      val s1_cancel = og1FailedVec2(i)(j)
286      val s1_ldCancel = LoadShouldCancel(s0.bits.common.loadDependency, io.ldCancel)
287      when (s0.fire && !s1_flush && notBlock && !s1_cancel && !s1_ldCancel) {
288        s1_valid := s0.valid
289        s1_data.fromIssueBundle(s0.bits) // no src data here
290        s1_addrOH := s0.bits.addrOH
291      }.otherwise {
292        s1_valid := false.B
293      }
294      s0.ready := (s1_ready || !s1_valid) && notBlock
295      // IQ(s0) --[Ctrl]--> s1Reg ---------- end
296
297      // IQ(s0) --[Data]--> s1Reg ---------- begin
298      // imm extract
299      when (s0.fire && !s1_flush && notBlock) {
300        if (s1_data.params.immType.nonEmpty && s1_data.src.size > 1) {
301          // rs1 is always int reg, rs2 may be imm
302          when(SrcType.isImm(s0.bits.srcType(1))) {
303            s1_data.src(1) := ImmExtractor(
304              s0.bits.common.imm,
305              s0.bits.immType,
306              s1_data.params.dataBitsMax,
307              s1_data.params.immType.map(_.litValue)
308            )
309          }
310        }
311        if (s1_data.params.hasJmpFu) {
312          when(SrcType.isPc(s0.bits.srcType(0))) {
313            s1_data.src(0) := SignExt(s0.bits.common.pc.get, XLEN)
314          }
315        } else if (s1_data.params.hasVecFu) {
316          // Fuck off riscv vector imm!!! Why not src1???
317          when(SrcType.isImm(s0.bits.srcType(0))) {
318            s1_data.src(0) := ImmExtractor(
319              s0.bits.common.imm,
320              s0.bits.immType,
321              s1_data.params.dataBitsMax,
322              s1_data.params.immType.map(_.litValue)
323            )
324          }
325        } else if (s1_data.params.hasLoadFu) {
326          // dirty code for fused_lui_load
327          when(SrcType.isImm(s0.bits.srcType(0))) {
328            s1_data.src(0) := SignExt(ImmUnion.U.toImm32(s0.bits.common.imm(s0.bits.common.imm.getWidth - 1, ImmUnion.I.len)), XLEN)
329          }
330        }
331      }
332      // IQ(s0) --[Data]--> s1Reg ---------- end
333    }
334  }
335
336  private val fromIQFire = fromIQ.map(_.map(_.fire))
337  private val toExuFire = toExu.map(_.map(_.fire))
338  toIQs.zipWithIndex.foreach {
339    case(toIQ, iqIdx) =>
340      toIQ.zipWithIndex.foreach {
341        case (toIU, iuIdx) =>
342          // IU: issue unit
343          val og0resp = toIU.og0resp
344          og0FailedVec2(iqIdx)(iuIdx) := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx))
345          og0resp.valid := og0FailedVec2(iqIdx)(iuIdx)
346          og0resp.bits.respType := RSFeedbackType.rfArbitFail
347          og0resp.bits.dataInvalidSqIdx := DontCare
348          og0resp.bits.robIdx := fromIQ(iqIdx)(iuIdx).bits.common.robIdx
349          og0resp.bits.rfWen := fromIQ(iqIdx)(iuIdx).bits.common.rfWen.getOrElse(false.B)
350          og0resp.bits.fuType := fromIQ(iqIdx)(iuIdx).bits.common.fuType
351
352          val og1resp = toIU.og1resp
353          og1FailedVec2(iqIdx)(iuIdx) := s1_toExuValid(iqIdx)(iuIdx) && !toExuFire(iqIdx)(iuIdx)
354          og1resp.valid := s1_toExuValid(iqIdx)(iuIdx)
355          og1resp.bits.respType := Mux(
356            !og1FailedVec2(iqIdx)(iuIdx),
357            if (toIU.issueQueueParams.isMemAddrIQ) RSFeedbackType.fuUncertain else RSFeedbackType.fuIdle,
358            RSFeedbackType.fuBusy
359          )
360          og1resp.bits.dataInvalidSqIdx := DontCare
361          og1resp.bits.robIdx := s1_toExuData(iqIdx)(iuIdx).robIdx
362          og1resp.bits.rfWen := s1_toExuData(iqIdx)(iuIdx).rfWen.getOrElse(false.B)
363          og1resp.bits.fuType := s1_toExuData(iqIdx)(iuIdx).fuType
364      }
365  }
366
367  io.og0CancelOH := VecInit(fromFlattenIQ.map(x => x.valid && !x.fire)).asUInt
368  io.og1CancelOH := VecInit(toFlattenExu.map(x => x.valid && !x.fire)).asUInt
369
370  io.cancelToBusyTable.zipWithIndex.foreach { case (cancel, i) =>
371    cancel.valid := fromFlattenIQ(i).valid && !fromFlattenIQ(i).fire && {
372      if (fromFlattenIQ(i).bits.common.rfWen.isDefined)
373        fromFlattenIQ(i).bits.common.rfWen.get && fromFlattenIQ(i).bits.common.pdest =/= 0.U
374      else
375        true.B
376    }
377    cancel.bits.rfWen := fromFlattenIQ(i).bits.common.rfWen.getOrElse(false.B)
378    cancel.bits.fpWen := fromFlattenIQ(i).bits.common.fpWen.getOrElse(false.B)
379    cancel.bits.vecWen := fromFlattenIQ(i).bits.common.vecWen.getOrElse(false.B)
380    cancel.bits.pdest := fromFlattenIQ(i).bits.common.pdest
381  }
382
383  for (i <- toExu.indices) {
384    for (j <- toExu(i).indices) {
385      // s1Reg --[Ctrl]--> exu(s1) ---------- begin
386      // refs
387      val sinkData = toExu(i)(j).bits
388      // assign
389      toExu(i)(j).valid := s1_toExuValid(i)(j)
390      s1_toExuReady(i)(j) := toExu(i)(j).ready
391      sinkData := s1_toExuData(i)(j)
392      // s1Reg --[Ctrl]--> exu(s1) ---------- end
393
394      // s1Reg --[Data]--> exu(s1) ---------- begin
395      // data source1: preg read data
396      for (k <- sinkData.src.indices) {
397        val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k)
398
399        val readRfMap: Seq[(Bool, UInt)] = (Seq(None) :+
400          (if (s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty)
401            Some(SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k))
402          else None) :+
403          (if (s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VfRegSrcDataSet).nonEmpty)
404            Some(SrcType.isVfp(s1_srcType(i)(j)(k))-> s1_vfPregRData(i)(j)(k))
405          else None)
406        ).filter(_.nonEmpty).map(_.get)
407        if (readRfMap.nonEmpty)
408          sinkData.src(k) := Mux1H(readRfMap)
409      }
410
411      // data source2: extracted imm and pc saved in s1Reg
412      if (sinkData.params.immType.nonEmpty && sinkData.src.size > 1) {
413        when(SrcType.isImm(s1_srcType(i)(j)(1))) {
414          sinkData.src(1) := s1_toExuData(i)(j).src(1)
415        }
416      }
417      if (sinkData.params.hasJmpFu) {
418        when(SrcType.isPc(s1_srcType(i)(j)(0))) {
419          sinkData.src(0) := s1_toExuData(i)(j).src(0)
420        }
421      } else if (sinkData.params.hasVecFu) {
422        when(SrcType.isImm(s1_srcType(i)(j)(0))) {
423          sinkData.src(0) := s1_toExuData(i)(j).src(0)
424        }
425      } else if (sinkData.params.hasLoadFu) {
426        when(SrcType.isImm(s1_srcType(i)(j)(0))) {
427          sinkData.src(0) := s1_toExuData(i)(j).src(0)
428        }
429      }
430      // s1Reg --[Data]--> exu(s1) ---------- end
431    }
432  }
433
434  if (env.AlwaysBasicDiff || env.EnableDifftest) {
435    val delayedCnt = 2
436    val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt)
437    difftestArchIntRegState.coreid := io.hartId
438    difftestArchIntRegState.value := intDebugRead.get._2
439
440    val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt)
441    difftestArchFpRegState.coreid := io.hartId
442    difftestArchFpRegState.value := fpDebugReadData.get
443
444    val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt)
445    difftestArchVecRegState.coreid := io.hartId
446    difftestArchVecRegState.value := vecDebugReadData.get
447  }
448}
449
450class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle {
451  // params
452  private val intSchdParams = params.schdParams(IntScheduler())
453  private val vfSchdParams = params.schdParams(VfScheduler())
454  private val memSchdParams = params.schdParams(MemScheduler())
455  private val exuParams = params.allExuParams
456  // bundles
457  val hartId = Input(UInt(8.W))
458
459  val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect))
460
461  // Todo: check if this can be removed
462  val vconfigReadPort = new RfReadPort(XLEN, PhyRegIdxWidth)
463
464  val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle())))))
465
466  val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] =
467    Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle)))
468
469  val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] =
470    Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle)))
471
472  val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle)))
473
474  val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle))
475
476  val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle))
477
478  val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle))
479
480  val og0CancelOH = Output(ExuOH(backendParams.numExu))
481
482  val og1CancelOH = Output(ExuOH(backendParams.numExu))
483
484  val ldCancel = Vec(backendParams.LduCnt, Flipped(new LoadCancelIO))
485
486  val cancelToBusyTable = Vec(backendParams.numExu, ValidIO(new CancelSignal))
487
488  val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle
489
490  val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle)
491
492  val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle
493
494  val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle)
495
496  val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle)
497
498  val debugIntRat     = if (params.debugEn) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None
499  val debugFpRat      = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None
500  val debugVecRat     = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None
501  val debugVconfigRat = if (params.debugEn) Some(Input(UInt(vfSchdParams.pregIdxWidth.W))) else None
502  val debugVconfig    = if (params.debugEn) Some(Output(UInt(XLEN.W))) else None
503}
504