1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule} 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility._ 9import utils.SeqUtils._ 10import utils._ 11import xiangshan._ 12import xiangshan.backend.{BackendParams, ExcpModToVprf, PcToDataPathIO, VprfToExcpMod} 13import xiangshan.backend.Bundles._ 14import xiangshan.backend.decode.ImmUnion 15import xiangshan.backend.datapath.DataConfig._ 16import xiangshan.backend.datapath.RdConfig._ 17import xiangshan.backend.issue.{FpScheduler, ImmExtractor, IntScheduler, MemScheduler, VfScheduler} 18import xiangshan.backend.issue.EntryBundles._ 19import xiangshan.backend.regfile._ 20import xiangshan.backend.regcache._ 21import xiangshan.backend.fu.FuType.is0latency 22import xiangshan.mem.{LqPtr, SqPtr} 23 24class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { 25 override def shouldBeInlined: Boolean = false 26 27 private implicit val dpParams: BackendParams = params 28 lazy val module = new DataPathImp(this) 29 30 println(s"[DataPath] Preg Params: ") 31 println(s"[DataPath] Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ") 32 println(s"[DataPath] Fp R(${params.getRfReadSize(FpData())}), W(${params.getRfWriteSize(FpData())}) ") 33 println(s"[DataPath] Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ") 34 println(s"[DataPath] V0 R(${params.getRfReadSize(V0Data())}), W(${params.getRfWriteSize(V0Data())}) ") 35 println(s"[DataPath] Vl R(${params.getRfReadSize(VlData())}), W(${params.getRfWriteSize(VlData())}) ") 36} 37 38class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams) 39 extends LazyModuleImp(wrapper) with HasXSParameter { 40 41 val io = IO(new DataPathIO()) 42 43 private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu) 44 private val (fromFpIQ, toFpIQ, toFpExu) = (io.fromFpIQ, io.toFpIQ, io.toFpExu) 45 private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu) 46 private val (fromVfIQ, toVfIQ, toVfExu ) = (io.fromVfIQ, io.toVfIQ, io.toVecExu) 47 private val (fromVecExcp, toVecExcp) = (io.fromVecExcpMod, io.toVecExcpMod) 48 49 println(s"[DataPath] IntIQ(${fromIntIQ.size}), FpIQ(${fromFpIQ.size}), VecIQ(${fromVfIQ.size}), MemIQ(${fromMemIQ.size})") 50 println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), FpExu(${fromFpIQ.map(_.size).sum}), VecExu(${fromVfIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})") 51 52 // just refences for convience 53 private val fromIQ: Seq[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = (fromIntIQ ++ fromFpIQ ++ fromVfIQ ++ fromMemIQ).toSeq 54 55 private val toIQs = toIntIQ ++ toFpIQ ++ toVfIQ ++ toMemIQ 56 57 private val toExu: Seq[MixedVec[DecoupledIO[ExuInput]]] = (toIntExu ++ toFpExu ++ toVfExu ++ toMemExu).toSeq 58 59 private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten 60 61 private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten 62 63 private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams)) 64 private val fpWbBusyArbiter = Module(new FpRFWBCollideChecker(backendParams)) 65 private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams)) 66 private val v0WbBusyArbiter = Module(new V0RFWBCollideChecker(backendParams)) 67 private val vlWbBusyArbiter = Module(new VlRFWBCollideChecker(backendParams)) 68 69 private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams)) 70 private val fpRFReadArbiter = Module(new FpRFReadArbiter(backendParams)) 71 private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams)) 72 private val v0RFReadArbiter = Module(new V0RFReadArbiter(backendParams)) 73 private val vlRFReadArbiter = Module(new VlRFReadArbiter(backendParams)) 74 75 private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 76 private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 77 78 // port -> win 79 private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 80 private val fpRdArbWinner: Seq2[MixedVec[Bool]] = fpRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 81 private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 82 private val v0RdArbWinner: Seq2[MixedVec[Bool]] = v0RFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 83 private val vlRdArbWinner: Seq2[MixedVec[Bool]] = vlRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 84 85 private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 86 private val fpWbNotBlock: Seq[MixedVec[Bool]] = fpWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 87 private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 88 private val v0WbNotBlock: Seq[MixedVec[Bool]] = v0WbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 89 private val vlWbNotBlock: Seq[MixedVec[Bool]] = vlWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 90 91 private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR)) 92 private val fpRdNotBlock: Seq2[Bool] = fpRdArbWinner.map(_.map(_.asUInt.andR)) 93 private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR)) 94 private val v0RdNotBlock: Seq2[Bool] = v0RdArbWinner.map(_.map(_.asUInt.andR)) 95 private val vlRdNotBlock: Seq2[Bool] = vlRdArbWinner.map(_.map(_.asUInt.andR)) 96 97 private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 98 private val fpRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 99 private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 100 private val v0RFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 101 private val vlRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 102 103 private val allDataSources: Seq[Seq[Vec[DataSource]]] = fromIQ.map(x => x.map(xx => xx.bits.common.dataSources).toSeq) 104 private val allNumRegSrcs: Seq[Seq[Int]] = fromIQ.map(x => x.map(xx => xx.bits.exuParams.numRegSrc).toSeq) 105 106 intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 107 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 108 val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData()) 109 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 110 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 111 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 112 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 113 } else { 114 arbInSeq(srcIdx).valid := false.B 115 arbInSeq(srcIdx).bits.addr := 0.U 116 } 117 } 118 } 119 } 120 fpRFReadArbiter.io.in.zip(fpRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 121 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 122 val srcIndices: Seq[Int] = FpRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 123 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 124 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 125 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 126 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 127 } else { 128 arbInSeq(srcIdx).valid := false.B 129 arbInSeq(srcIdx).bits.addr := 0.U 130 } 131 } 132 } 133 } 134 135 vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 136 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 137 val srcIndices: Seq[Int] = VecRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 138 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 139 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 140 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 141 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 142 } else { 143 arbInSeq(srcIdx).valid := false.B 144 arbInSeq(srcIdx).bits.addr := 0.U 145 } 146 } 147 } 148 } 149 150 v0RFReadArbiter.io.in.zip(v0RFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 151 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 152 val srcIndices: Seq[Int] = V0RegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 153 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 154 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 155 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 156 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 157 } else { 158 arbInSeq(srcIdx).valid := false.B 159 arbInSeq(srcIdx).bits.addr := 0.U 160 } 161 } 162 } 163 } 164 165 vlRFReadArbiter.io.in.zip(vlRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 166 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 167 val srcIndices: Seq[Int] = VlRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 168 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 169 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 170 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 171 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 172 } else { 173 arbInSeq(srcIdx).valid := false.B 174 arbInSeq(srcIdx).bits.addr := 0.U 175 } 176 } 177 } 178 } 179 180 private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B)).toSeq).toSeq 181 private val fpRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.fpWen.getOrElse(false.B)).toSeq).toSeq 182 private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.vecWen.getOrElse(false.B)).toSeq).toSeq 183 private val v0RFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.v0Wen.getOrElse(false.B)).toSeq).toSeq 184 private val vlRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.vlWen.getOrElse(false.B)).toSeq).toSeq 185 186 intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 187 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 188 arbIn.valid := inRFWriteReq 189 } 190 } 191 192 fpWbBusyArbiter.io.in.zip(fpRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 193 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 194 arbIn.valid := inRFWriteReq 195 } 196 } 197 198 vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 199 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 200 arbIn.valid := inRFWriteReq 201 } 202 } 203 204 v0WbBusyArbiter.io.in.zip(v0RFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 205 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 206 arbIn.valid := inRFWriteReq 207 } 208 } 209 210 vlWbBusyArbiter.io.in.zip(vlRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 211 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 212 arbIn.valid := inRFWriteReq 213 } 214 } 215 216 private val intSchdParams = params.schdParams(IntScheduler()) 217 private val fpSchdParams = params.schdParams(FpScheduler()) 218 private val vfSchdParams = params.schdParams(VfScheduler()) 219 private val memSchdParams = params.schdParams(MemScheduler()) 220 221 private val schdParams = params.allSchdParams 222 223 private val pcReadValid = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathValid)) 224 private val pcReadFtqPtr = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqPtr)) 225 private val pcReadFtqOffset = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqOffset)) 226 private val targetPCRdata = io.fromPcTargetMem.toDataPathTargetPC 227 private val pcRdata = io.fromPcTargetMem.toDataPathPC 228 private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W))) 229 private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W))) 230 private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool())) 231 private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W))) 232 private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W))) 233 234 private val fpRfRaddr = Wire(Vec(params.numPregRd(FpData()), UInt(fpSchdParams.pregIdxWidth.W))) 235 private val fpRfRdata = Wire(Vec(params.numPregRd(FpData()), UInt(fpSchdParams.rfDataWidth.W))) 236 private val fpRfWen = Wire(Vec(io.fromFpWb.length, Bool())) 237 private val fpRfWaddr = Wire(Vec(io.fromFpWb.length, UInt(fpSchdParams.pregIdxWidth.W))) 238 private val fpRfWdata = Wire(Vec(io.fromFpWb.length, UInt(fpSchdParams.rfDataWidth.W))) 239 240 private val vfRfSplitNum = VLEN / XLEN 241 private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W))) 242 private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W))) 243 private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool()))) 244 private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W))) 245 private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W))) 246 247 private val v0RfSplitNum = VLEN / XLEN 248 private val v0RfRaddr = Wire(Vec(params.numPregRd(V0Data()), UInt(log2Up(V0PhyRegs).W))) 249 private val v0RfRdata = Wire(Vec(params.numPregRd(V0Data()), UInt(V0Data().dataWidth.W))) 250 private val v0RfWen = Wire(Vec(v0RfSplitNum, Vec(io.fromV0Wb.length, Bool()))) 251 private val v0RfWaddr = Wire(Vec(io.fromV0Wb.length, UInt(log2Up(V0PhyRegs).W))) 252 private val v0RfWdata = Wire(Vec(io.fromV0Wb.length, UInt(V0Data().dataWidth.W))) 253 254 private val vlRfRaddr = Wire(Vec(params.numPregRd(VlData()), UInt(log2Up(VlPhyRegs).W))) 255 private val vlRfRdata = Wire(Vec(params.numPregRd(VlData()), UInt(VlData().dataWidth.W))) 256 private val vlRfWen = Wire(Vec(io.fromVlWb.length, Bool())) 257 private val vlRfWaddr = Wire(Vec(io.fromVlWb.length, UInt(log2Up(VlPhyRegs).W))) 258 private val vlRfWdata = Wire(Vec(io.fromVlWb.length, UInt(VlData().dataWidth.W))) 259 260 val pcReadFtqPtrFormIQ = fromIntIQ.flatten.filter(x => x.bits.exuParams.needPc) 261 assert(pcReadFtqPtrFormIQ.size == pcReadFtqPtr.size, s"pcReadFtqPtrFormIQ.size ${pcReadFtqPtrFormIQ.size} not equal pcReadFtqPtr.size ${pcReadFtqPtr.size}") 262 pcReadValid.zip(pcReadFtqPtrFormIQ.map(_.valid)).map(x => x._1 := x._2) 263 pcReadFtqPtr.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqIdx.get)).map(x => x._1 := x._2) 264 pcReadFtqOffset.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqOffset.get)).map(x => x._1 := x._2) 265 io.fromPcTargetMem.fromDataPathValid := pcReadValid 266 io.fromPcTargetMem.fromDataPathFtqPtr := pcReadFtqPtr 267 io.fromPcTargetMem.fromDataPathFtqOffset := pcReadFtqOffset 268 269 private val intDiffRead: Option[(Vec[UInt], Vec[UInt])] = 270 OptionWrapper(backendParams.basicDebugEn, (Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W))))) 271 private val fpDiffRead: Option[(Vec[UInt], Vec[UInt])] = 272 OptionWrapper(backendParams.basicDebugEn, (Wire(Vec(32, UInt(fpSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W))))) 273 private val vfDiffRead: Option[(Vec[UInt], Vec[UInt])] = 274 OptionWrapper(backendParams.basicDebugEn, (Wire(Vec(31, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(31, UInt(VLEN.W))))) 275 private val v0DiffRead: Option[(Vec[UInt], Vec[UInt])] = 276 OptionWrapper(backendParams.basicDebugEn, (Wire(Vec(1, UInt(log2Up(V0PhyRegs).W))), Wire(Vec(1, UInt(V0Data().dataWidth.W))))) 277 private val vlDiffRead: Option[(Vec[UInt], Vec[UInt])] = 278 OptionWrapper(backendParams.basicDebugEn, (Wire(Vec(1, UInt(log2Up(VlPhyRegs).W))), Wire(Vec(1, UInt(VlData().dataWidth.W))))) 279 280 private val fpDiffReadData: Option[Vec[UInt]] = 281 OptionWrapper(backendParams.basicDebugEn, Wire(Vec(32, UInt(XLEN.W)))) 282 private val vecDiffReadData: Option[Vec[UInt]] = 283 OptionWrapper(backendParams.basicDebugEn, Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0)) 284 private val vlDiffReadData: Option[UInt] = 285 OptionWrapper(backendParams.basicDebugEn, Wire(UInt(VlData().dataWidth.W))) 286 287 288 fpDiffReadData.foreach(_ := fpDiffRead 289 .get._2 290 .slice(0, 32) 291 .map(_(63, 0)) 292 ) // fp only used [63, 0] 293 vecDiffReadData.foreach(_ := 294 v0DiffRead 295 .get._2 296 .slice(0, 1) 297 .map(x => Seq(x(63, 0), x(127, 64))).flatten ++ 298 vfDiffRead 299 .get._2 300 .slice(0, 31) 301 .map(x => Seq(x(63, 0), x(127, 64))).flatten 302 ) 303 vlDiffReadData.foreach(_ := vlDiffRead 304 .get._2(0) 305 ) 306 307 io.diffVl.foreach(_ := vlDiffReadData.get) 308 309 IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata, 310 bankNum = 1, 311 debugReadAddr = intDiffRead.map(_._1), 312 debugReadData = intDiffRead.map(_._2) 313 ) 314 FpRegFile("FpRegFile", fpSchdParams.numPregs, fpRfRaddr, fpRfRdata, fpRfWen, fpRfWaddr, fpRfWdata, 315 bankNum = 1, 316 debugReadAddr = fpDiffRead.map(_._1), 317 debugReadData = fpDiffRead.map(_._2) 318 ) 319 VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata, 320 debugReadAddr = vfDiffRead.map(_._1), 321 debugReadData = vfDiffRead.map(_._2) 322 ) 323 VfRegFile("V0RegFile", V0PhyRegs, v0RfSplitNum, v0RfRaddr, v0RfRdata, v0RfWen, v0RfWaddr, v0RfWdata, 324 debugReadAddr = v0DiffRead.map(_._1), 325 debugReadData = v0DiffRead.map(_._2) 326 ) 327 FpRegFile("VlRegFile", VlPhyRegs, vlRfRaddr, vlRfRdata, vlRfWen, vlRfWaddr, vlRfWdata, 328 bankNum = 1, 329 isVlRegfile = true, 330 debugReadAddr = vlDiffRead.map(_._1), 331 debugReadData = vlDiffRead.map(_._2) 332 ) 333 334 intRfWaddr := io.fromIntWb.map(x => RegEnable(x.addr, x.wen)).toSeq 335 intRfWdata := io.fromIntWb.map(x => RegEnable(x.data, x.wen)).toSeq 336 intRfWen := RegNext(VecInit(io.fromIntWb.map(_.wen).toSeq)) 337 338 for (portIdx <- intRfRaddr.indices) { 339 if (intRFReadArbiter.io.out.isDefinedAt(portIdx)) 340 intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr 341 else 342 intRfRaddr(portIdx) := 0.U 343 } 344 345 fpRfWaddr := io.fromFpWb.map(x => RegEnable(x.addr, x.wen)).toSeq 346 fpRfWdata := io.fromFpWb.map(x => RegEnable(x.data, x.wen)).toSeq 347 fpRfWen := RegNext(VecInit(io.fromFpWb.map(_.wen).toSeq)) 348 349 for (portIdx <- fpRfRaddr.indices) { 350 if (fpRFReadArbiter.io.out.isDefinedAt(portIdx)) 351 fpRfRaddr(portIdx) := fpRFReadArbiter.io.out(portIdx).bits.addr 352 else 353 fpRfRaddr(portIdx) := 0.U 354 } 355 356 vfRfWaddr := io.fromVfWb.map(x => RegEnable(x.addr, x.wen)).toSeq 357 vfRfWdata := io.fromVfWb.map(x => RegEnable(x.data, x.wen)).toSeq 358 vfRfWen.foreach(_.zip(io.fromVfWb.map(x => RegNext(x.wen))).foreach { case (wenSink, wenSource) => wenSink := wenSource } ) 359 360 for (portIdx <- vfRfRaddr.indices) { 361 if (vfRFReadArbiter.io.out.isDefinedAt(portIdx)) 362 vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr 363 else 364 vfRfRaddr(portIdx) := 0.U 365 } 366 367 v0RfWaddr := io.fromV0Wb.map(x => RegEnable(x.addr, x.wen)).toSeq 368 v0RfWdata := io.fromV0Wb.map(x => RegEnable(x.data, x.wen)).toSeq 369 v0RfWen.foreach(_.zip(io.fromV0Wb.map(x => RegNext(x.wen))).foreach { case (wenSink, wenSource) => wenSink := wenSource } ) 370 371 for (portIdx <- v0RfRaddr.indices) { 372 if (v0RFReadArbiter.io.out.isDefinedAt(portIdx)) 373 v0RfRaddr(portIdx) := v0RFReadArbiter.io.out(portIdx).bits.addr 374 else 375 v0RfRaddr(portIdx) := 0.U 376 } 377 378 private val vecExcpUseVecRdPorts = Seq(6, 7, 8, 9, 10, 11, 0, 1) 379 private val vecExcpUseVecWrPorts = Seq(1, 4, 5, 3) 380 private val vecExcpUseV0RdPorts = Seq(2, 3) 381 private val vecExcpUsev0WrPorts = Seq(4) 382 383 private var v0RdPortsIter: Iterator[Int] = vecExcpUseV0RdPorts.iterator 384 private val v0WrPortsIter: Iterator[Int] = vecExcpUsev0WrPorts.iterator 385 386 for (i <- fromVecExcp.r.indices) { 387 when (fromVecExcp.r(i).valid && !fromVecExcp.r(i).bits.isV0) { 388 vfRfRaddr(vecExcpUseVecRdPorts(i)) := fromVecExcp.r(i).bits.addr 389 } 390 if (i % maxMergeNumPerCycle == 0) { 391 val v0RdPort = v0RdPortsIter.next() 392 when (fromVecExcp.r(i).valid && fromVecExcp.r(i).bits.isV0) { 393 v0RfRaddr(v0RdPort) := fromVecExcp.r(i).bits.addr 394 } 395 } 396 } 397 398 for (i <- fromVecExcp.w.indices) { 399 when (fromVecExcp.w(i).valid && !fromVecExcp.w(i).bits.isV0) { 400 val vecWrPort = vecExcpUseVecWrPorts(i) 401 vfRfWen.foreach(_(vecWrPort) := true.B) 402 vfRfWaddr(vecWrPort) := fromVecExcp.w(i).bits.newVdAddr 403 vfRfWdata(vecWrPort) := fromVecExcp.w(i).bits.newVdData 404 } 405 if (i % maxMergeNumPerCycle == 0) { 406 when(fromVecExcp.w(i).valid && fromVecExcp.w(i).bits.isV0) { 407 val v0WrPort = v0WrPortsIter.next() 408 v0RfWen.foreach(_(v0WrPort) := true.B) 409 v0RfWaddr(v0WrPort) := fromVecExcp.w(i).bits.newVdAddr 410 v0RfWdata(v0WrPort) := fromVecExcp.w(i).bits.newVdData 411 } 412 } 413 } 414 415 vlRfWaddr := io.fromVlWb.map(x => RegEnable(x.addr, x.wen)).toSeq 416 vlRfWdata := io.fromVlWb.map(x => RegEnable(x.data, x.wen)).toSeq 417 vlRfWen := io.fromVlWb.map(x => RegNext(x.wen)).toSeq 418 419 for (portIdx <- vlRfRaddr.indices) { 420 if (vlRFReadArbiter.io.out.isDefinedAt(portIdx)) 421 vlRfRaddr(portIdx) := vlRFReadArbiter.io.out(portIdx).bits.addr 422 else 423 vlRfRaddr(portIdx) := 0.U 424 } 425 426 427 intDiffRead.foreach { case (addr, _) => 428 addr := io.diffIntRat.get 429 } 430 431 fpDiffRead.foreach { case (addr, _) => 432 addr := io.diffFpRat.get 433 } 434 435 vfDiffRead.foreach { case (addr, _) => 436 addr := io.diffVecRat.get 437 } 438 v0DiffRead.foreach { case (addr, _) => 439 addr := io.diffV0Rat.get 440 } 441 vlDiffRead.foreach { case (addr, _) => 442 addr := io.diffVlRat.get 443 } 444 445 println(s"[DataPath] " + 446 s"has intDiffRead: ${intDiffRead.nonEmpty}, " + 447 s"has fpDiffRead: ${fpDiffRead.nonEmpty}, " + 448 s"has vecDiffRead: ${vfDiffRead.nonEmpty}, " + 449 s"has v0DiffRead: ${v0DiffRead.nonEmpty}, " + 450 s"has vlDiffRead: ${vlDiffRead.nonEmpty}") 451 452 // regcache 453 private val regCache = Module(new RegCache()) 454 455 def IssueBundle2RCReadPort(issue: DecoupledIO[IssueQueueIssueBundle]): Vec[RCReadPort] = { 456 val readPorts = Wire(Vec(issue.bits.exuParams.numIntSrc, new RCReadPort(params.intSchdParams.get.rfDataWidth, RegCacheIdxWidth))) 457 readPorts.zipWithIndex.foreach{ case (r, idx) => 458 r.ren := issue.valid && issue.bits.common.dataSources(idx).readRegCache 459 r.addr := issue.bits.rcIdx.get(idx) 460 r.data := DontCare 461 } 462 readPorts 463 } 464 465 private val regCacheReadReq = fromIntIQ.flatten.filter(_.bits.exuParams.numIntSrc > 0).flatMap(IssueBundle2RCReadPort(_)) ++ 466 fromMemIQ.flatten.filter(_.bits.exuParams.numIntSrc > 0).flatMap(IssueBundle2RCReadPort(_)) 467 private val regCacheReadData = regCache.io.readPorts.map(_.data) 468 469 println(s"[DataPath] regCache readPorts size: ${regCache.io.readPorts.size}, regCacheReadReq size: ${regCacheReadReq.size}") 470 require(regCache.io.readPorts.size == regCacheReadReq.size, "reg cache's readPorts size should be equal to regCacheReadReq") 471 472 regCache.io.readPorts.zip(regCacheReadReq).foreach{ case (r, req) => 473 r.ren := req.ren 474 r.addr := req.addr 475 } 476 477 val s1_RCReadData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 478 s1_RCReadData.foreach(_.foreach(_.foreach(_ := 0.U))) 479 s1_RCReadData.zip(toExu).filter(_._2.map(_.bits.params.isIntExeUnit).reduce(_ || _)).flatMap(_._1).flatten 480 .zip(regCacheReadData.take(params.getIntExuRCReadSize)).foreach{ case (s1_data, rdata) => 481 s1_data := rdata 482 } 483 s1_RCReadData.zip(toExu).filter(_._2.map(x => x.bits.params.isMemExeUnit && x.bits.params.readIntRf).reduce(_ || _)).flatMap(_._1).flatten 484 .zip(regCacheReadData.takeRight(params.getMemExuRCReadSize)).foreach{ case (s1_data, rdata) => 485 s1_data := rdata 486 } 487 488 println(s"[DataPath] s1_RCReadData.int.size: ${s1_RCReadData.zip(toExu).filter(_._2.map(_.bits.params.isIntExeUnit).reduce(_ || _)).flatMap(_._1).flatten.size}, RCRdata.int.size: ${params.getIntExuRCReadSize}") 489 println(s"[DataPath] s1_RCReadData.mem.size: ${s1_RCReadData.zip(toExu).filter(_._2.map(x => x.bits.params.isMemExeUnit && x.bits.params.readIntRf).reduce(_ || _)).flatMap(_._1).flatten.size}, RCRdata.mem.size: ${params.getMemExuRCReadSize}") 490 491 io.toWakeupQueueRCIdx := regCache.io.toWakeupQueueRCIdx 492 io.toBypassNetworkRCData := s1_RCReadData 493 regCache.io.writePorts := io.fromBypassNetwork 494 495 val s1_addrOHs = Reg(MixedVec( 496 fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType).toSeq)).toSeq 497 )) 498 val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec( 499 toExu.map(x => MixedVec(x.map(_.valid.cloneType).toSeq)).toSeq 500 )) 501 val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType).toSeq)).toSeq)) 502 val s1_immInfo = Reg(MixedVec(toExu.map(x => MixedVec(x.map(x => new ImmInfo).toSeq)).toSeq)) 503 s1_immInfo.zip(fromIQ).map { case (s1Vec, s0Vec) => 504 s1Vec.zip(s0Vec).map { case (s1, s0) => 505 s1.imm := Mux(s0.valid, s0.bits.common.imm, s1.imm) 506 s1.immType := Mux(s0.valid, s0.bits.immType, s1.immType) 507 } 508 } 509 io.og1ImmInfo.zip(s1_immInfo.flatten).map{ case(out, reg) => 510 out := reg 511 } 512 val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType).toSeq)))) 513 val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire)).toSeq))) 514 515 val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 516 val s1_fpPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 517 val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 518 val s1_v0PregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 519 val s1_vlPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 520 521 val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs)) 522 523 println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}") 524 s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 525 s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 526 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 527 iuRdata.zip(iuCfg) 528 .filter { case (_, cfg) => cfg.count(_.isInstanceOf[IntRD]) > 0 } 529 .foreach { case (sink, cfg) => sink := intRfRdata(cfg.find(_.isInstanceOf[IntRD]).get.port) } 530 } 531 } 532 533 println(s"[DataPath] s1_fpPregRData.flatten.flatten.size: ${s1_fpPregRData.flatten.flatten.size}, fpRfRdata.size: ${fpRfRdata.size}") 534 s1_fpPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 535 s1_fpPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 536 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 537 iuRdata.zip(iuCfg) 538 .filter { case (_, cfg) => cfg.count(_.isInstanceOf[FpRD]) > 0 } 539 .foreach { case (sink, cfg) => sink := fpRfRdata(cfg.find(_.isInstanceOf[FpRD]).get.port) } 540 } 541 } 542 543 println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}") 544 s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 545 s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 546 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 547 iuRdata.zip(iuCfg) 548 .filter { case (_, cfg) => cfg.count(_.isInstanceOf[VfRD]) > 0 } 549 .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.find(_.isInstanceOf[VfRD]).get.port) } 550 } 551 } 552 553 println(s"[DataPath] s1_v0PregRData.flatten.flatten.size: ${s1_v0PregRData.flatten.flatten.size}, v0RfRdata.size: ${v0RfRdata.size}") 554 s1_v0PregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 555 s1_v0PregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 556 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 557 iuRdata.zip(iuCfg) 558 .filter { case (_, cfg) => cfg.count(_.isInstanceOf[V0RD]) > 0 } 559 .foreach { case (sink, cfg) => sink := v0RfRdata(cfg.find(_.isInstanceOf[V0RD]).get.port) } 560 } 561 } 562 563 println(s"[DataPath] s1_vlPregRData.flatten.flatten.size: ${s1_vlPregRData.flatten.flatten.size}, vlRfRdata.size: ${vlRfRdata.size}") 564 s1_vlPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 565 s1_vlPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 566 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 567 iuRdata.zip(iuCfg) 568 .filter { case (_, cfg) => cfg.count(_.isInstanceOf[VlRD]) > 0 } 569 .foreach { case (sink, cfg) => sink := vlRfRdata(cfg.find(_.isInstanceOf[VlRD]).get.port) } 570 } 571 } 572 573 val og0_cancel_no_load = VecInit(og0FailedVec2.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1).toSeq) 574 val exuParamsNoLoad = fromIQ.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu) 575 val is_0latency = Wire(Vec(og0_cancel_no_load.size, Bool())) 576 is_0latency := exuParamsNoLoad.map(x => is0latency(x._1.bits.common.fuType)) 577 val og0_cancel_delay = RegNext(VecInit(og0_cancel_no_load.zip(is_0latency).map(x => x._1 && x._2))) 578 val isVfScheduler = VecInit(exuParamsNoLoad.map(x => x._2.schdType.isInstanceOf[VfScheduler].B)) 579 val og0_cancel_delay_for_mem = VecInit(og0_cancel_delay.zip(isVfScheduler).map(x => x._1 && !x._2)) 580 for (i <- fromIQ.indices) { 581 for (j <- fromIQ(i).indices) { 582 // IQ(s0) --[Ctrl]--> s1Reg ---------- begin 583 // refs 584 val s1_valid = s1_toExuValid(i)(j) 585 val s1_ready = s1_toExuReady(i)(j) 586 val s1_data = s1_toExuData(i)(j) 587 val s1_addrOH = s1_addrOHs(i)(j) 588 val s0 = fromIQ(i)(j) // s0 589 590 val srcNotBlock = Wire(Bool()) 591 srcNotBlock := s0.bits.common.dataSources.zip(intRdArbWinner(i)(j) zip fpRdArbWinner(i)(j) zip vfRdArbWinner(i)(j) zip v0RdArbWinner(i)(j) zip vlRdArbWinner(i)(j)).map { 592 case (source, ((((win_int, win_fp), win_vf), win_v0), win_vl)) => 593 !source.readReg || win_int && win_fp && win_vf && win_v0 && win_vl 594 }.fold(true.B)(_ && _) 595 val notBlock = srcNotBlock && intWbNotBlock(i)(j) && fpWbNotBlock(i)(j) && vfWbNotBlock(i)(j) && v0WbNotBlock(i)(j) && vlWbNotBlock(i)(j) 596 val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush))) 597 val s1_cancel = og1FailedVec2(i)(j) 598 val s0_cancel = Wire(Bool()) 599 val og0_cancel_delay_need = if (s0.bits.exuParams.schdType.isInstanceOf[MemScheduler]) og0_cancel_delay_for_mem else og0_cancel_delay 600 if (s0.bits.exuParams.isIQWakeUpSink) { 601 val exuOHNoLoad = s0.bits.common.l1ExuOH.get.map(x => x.asTypeOf(Vec(x.getWidth, Bool())).zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1)) 602 s0_cancel := exuOHNoLoad.zip(s0.bits.common.dataSources).map{ 603 case (exuOH, dataSource) => (VecInit(exuOH).asUInt & og0_cancel_delay_need.asUInt).orR && dataSource.readForward 604 }.reduce(_ || _) && s0.valid 605 } else s0_cancel := false.B 606 val s0_ldCancel = LoadShouldCancel(s0.bits.common.loadDependency, io.ldCancel) 607 when (s0.fire && !s1_flush && !s0_ldCancel) { 608 s1_valid := true.B 609 }.otherwise { 610 s1_valid := false.B 611 } 612 when (s0.valid) { 613 s1_data.fromIssueBundle(s0.bits) // no src data here 614 s1_addrOH := s0.bits.addrOH 615 } 616 s0.ready := notBlock && !s0_cancel 617 // IQ(s0) --[Ctrl]--> s1Reg ---------- end 618 } 619 } 620 621 private val fromIQFire = fromIQ.map(_.map(_.fire)) 622 private val toExuFire = toExu.map(_.map(_.fire)) 623 toIQs.zipWithIndex.foreach { 624 case(toIQ, iqIdx) => 625 toIQ.zipWithIndex.foreach { 626 case (toIU, iuIdx) => 627 // IU: issue unit 628 val og0resp = toIU.og0resp 629 og0FailedVec2(iqIdx)(iuIdx) := fromIQ(iqIdx)(iuIdx).valid && !fromIQ(iqIdx)(iuIdx).ready 630 og0resp.valid := og0FailedVec2(iqIdx)(iuIdx) 631 og0resp.bits.robIdx := fromIQ(iqIdx)(iuIdx).bits.common.robIdx 632 og0resp.bits.uopIdx.foreach(_ := fromIQ(iqIdx)(iuIdx).bits.common.vpu.get.vuopIdx) 633 og0resp.bits.sqIdx.foreach(_ := 0.U.asTypeOf(new SqPtr)) 634 og0resp.bits.lqIdx.foreach(_ := 0.U.asTypeOf(new LqPtr)) 635 og0resp.bits.resp := RespType.block 636 og0resp.bits.fuType := fromIQ(iqIdx)(iuIdx).bits.common.fuType 637 638 val og1resp = toIU.og1resp 639 og1FailedVec2(iqIdx)(iuIdx) := s1_toExuValid(iqIdx)(iuIdx) && !s1_toExuReady(iqIdx)(iuIdx) 640 og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) 641 og1resp.bits.robIdx := s1_toExuData(iqIdx)(iuIdx).robIdx 642 og1resp.bits.uopIdx.foreach(_ := s1_toExuData(iqIdx)(iuIdx).vpu.get.vuopIdx) 643 og1resp.bits.sqIdx.foreach(_ := 0.U.asTypeOf(new SqPtr)) 644 og1resp.bits.lqIdx.foreach(_ := 0.U.asTypeOf(new LqPtr)) 645 // respType: success -> IQ entry clear 646 // uncertain -> IQ entry no action 647 // block -> IQ entry issued set false, then re-issue 648 // hyu, lda and sta are uncertain at OG1 stage 649 // and all vector arith exu should check success in og2 stage 650 og1resp.bits.resp := Mux(og1FailedVec2(iqIdx)(iuIdx), 651 RespType.block, 652 if (toIU.issueQueueParams match { case x => x.isLdAddrIQ || x.isStAddrIQ || x.isHyAddrIQ || x.isVecLduIQ || x.isVecStuIQ || x.inVfSchd}) 653 RespType.uncertain 654 else 655 RespType.success, 656 ) 657 og1resp.bits.fuType := s1_toExuData(iqIdx)(iuIdx).fuType 658 } 659 } 660 661 io.og0Cancel := og0FailedVec2.flatten.zip(params.allExuParams).map{ case (cancel, params) => 662 if (params.isIQWakeUpSource && params.latencyCertain && params.wakeUpFuLatancySet.contains(0)) cancel else false.B 663 }.toSeq 664 io.og1Cancel := toFlattenExu.map(x => x.valid && !x.fire) 665 666 667 if (backendParams.debugEn){ 668 dontTouch(og0_cancel_no_load) 669 dontTouch(is_0latency) 670 dontTouch(og0_cancel_delay) 671 dontTouch(isVfScheduler) 672 dontTouch(og0_cancel_delay_for_mem) 673 } 674 for (i <- toExu.indices) { 675 for (j <- toExu(i).indices) { 676 // s1Reg --[Ctrl]--> exu(s1) ---------- begin 677 // refs 678 val sinkData = toExu(i)(j).bits 679 // assign 680 toExu(i)(j).valid := s1_toExuValid(i)(j) 681 s1_toExuReady(i)(j) := toExu(i)(j).ready 682 sinkData := s1_toExuData(i)(j) 683 // s1Reg --[Ctrl]--> exu(s1) ---------- end 684 685 // s1Reg --[Data]--> exu(s1) ---------- begin 686 // data source1: preg read data 687 for (k <- sinkData.src.indices) { 688 val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k) 689 val readRfMap: Seq[(Bool, UInt)] = ( 690 if (k == 3) {( 691 Seq(None) 692 :+ 693 OptionWrapper(s1_v0PregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(V0RegSrcDataSet).nonEmpty, 694 (SrcType.isV0(s1_srcType(i)(j)(k)) -> s1_v0PregRData(i)(j)(k))) 695 )} 696 else if (k == 4) {( 697 Seq(None) 698 :+ 699 OptionWrapper(s1_vlPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VlRegSrcDataSet).nonEmpty, 700 (SrcType.isVp(s1_srcType(i)(j)(k)) -> s1_vlPregRData(i)(j)(k))) 701 )} 702 else {( 703 Seq(None) 704 :+ 705 OptionWrapper(s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty, 706 (SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k))) 707 :+ 708 OptionWrapper(s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VecRegSrcDataSet).nonEmpty, 709 (SrcType.isVp(s1_srcType(i)(j)(k)) -> s1_vfPregRData(i)(j)(k))) 710 :+ 711 OptionWrapper(s1_fpPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(FpRegSrcDataSet).nonEmpty, 712 (SrcType.isFp(s1_srcType(i)(j)(k)) -> s1_fpPregRData(i)(j)(k))) 713 )} 714 ).filter(_.nonEmpty).map(_.get) 715 716 if (readRfMap.nonEmpty) 717 sinkData.src(k) := Mux1H(readRfMap) 718 } 719 if (sinkData.params.hasJmpFu) { 720 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 721 sinkData.pc.get := pcRdata(index) 722 } 723 if (sinkData.params.needTarget) { 724 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 725 sinkData.predictInfo.get.target := targetPCRdata(index) 726 } 727 } 728 } 729 730 if (env.AlwaysBasicDiff || env.EnableDifftest) { 731 val delayedCnt = 2 732 val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt) 733 difftestArchIntRegState.coreid := io.hartId 734 difftestArchIntRegState.value := intDiffRead.get._2 735 736 val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt) 737 difftestArchFpRegState.coreid := io.hartId 738 difftestArchFpRegState.value := fpDiffReadData.get 739 740 val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt) 741 difftestArchVecRegState.coreid := io.hartId 742 difftestArchVecRegState.value := vecDiffReadData.get 743 } 744 745 val int_regcache_size = 48 746 val int_regcache_tag = RegInit(VecInit(Seq.fill(int_regcache_size)(0.U(intSchdParams.pregIdxWidth.W)))) 747 val int_regcache_enqPtr = RegInit(0.U(log2Up(int_regcache_size).W)) 748 int_regcache_enqPtr := int_regcache_enqPtr + PopCount(intRfWen) 749 for (i <- intRfWen.indices) { 750 when (intRfWen(i)) { 751 int_regcache_tag(int_regcache_enqPtr + PopCount(intRfWen.take(i))) := intRfWaddr(i) 752 } 753 } 754 755 val vf_regcache_size = 48 756 val vf_regcache_tag = RegInit(VecInit(Seq.fill(vf_regcache_size)(0.U(vfSchdParams.pregIdxWidth.W)))) 757 val vf_regcache_enqPtr = RegInit(0.U(log2Up(vf_regcache_size).W)) 758 vf_regcache_enqPtr := vf_regcache_enqPtr + PopCount(vfRfWen.head) 759 for (i <- vfRfWen.indices) { 760 when (vfRfWen.head(i)) { 761 vf_regcache_tag(vf_regcache_enqPtr + PopCount(vfRfWen.head.take(i))) := vfRfWaddr(i) 762 } 763 } 764 765 v0RdPortsIter = vecExcpUseV0RdPorts.iterator 766 for (i <- toVecExcp.rdata.indices) { 767 toVecExcp.rdata(i).valid := RegNext(fromVecExcp.r(i).valid) 768 toVecExcp.rdata(i).bits := Mux( 769 RegEnable(!fromVecExcp.r(i).bits.isV0, fromVecExcp.r(i).valid), 770 vfRfRdata(vecExcpUseVecRdPorts(i)), 771 if (i % maxMergeNumPerCycle == 0) v0RfRdata(v0RdPortsIter.next()) else 0.U, 772 ) 773 } 774 775 XSPerfHistogram(s"IntRegFileRead_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 776 XSPerfHistogram(s"FpRegFileRead_hist", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 777 XSPerfHistogram(s"VfRegFileRead_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 778 XSPerfHistogram(s"IntRegFileWrite_hist", PopCount(intRFWriteReq.flatten), true.B, 0, 20, 1) 779 XSPerfHistogram(s"FpRegFileWrite_hist", PopCount(fpRFWriteReq.flatten), true.B, 0, 20, 1) 780 XSPerfHistogram(s"VfRegFileWrite_hist", PopCount(vfRFWriteReq.flatten), true.B, 0, 20, 1) 781 782 val int_regcache_part32 = (1 until 33).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 783 val int_regcache_part24 = (1 until 24).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 784 val int_regcache_part16 = (1 until 17).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 785 val int_regcache_part8 = (1 until 9).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 786 787 val int_regcache_48_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_tag.map(_ === x.bits.addr).reduce(_ || _)) 788 val int_regcache_8_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part8.map(_ === x.bits.addr).reduce(_ || _)) 789 val int_regcache_16_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part16.map(_ === x.bits.addr).reduce(_ || _)) 790 val int_regcache_24_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part24.map(_ === x.bits.addr).reduce(_ || _)) 791 val int_regcache_32_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part32.map(_ === x.bits.addr).reduce(_ || _)) 792 XSPerfAccumulate("IntRegCache48Hit", PopCount(int_regcache_48_hit_vec)) 793 XSPerfAccumulate("IntRegCache8Hit", PopCount(int_regcache_8_hit_vec)) 794 XSPerfAccumulate("IntRegCache16Hit", PopCount(int_regcache_16_hit_vec)) 795 XSPerfAccumulate("IntRegCache24Hit", PopCount(int_regcache_24_hit_vec)) 796 XSPerfAccumulate("IntRegCache32Hit", PopCount(int_regcache_32_hit_vec)) 797 XSPerfHistogram("IntRegCache48Hit_hist", PopCount(int_regcache_48_hit_vec), true.B, 0, 16, 2) 798 799 XSPerfAccumulate(s"IntRFReadBeforeArb", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 800 XSPerfAccumulate(s"IntRFReadAfterArb", PopCount(intRFReadArbiter.io.out.map(_.valid))) 801 XSPerfAccumulate(s"FpRFReadBeforeArb", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 802 XSPerfAccumulate(s"FpRFReadAfterArb", PopCount(fpRFReadArbiter.io.out.map(_.valid))) 803 XSPerfAccumulate(s"VfRFReadBeforeArb", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 804 XSPerfAccumulate(s"VfRFReadAfterArb", PopCount(vfRFReadArbiter.io.out.map(_.valid))) 805 XSPerfAccumulate(s"IntUopBeforeArb", PopCount(fromIntIQ.flatten.map(_.valid))) 806 XSPerfAccumulate(s"IntUopAfterArb", PopCount(fromIntIQ.flatten.map(_.fire))) 807 XSPerfAccumulate(s"MemUopBeforeArb", PopCount(fromMemIQ.flatten.map(_.valid))) 808 XSPerfAccumulate(s"MemUopAfterArb", PopCount(fromMemIQ.flatten.map(_.fire))) 809 XSPerfAccumulate(s"VfUopBeforeArb", PopCount(fromVfIQ.flatten.map(_.valid))) 810 XSPerfAccumulate(s"VfUopAfterArb", PopCount(fromVfIQ.flatten.map(_.fire))) 811 812 XSPerfHistogram(s"IntRFReadBeforeArb_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 813 XSPerfHistogram(s"IntRFReadAfterArb_hist", PopCount(intRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 814 XSPerfHistogram(s"FpRFReadBeforeArb_hist", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 815 XSPerfHistogram(s"FpRFReadAfterArb_hist", PopCount(fpRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 816 XSPerfHistogram(s"VfRFReadBeforeArb_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 817 XSPerfHistogram(s"VfRFReadAfterArb_hist", PopCount(vfRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 818 XSPerfHistogram(s"IntUopBeforeArb_hist", PopCount(fromIntIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 819 XSPerfHistogram(s"IntUopAfterArb_hist", PopCount(fromIntIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 820 XSPerfHistogram(s"MemUopBeforeArb_hist", PopCount(fromMemIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 821 XSPerfHistogram(s"MemUopAfterArb_hist", PopCount(fromMemIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 822 XSPerfHistogram(s"VfUopBeforeArb_hist", PopCount(fromVfIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 823 XSPerfHistogram(s"VfUopAfterArb_hist", PopCount(fromVfIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 824 825 // datasource perf counter (after arbiter) 826 fromIQ.foreach(iq => iq.foreach{exu => 827 val exuParams = exu.bits.exuParams 828 if (exuParams.isIntExeUnit) { 829 for (i <- 0 until 2) { 830 XSPerfAccumulate(s"INT_ExuId${exuParams.exuIdx}_src${i}_dataSource_forward", exu.fire && exu.bits.common.dataSources(i).readForward) 831 XSPerfAccumulate(s"INT_ExuId${exuParams.exuIdx}_src${i}_dataSource_bypass", exu.fire && exu.bits.common.dataSources(i).readBypass) 832 XSPerfAccumulate(s"INT_ExuId${exuParams.exuIdx}_src${i}_dataSource_regcache", exu.fire && exu.bits.common.dataSources(i).readRegCache) 833 XSPerfAccumulate(s"INT_ExuId${exuParams.exuIdx}_src${i}_dataSource_reg", exu.fire && exu.bits.common.dataSources(i).readReg) 834 XSPerfAccumulate(s"INT_ExuId${exuParams.exuIdx}_src${i}_dataSource_zero", exu.fire && exu.bits.common.dataSources(i).readZero) 835 } 836 } 837 if (exuParams.isMemExeUnit && exuParams.readIntRf) { 838 XSPerfAccumulate(s"MEM_ExuId${exuParams.exuIdx}_src0_dataSource_forward", exu.fire && exu.bits.common.dataSources(0).readForward) 839 XSPerfAccumulate(s"MEM_ExuId${exuParams.exuIdx}_src0_dataSource_bypass", exu.fire && exu.bits.common.dataSources(0).readBypass) 840 XSPerfAccumulate(s"MEM_ExuId${exuParams.exuIdx}_src0_dataSource_regcache", exu.fire && exu.bits.common.dataSources(0).readRegCache) 841 XSPerfAccumulate(s"MEM_ExuId${exuParams.exuIdx}_src0_dataSource_reg", exu.fire && exu.bits.common.dataSources(0).readReg) 842 XSPerfAccumulate(s"MEM_ExuId${exuParams.exuIdx}_src0_dataSource_zero", exu.fire && exu.bits.common.dataSources(0).readZero) 843 } 844 }) 845} 846 847class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 848 // params 849 private val intSchdParams = params.schdParams(IntScheduler()) 850 private val fpSchdParams = params.schdParams(FpScheduler()) 851 private val vfSchdParams = params.schdParams(VfScheduler()) 852 private val memSchdParams = params.schdParams(MemScheduler()) 853 // bundles 854 val hartId = Input(UInt(8.W)) 855 856 val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect)) 857 858 val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle()))))) 859 860 val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 861 Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 862 863 val fromFpIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 864 Flipped(MixedVec(fpSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 865 866 val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 867 Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 868 869 val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 870 871 val fromVecExcpMod = Input(new ExcpModToVprf(maxMergeNumPerCycle * 2, maxMergeNumPerCycle)) 872 873 val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle)) 874 875 val toFpIQ = MixedVec(fpSchdParams.issueBlockParams.map(_.genOGRespBundle)) 876 877 val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle)) 878 879 val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) 880 881 val toVecExcpMod = Output(new VprfToExcpMod(maxMergeNumPerCycle * 2)) 882 883 val og0Cancel = Output(ExuVec()) 884 885 val og1Cancel = Output(ExuVec()) 886 887 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 888 889 val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle 890 891 val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(fpSchdParams.genExuInputBundle) 892 893 val toVecExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle) 894 895 val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle 896 897 val og1ImmInfo: Vec[ImmInfo] = Output(Vec(params.allExuParams.size, new ImmInfo)) 898 899 val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle) 900 901 val fromFpWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genFpWriteBackBundle) 902 903 val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle) 904 905 val fromV0Wb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genV0WriteBackBundle) 906 907 val fromVlWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVlWriteBackBundle) 908 909 val fromPcTargetMem = Flipped(new PcToDataPathIO(params)) 910 911 val fromBypassNetwork: Vec[RCWritePort] = Vec(params.getIntExuRCWriteSize + params.getMemExuRCWriteSize, 912 new RCWritePort(params.intSchdParams.get.rfDataWidth, RegCacheIdxWidth, params.intSchdParams.get.pregIdxWidth, params.debugEn) 913 ) 914 915 val toBypassNetworkRCData: MixedVec[MixedVec[Vec[UInt]]] = MixedVec( 916 Seq(intSchdParams, fpSchdParams, vfSchdParams, memSchdParams).map(schd => schd.issueBlockParams.map(iq => 917 MixedVec(iq.exuBlockParams.map(exu => Output(Vec(exu.numRegSrc, UInt(exu.srcDataBitsMax.W))))) 918 )).flatten 919 ) 920 921 val toWakeupQueueRCIdx: Vec[UInt] = Vec(params.getIntExuRCWriteSize + params.getMemExuRCWriteSize, 922 Output(UInt(RegCacheIdxWidth.W)) 923 ) 924 925 val diffIntRat = if (params.basicDebugEn) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None 926 val diffFpRat = if (params.basicDebugEn) Some(Input(Vec(32, UInt(fpSchdParams.pregIdxWidth.W)))) else None 927 val diffVecRat = if (params.basicDebugEn) Some(Input(Vec(31, UInt(vfSchdParams.pregIdxWidth.W)))) else None 928 val diffV0Rat = if (params.basicDebugEn) Some(Input(Vec(1, UInt(log2Up(V0PhyRegs).W)))) else None 929 val diffVlRat = if (params.basicDebugEn) Some(Input(Vec(1, UInt(log2Up(VlPhyRegs).W)))) else None 930 val diffVl = if (params.basicDebugEn) Some(Output(UInt(VlData().dataWidth.W))) else None 931} 932