1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule} 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility._ 9import utils.SeqUtils._ 10import utils.{XSPerfAccumulate, XSPerfHistogram} 11import xiangshan._ 12import xiangshan.backend.BackendParams 13import xiangshan.backend.Bundles._ 14import xiangshan.backend.decode.ImmUnion 15import xiangshan.backend.datapath.DataConfig._ 16import xiangshan.backend.datapath.RdConfig._ 17import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler} 18import xiangshan.backend.implicitCast._ 19import xiangshan.backend.regfile._ 20 21class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { 22 override def shouldBeInlined: Boolean = false 23 24 private implicit val dpParams: BackendParams = params 25 lazy val module = new DataPathImp(this) 26 27 println(s"[DataPath] Preg Params: ") 28 println(s"[DataPath] Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ") 29 println(s"[DataPath] Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ") 30} 31 32class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams) 33 extends LazyModuleImp(wrapper) with HasXSParameter { 34 35 private val VCONFIG_PORT = params.vconfigPort 36 private val VLD_PORT = params.vldPort 37 38 val io = IO(new DataPathIO()) 39 40 private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu) 41 private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu) 42 private val (fromVfIQ , toVfIQ , toVfExu ) = (io.fromVfIQ , io.toVfIQ , io.toFpExu) 43 44 println(s"[DataPath] IntIQ(${fromIntIQ.size}), MemIQ(${fromMemIQ.size})") 45 println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})") 46 47 // just refences for convience 48 private val fromIQ: Seq[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = fromIntIQ ++ fromVfIQ ++ fromMemIQ 49 50 private val toIQs = toIntIQ ++ toVfIQ ++ toMemIQ 51 52 private val toExu: Seq[MixedVec[DecoupledIO[ExuInput]]] = toIntExu ++ toVfExu ++ toMemExu 53 54 private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten 55 56 private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten 57 58 private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams)) 59 private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams)) 60 private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams)) 61 private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams)) 62 63 private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 64 private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 65 66 // port -> win 67 private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 68 private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 69 private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 70 private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 71 72 private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR)) 73 private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR)) 74 75 private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getIntRfReadValidBundle(xx.valid)).toSeq).toSeq 76 private val intDataSources: Seq[Seq[Vec[DataSource]]] = fromIQ.map(x => x.map(xx => xx.bits.common.dataSources)) 77 78 intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 79 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 80 val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData()) 81 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 82 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 83 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && intDataSources(iqIdx)(exuIdx)(srcIdx).readReg 84 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 85 } else { 86 arbInSeq(srcIdx).valid := false.B 87 arbInSeq(srcIdx).bits.addr := 0.U 88 } 89 } 90 } 91 } 92 93 private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getVfRfReadValidBundle(xx.valid)).toSeq).toSeq 94 95 vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 96 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 97 val srcIndices: Seq[Int] = VfRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 98 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 99 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 100 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid 101 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 102 } else { 103 arbInSeq(srcIdx).valid := false.B 104 arbInSeq(srcIdx).bits.addr := 0.U 105 } 106 } 107 } 108 } 109 110 private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B)).toSeq).toSeq 111 private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.getVfWen.getOrElse(false.B)).toSeq).toSeq 112 113 intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 114 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 115 arbIn.valid := inRFWriteReq 116 } 117 } 118 119 vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 120 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 121 arbIn.valid := inRFWriteReq 122 } 123 } 124 125 private val intSchdParams = params.schdParams(IntScheduler()) 126 private val vfSchdParams = params.schdParams(VfScheduler()) 127 private val memSchdParams = params.schdParams(MemScheduler()) 128 129 private val numIntRfReadByExu = intSchdParams.numIntRfReadByExu + memSchdParams.numIntRfReadByExu 130 private val numVfRfReadByExu = vfSchdParams.numVfRfReadByExu + memSchdParams.numVfRfReadByExu 131 // Todo: limit read port 132 private val numIntR = numIntRfReadByExu 133 private val numVfR = numVfRfReadByExu 134 println(s"[DataPath] RegFile read req needed by Exu: Int(${numIntRfReadByExu}), Vf(${numVfRfReadByExu})") 135 println(s"[DataPath] RegFile read port: Int(${numIntR}), Vf(${numVfR})") 136 137 private val schdParams = params.allSchdParams 138 139 private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W))) 140 private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W))) 141 private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool())) 142 private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W))) 143 private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W))) 144 145 private val vfRfSplitNum = VLEN / XLEN 146 private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W))) 147 private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W))) 148 private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool()))) 149 private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W))) 150 private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W))) 151 152 private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] = 153 if (env.AlwaysBasicDiff || env.EnableDifftest) { 154 Some(Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))) 155 } else { None } 156 private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] = 157 if (env.AlwaysBasicDiff || env.EnableDifftest) { 158 Some(Wire(Vec(32 + 32 + 1, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(32 + 32 + 1, UInt(VLEN.W)))) 159 } else { None } 160 161 private val fpDebugReadData: Option[Vec[UInt]] = 162 if (env.AlwaysBasicDiff || env.EnableDifftest) { 163 Some(Wire(Vec(32, UInt(XLEN.W)))) 164 } else { None } 165 private val vecDebugReadData: Option[Vec[UInt]] = 166 if (env.AlwaysBasicDiff || env.EnableDifftest) { 167 Some(Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0)) 168 } else { None } 169 private val vconfigDebugReadData: Option[UInt] = 170 if (env.AlwaysBasicDiff || env.EnableDifftest) { 171 Some(Wire(UInt(64.W))) 172 } else { None } 173 174 175 fpDebugReadData.foreach(_ := vfDebugRead 176 .get._2 177 .slice(0, 32) 178 .map(_(63, 0)) 179 ) // fp only used [63, 0] 180 vecDebugReadData.foreach(_ := vfDebugRead 181 .get._2 182 .slice(32, 64) 183 .map(x => Seq(x(63, 0), x(127, 64))).flatten 184 ) 185 vconfigDebugReadData.foreach(_ := vfDebugRead 186 .get._2(64)(63, 0) 187 ) 188 189 io.debugVconfig.foreach(_ := vconfigDebugReadData.get) 190 191 IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata, 192 debugReadAddr = intDebugRead.map(_._1), 193 debugReadData = intDebugRead.map(_._2)) 194 VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata, 195 debugReadAddr = vfDebugRead.map(_._1), 196 debugReadData = vfDebugRead.map(_._2)) 197 198 intRfWaddr := io.fromIntWb.map(_.addr).toSeq 199 intRfWdata := io.fromIntWb.map(_.data).toSeq 200 intRfWen := io.fromIntWb.map(_.wen).toSeq 201 202 for (portIdx <- intRfRaddr.indices) { 203 if (intRFReadArbiter.io.out.isDefinedAt(portIdx)) 204 intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr 205 else 206 intRfRaddr(portIdx) := 0.U 207 } 208 209 vfRfWaddr := io.fromVfWb.map(_.addr).toSeq 210 vfRfWdata := io.fromVfWb.map(_.data).toSeq 211 vfRfWen.foreach(_.zip(io.fromVfWb.map(_.wen)).foreach { case (wenSink, wenSource) => wenSink := wenSource } )// Todo: support fp multi-write 212 213 for (portIdx <- vfRfRaddr.indices) { 214 if (vfRFReadArbiter.io.out.isDefinedAt(portIdx)) 215 vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr 216 else 217 vfRfRaddr(portIdx) := 0.U 218 } 219 220 vfRfRaddr(VCONFIG_PORT) := io.vconfigReadPort.addr 221 io.vconfigReadPort.data := vfRfRdata(VCONFIG_PORT) 222 // vfRfRaddr(VLD_PORT) := io.vldReadPort.addr 223 io.vldReadPort.data := DontCare 224 225 intDebugRead.foreach { case (addr, _) => 226 addr := io.debugIntRat.get 227 } 228 229 vfDebugRead.foreach { case (addr, _) => 230 addr := io.debugFpRat.get ++ io.debugVecRat.get :+ io.debugVconfigRat.get 231 } 232 println(s"[DataPath] " + 233 s"has intDebugRead: ${intDebugRead.nonEmpty}, " + 234 s"has vfDebugRead: ${vfDebugRead.nonEmpty}") 235 236 val s1_addrOHs = Reg(MixedVec( 237 fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType).toSeq)).toSeq 238 )) 239 val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec( 240 toExu.map(x => MixedVec(x.map(_.valid.cloneType).toSeq)).toSeq 241 )) 242 val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType).toSeq)).toSeq)) 243 val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType))))) // Todo 244 val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire))))) 245 246 val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType))))) 247 val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType))))) 248 249 val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs)) 250 251 println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}") 252 s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 253 s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 254 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 255 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[IntRD]) else x).flatten 256 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 257 iuRdata.zip(realIuCfg) 258 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[IntRD] } 259 .foreach { case (sink, cfg) => sink := intRfRdata(cfg.port) } 260 } 261 } 262 263 println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}") 264 s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 265 s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 266 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 267 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[VfRD]) else x).flatten 268 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 269 iuRdata.zip(realIuCfg) 270 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VfRD] } 271 .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.port) } 272 } 273 } 274 275 for (i <- fromIQ.indices) { 276 for (j <- fromIQ(i).indices) { 277 // IQ(s0) --[Ctrl]--> s1Reg ---------- begin 278 // refs 279 val s1_valid = s1_toExuValid(i)(j) 280 val s1_ready = s1_toExuReady(i)(j) 281 val s1_data = s1_toExuData(i)(j) 282 val s1_addrOH = s1_addrOHs(i)(j) 283 val s0 = fromIQ(i)(j) // s0 284 val srcNotBlock = s0.bits.common.dataSources.zip(intRdArbWinner(i)(j) zip vfRdArbWinner(i)(j)).map { case (source, win) => 285 !source.readReg || win._1 && win._2 286 }.fold(true.B)(_ && _) 287 val notBlock = srcNotBlock && intWbNotBlock(i)(j) && vfWbNotBlock(i)(j) 288 val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush))) 289 val s1_cancel = og1FailedVec2(i)(j) 290 val s1_ldCancel = LoadShouldCancel(s0.bits.common.loadDependency, io.ldCancel) 291 when (s0.fire && !s1_flush && notBlock && !s1_cancel && !s1_ldCancel) { 292 s1_valid := s0.valid 293 s1_data.fromIssueBundle(s0.bits) // no src data here 294 s1_addrOH := s0.bits.addrOH 295 }.otherwise { 296 s1_valid := false.B 297 } 298 s0.ready := (s1_ready || !s1_valid) && notBlock 299 // IQ(s0) --[Ctrl]--> s1Reg ---------- end 300 301 // IQ(s0) --[Data]--> s1Reg ---------- begin 302 // imm extract 303 when (s0.fire && !s1_flush && notBlock) { 304 if (s1_data.params.immType.nonEmpty && s1_data.src.size > 1) { 305 // rs1 is always int reg, rs2 may be imm 306 when(SrcType.isImm(s0.bits.srcType(1))) { 307 s1_data.src(1) := ImmExtractor( 308 s0.bits.common.imm, 309 s0.bits.immType, 310 s1_data.params.dataBitsMax, 311 s1_data.params.immType.map(_.litValue) 312 ) 313 } 314 } 315 if (s1_data.params.hasJmpFu) { 316 when(SrcType.isPc(s0.bits.srcType(0))) { 317 s1_data.src(0) := SignExt(s0.bits.common.pc.get, XLEN) 318 } 319 } else if (s1_data.params.hasVecFu) { 320 // Fuck off riscv vector imm!!! Why not src1??? 321 when(SrcType.isImm(s0.bits.srcType(0))) { 322 s1_data.src(0) := ImmExtractor( 323 s0.bits.common.imm, 324 s0.bits.immType, 325 s1_data.params.dataBitsMax, 326 s1_data.params.immType.map(_.litValue) 327 ) 328 } 329 } else if (s1_data.params.hasLoadFu || s1_data.params.hasHyldaFu) { 330 // dirty code for fused_lui_load 331 when(SrcType.isImm(s0.bits.srcType(0))) { 332 s1_data.src(0) := SignExt(ImmUnion.U.toImm32(s0.bits.common.imm(s0.bits.common.imm.getWidth - 1, ImmUnion.I.len)), XLEN) 333 } 334 } 335 } 336 // IQ(s0) --[Data]--> s1Reg ---------- end 337 } 338 } 339 340 private val fromIQFire = fromIQ.map(_.map(_.fire)) 341 private val toExuFire = toExu.map(_.map(_.fire)) 342 toIQs.zipWithIndex.foreach { 343 case(toIQ, iqIdx) => 344 toIQ.zipWithIndex.foreach { 345 case (toIU, iuIdx) => 346 // IU: issue unit 347 val og0resp = toIU.og0resp 348 og0FailedVec2(iqIdx)(iuIdx) := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx)) 349 og0resp.valid := og0FailedVec2(iqIdx)(iuIdx) 350 og0resp.bits.respType := RSFeedbackType.rfArbitFail 351 og0resp.bits.dataInvalidSqIdx := DontCare 352 og0resp.bits.robIdx := fromIQ(iqIdx)(iuIdx).bits.common.robIdx 353 og0resp.bits.uopIdx := fromIQ(iqIdx)(iuIdx).bits.common.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)).vuopIdx 354 og0resp.bits.rfWen := fromIQ(iqIdx)(iuIdx).bits.common.rfWen.getOrElse(false.B) 355 og0resp.bits.fuType := fromIQ(iqIdx)(iuIdx).bits.common.fuType 356 357 val og1resp = toIU.og1resp 358 og1FailedVec2(iqIdx)(iuIdx) := s1_toExuValid(iqIdx)(iuIdx) && !toExuFire(iqIdx)(iuIdx) 359 og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) 360 // respType: fuIdle ->IQ entry clear 361 // fuUncertain ->IQ entry no action 362 // fuBusy ->IQ entry issued set false, then re-issue 363 // Only hyu, lda and sta are fuUncertain at OG1 stage 364 og1resp.bits.respType := Mux( 365 !og1FailedVec2(iqIdx)(iuIdx), 366 if (toIU.issueQueueParams match { case x => x.isHyAddrIQ || x.isLdAddrIQ || x.isStAddrIQ } ) RSFeedbackType.fuUncertain else RSFeedbackType.fuIdle, 367 RSFeedbackType.fuBusy 368 ) 369 og1resp.bits.dataInvalidSqIdx := DontCare 370 og1resp.bits.robIdx := s1_toExuData(iqIdx)(iuIdx).robIdx 371 og1resp.bits.uopIdx := s1_toExuData(iqIdx)(iuIdx).vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)).vuopIdx 372 og1resp.bits.rfWen := s1_toExuData(iqIdx)(iuIdx).rfWen.getOrElse(false.B) 373 og1resp.bits.fuType := s1_toExuData(iqIdx)(iuIdx).fuType 374 } 375 } 376 377 io.og0CancelOH := VecInit(fromFlattenIQ.map(x => x.valid && !x.fire)).asUInt 378 io.og1CancelOH := VecInit(toFlattenExu.map(x => x.valid && !x.fire)).asUInt 379 380 io.cancelToBusyTable.zipWithIndex.foreach { case (cancel, i) => 381 cancel.valid := fromFlattenIQ(i).valid && !fromFlattenIQ(i).fire && { 382 if (fromFlattenIQ(i).bits.common.rfWen.isDefined) 383 fromFlattenIQ(i).bits.common.rfWen.get && fromFlattenIQ(i).bits.common.pdest =/= 0.U 384 else 385 true.B 386 } 387 cancel.bits.rfWen := fromFlattenIQ(i).bits.common.rfWen.getOrElse(false.B) 388 cancel.bits.fpWen := fromFlattenIQ(i).bits.common.fpWen.getOrElse(false.B) 389 cancel.bits.vecWen := fromFlattenIQ(i).bits.common.vecWen.getOrElse(false.B) 390 cancel.bits.pdest := fromFlattenIQ(i).bits.common.pdest 391 } 392 393 for (i <- toExu.indices) { 394 for (j <- toExu(i).indices) { 395 // s1Reg --[Ctrl]--> exu(s1) ---------- begin 396 // refs 397 val sinkData = toExu(i)(j).bits 398 // assign 399 toExu(i)(j).valid := s1_toExuValid(i)(j) 400 s1_toExuReady(i)(j) := toExu(i)(j).ready 401 sinkData := s1_toExuData(i)(j) 402 // s1Reg --[Ctrl]--> exu(s1) ---------- end 403 404 // s1Reg --[Data]--> exu(s1) ---------- begin 405 // data source1: preg read data 406 for (k <- sinkData.src.indices) { 407 val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k) 408 409 val readRfMap: Seq[(Bool, UInt)] = (Seq(None) :+ 410 (if (s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty) 411 Some(SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k)) 412 else None) :+ 413 (if (s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VfRegSrcDataSet).nonEmpty) 414 Some(SrcType.isVfp(s1_srcType(i)(j)(k))-> s1_vfPregRData(i)(j)(k)) 415 else None) 416 ).filter(_.nonEmpty).map(_.get) 417 if (readRfMap.nonEmpty) 418 sinkData.src(k) := Mux1H(readRfMap) 419 } 420 421 // data source2: extracted imm and pc saved in s1Reg 422 if (sinkData.params.immType.nonEmpty && sinkData.src.size > 1) { 423 when(SrcType.isImm(s1_srcType(i)(j)(1))) { 424 sinkData.src(1) := s1_toExuData(i)(j).src(1) 425 } 426 } 427 if (sinkData.params.hasJmpFu) { 428 when(SrcType.isPc(s1_srcType(i)(j)(0))) { 429 sinkData.src(0) := s1_toExuData(i)(j).src(0) 430 } 431 } else if (sinkData.params.hasVecFu) { 432 when(SrcType.isImm(s1_srcType(i)(j)(0))) { 433 sinkData.src(0) := s1_toExuData(i)(j).src(0) 434 } 435 } else if (sinkData.params.hasLoadFu || sinkData.params.hasHyldaFu) { 436 when(SrcType.isImm(s1_srcType(i)(j)(0))) { 437 sinkData.src(0) := s1_toExuData(i)(j).src(0) 438 } 439 } 440 // s1Reg --[Data]--> exu(s1) ---------- end 441 } 442 } 443 444 if (env.AlwaysBasicDiff || env.EnableDifftest) { 445 val delayedCnt = 2 446 val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt) 447 difftestArchIntRegState.coreid := io.hartId 448 difftestArchIntRegState.value := intDebugRead.get._2 449 450 val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt) 451 difftestArchFpRegState.coreid := io.hartId 452 difftestArchFpRegState.value := fpDebugReadData.get 453 454 val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt) 455 difftestArchVecRegState.coreid := io.hartId 456 difftestArchVecRegState.value := vecDebugReadData.get 457 } 458 459 val int_regcache_size = 48 460 val int_regcache_tag = RegInit(VecInit(Seq.fill(int_regcache_size)(0.U(intSchdParams.pregIdxWidth.W)))) 461 val int_regcache_enqPtr = RegInit(0.U(log2Up(int_regcache_size).W)) 462 int_regcache_enqPtr := int_regcache_enqPtr + PopCount(intRfWen) 463 for (i <- intRfWen.indices) { 464 when (intRfWen(i)) { 465 int_regcache_tag(int_regcache_enqPtr + PopCount(intRfWen.take(i))) := intRfWaddr(i) 466 } 467 } 468 469 val vf_regcache_size = 48 470 val vf_regcache_tag = RegInit(VecInit(Seq.fill(vf_regcache_size)(0.U(vfSchdParams.pregIdxWidth.W)))) 471 val vf_regcache_enqPtr = RegInit(0.U(log2Up(vf_regcache_size).W)) 472 vf_regcache_enqPtr := vf_regcache_enqPtr + PopCount(vfRfWen.head) 473 for (i <- vfRfWen.indices) { 474 when (vfRfWen.head(i)) { 475 vf_regcache_tag(vf_regcache_enqPtr + PopCount(vfRfWen.head.take(i))) := vfRfWaddr(i) 476 } 477 } 478 479 XSPerfHistogram(s"IntRegFileRead_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 480 XSPerfHistogram(s"VfRegFileRead_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 481 XSPerfHistogram(s"IntRegFileWrite_hist", PopCount(intRFWriteReq.flatten), true.B, 0, 20, 1) 482 XSPerfHistogram(s"VfRegFileWrite_hist", PopCount(vfRFWriteReq.flatten), true.B, 0, 20, 1) 483 484 val int_regcache_part32 = (1 until 33).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 485 val int_regcache_part24 = (1 until 24).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 486 val int_regcache_part16 = (1 until 17).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 487 val int_regcache_part8 = (1 until 9).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 488 489 val int_regcache_48_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_tag.map(_ === x.bits.addr).reduce(_ || _)) 490 val int_regcache_8_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part8.map(_ === x.bits.addr).reduce(_ || _)) 491 val int_regcache_16_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part16.map(_ === x.bits.addr).reduce(_ || _)) 492 val int_regcache_24_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part24.map(_ === x.bits.addr).reduce(_ || _)) 493 val int_regcache_32_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part32.map(_ === x.bits.addr).reduce(_ || _)) 494 XSPerfAccumulate("IntRegCache48Hit", PopCount(int_regcache_48_hit_vec)) 495 XSPerfAccumulate("IntRegCache8Hit", PopCount(int_regcache_8_hit_vec)) 496 XSPerfAccumulate("IntRegCache16Hit", PopCount(int_regcache_16_hit_vec)) 497 XSPerfAccumulate("IntRegCache24Hit", PopCount(int_regcache_24_hit_vec)) 498 XSPerfAccumulate("IntRegCache32Hit", PopCount(int_regcache_32_hit_vec)) 499 XSPerfHistogram("IntRegCache48Hit_hist", PopCount(int_regcache_48_hit_vec), true.B, 0, 16, 2) 500 501 XSPerfAccumulate(s"IntRFReadBeforeArb", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 502 XSPerfAccumulate(s"IntRFReadAfterArb", PopCount(intRFReadArbiter.io.out.map(_.valid))) 503 XSPerfAccumulate(s"VfRFReadBeforeArb", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 504 XSPerfAccumulate(s"VfRFReadAfterArb", PopCount(vfRFReadArbiter.io.out.map(_.valid))) 505 XSPerfAccumulate(s"IntUopBeforeArb", PopCount(fromIntIQ.flatten.map(_.valid))) 506 XSPerfAccumulate(s"IntUopAfterArb", PopCount(fromIntIQ.flatten.map(_.fire))) 507 XSPerfAccumulate(s"MemUopBeforeArb", PopCount(fromMemIQ.flatten.map(_.valid))) 508 XSPerfAccumulate(s"MemUopAfterArb", PopCount(fromMemIQ.flatten.map(_.fire))) 509 XSPerfAccumulate(s"VfUopBeforeArb", PopCount(fromVfIQ.flatten.map(_.valid))) 510 XSPerfAccumulate(s"VfUopAfterArb", PopCount(fromVfIQ.flatten.map(_.fire))) 511 512 XSPerfHistogram(s"IntRFReadBeforeArb_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 513 XSPerfHistogram(s"IntRFReadAfterArb_hist", PopCount(intRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 514 XSPerfHistogram(s"VfRFReadBeforeArb_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 515 XSPerfHistogram(s"VfRFReadAfterArb_hist", PopCount(vfRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 516 XSPerfHistogram(s"IntUopBeforeArb_hist", PopCount(fromIntIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 517 XSPerfHistogram(s"IntUopAfterArb_hist", PopCount(fromIntIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 518 XSPerfHistogram(s"MemUopBeforeArb_hist", PopCount(fromMemIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 519 XSPerfHistogram(s"MemUopAfterArb_hist", PopCount(fromMemIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 520 XSPerfHistogram(s"VfUopBeforeArb_hist", PopCount(fromVfIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 521 XSPerfHistogram(s"VfUopAfterArb_hist", PopCount(fromVfIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 522} 523 524class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 525 // params 526 private val intSchdParams = params.schdParams(IntScheduler()) 527 private val vfSchdParams = params.schdParams(VfScheduler()) 528 private val memSchdParams = params.schdParams(MemScheduler()) 529 // bundles 530 val hartId = Input(UInt(8.W)) 531 532 val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect)) 533 534 // Todo: check if this can be removed 535 val vconfigReadPort = new RfReadPort(XLEN, PhyRegIdxWidth) 536 537 val vldReadPort = new RfReadPort(VLEN, PhyRegIdxWidth) 538 539 val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle()))))) 540 541 val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 542 Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 543 544 val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 545 Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 546 547 val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 548 549 val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle)) 550 551 val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle)) 552 553 val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) 554 555 val og0CancelOH = Output(ExuOH(backendParams.numExu)) 556 557 val og1CancelOH = Output(ExuOH(backendParams.numExu)) 558 559 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 560 561 val cancelToBusyTable = Vec(backendParams.numExu, ValidIO(new CancelSignal)) 562 563 val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle 564 565 val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle) 566 567 val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle 568 569 val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle) 570 571 val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle) 572 573 val debugIntRat = if (params.debugEn) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None 574 val debugFpRat = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None 575 val debugVecRat = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None 576 val debugVconfigRat = if (params.debugEn) Some(Input(UInt(vfSchdParams.pregIdxWidth.W))) else None 577 val debugVconfig = if (params.debugEn) Some(Output(UInt(XLEN.W))) else None 578} 579