xref: /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala (revision 60f0c5ae701c71b6347e32d54543e5e7858f2038)
1package xiangshan.backend.datapath
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule}
7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
8import utility._
9import utils.SeqUtils._
10import utils.{XSPerfAccumulate, XSPerfHistogram}
11import xiangshan._
12import xiangshan.backend.BackendParams
13import xiangshan.backend.Bundles._
14import xiangshan.backend.decode.ImmUnion
15import xiangshan.backend.datapath.DataConfig._
16import xiangshan.backend.datapath.RdConfig._
17import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler, FpScheduler}
18import xiangshan.backend.issue.EntryBundles._
19import xiangshan.backend.regfile._
20import xiangshan.backend.PcToDataPathIO
21import xiangshan.backend.fu.FuType.is0latency
22
23class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule {
24  override def shouldBeInlined: Boolean = false
25
26  private implicit val dpParams: BackendParams = params
27  lazy val module = new DataPathImp(this)
28
29  println(s"[DataPath] Preg Params: ")
30  println(s"[DataPath]   Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ")
31  println(s"[DataPath]   Fp R(${params.getRfReadSize(FpData())}), W(${params.getRfWriteSize(FpData())}) ")
32  println(s"[DataPath]   Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ")
33}
34
35class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams)
36  extends LazyModuleImp(wrapper) with HasXSParameter {
37
38  val io = IO(new DataPathIO())
39
40  private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu)
41  private val (fromFpIQ, toFpIQ, toFpExu) = (io.fromFpIQ, io.toFpIQ, io.toFpExu)
42  private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu)
43  private val (fromVfIQ , toVfIQ , toVfExu ) = (io.fromVfIQ , io.toVfIQ , io.toVecExu)
44
45  println(s"[DataPath] IntIQ(${fromIntIQ.size}), MemIQ(${fromFpIQ.size}), MemIQ(${fromMemIQ.size})")
46  println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), FpExu(${fromFpIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})")
47
48  // just refences for convience
49  private val fromIQ: Seq[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = (fromIntIQ ++ fromFpIQ ++ fromVfIQ ++ fromMemIQ).toSeq
50
51  private val toIQs = toIntIQ ++ toFpIQ ++ toVfIQ ++ toMemIQ
52
53  private val toExu: Seq[MixedVec[DecoupledIO[ExuInput]]] = (toIntExu ++ toFpExu ++ toVfExu ++ toMemExu).toSeq
54
55  private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten
56
57  private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten
58
59  private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams))
60  private val fpWbBusyArbiter = Module(new FpRFWBCollideChecker(backendParams))
61  private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams))
62  private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams))
63  private val fpRFReadArbiter = Module(new FpRFReadArbiter(backendParams))
64  private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams))
65
66  private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq))
67  private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq))
68
69  // port -> win
70  private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq
71  private val fpRdArbWinner: Seq2[MixedVec[Bool]] = fpRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq
72  private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq
73  private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq
74  private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq
75
76  private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR))
77  private val fpRdNotBlock: Seq2[Bool] = fpRdArbWinner.map(_.map(_.asUInt.andR))
78  private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR))
79
80  private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getIntRfReadValidBundle(xx.valid)).toSeq).toSeq
81  private val fpRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getFpRfReadValidBundle(xx.valid)).toSeq).toSeq
82  private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getVfRfReadValidBundle(xx.valid)).toSeq).toSeq
83  private val allDataSources: Seq[Seq[Vec[DataSource]]] = fromIQ.map(x => x.map(xx => xx.bits.common.dataSources).toSeq)
84  private val allNumRegSrcs: Seq[Seq[Int]] = fromIQ.map(x => x.map(xx => xx.bits.exuParams.numRegSrc).toSeq)
85
86  intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) =>
87    arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) =>
88      val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData())
89      for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) {
90        if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) {
91          arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg
92          arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr
93//          if (allNumRegSrcs(iqIdx)(exuIdx) == 2) {
94//            val src0Req = inRFReadReqSeq(0).valid && allDataSources(iqIdx)(exuIdx)(0).readReg
95//            val src1Req = inRFReadReqSeq(1).valid && allDataSources(iqIdx)(exuIdx)(1).readReg
96//            if (srcIdx == 0) {
97//              arbInSeq(srcIdx).valid := src0Req || src1Req
98//              arbInSeq(srcIdx).bits.addr := Mux(src1Req && !src0Req, inRFReadReqSeq(1).bits.addr,inRFReadReqSeq(0).bits.addr)
99//            } else {
100//              arbInSeq(srcIdx).valid := src0Req && src1Req
101//              arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr
102//            }
103//          } else {
104//            arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg
105//            arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr
106//          }
107        } else {
108          arbInSeq(srcIdx).valid := false.B
109          arbInSeq(srcIdx).bits.addr := 0.U
110        }
111      }
112    }
113  }
114  fpRFReadArbiter.io.in.zip(fpRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) =>
115    arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) =>
116      val srcIndices: Seq[Int] = FpRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted
117      for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) {
118        if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) {
119          arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg
120          arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr
121        } else {
122          arbInSeq(srcIdx).valid := false.B
123          arbInSeq(srcIdx).bits.addr := 0.U
124        }
125      }
126    }
127  }
128
129  vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) =>
130    arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) =>
131      val srcIndices: Seq[Int] = VfRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted
132      for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) {
133        if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) {
134          arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg
135          arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr
136        } else {
137          arbInSeq(srcIdx).valid := false.B
138          arbInSeq(srcIdx).bits.addr := 0.U
139        }
140      }
141    }
142  }
143
144  private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B)).toSeq).toSeq
145  private val fpRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.getFpWen.getOrElse(false.B)).toSeq).toSeq
146  private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.getVfWen.getOrElse(false.B)).toSeq).toSeq
147
148  intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) =>
149    arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) =>
150      arbIn.valid := inRFWriteReq
151    }
152  }
153
154  fpWbBusyArbiter.io.in.zip(fpRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) =>
155    arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) =>
156      arbIn.valid := inRFWriteReq
157    }
158  }
159
160  vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) =>
161    arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) =>
162      arbIn.valid := inRFWriteReq
163    }
164  }
165
166  private val intSchdParams = params.schdParams(IntScheduler())
167  private val fpSchdParams = params.schdParams(FpScheduler())
168  private val vfSchdParams = params.schdParams(VfScheduler())
169  private val memSchdParams = params.schdParams(MemScheduler())
170
171  private val numIntRfReadByExu = intSchdParams.numIntRfReadByExu + memSchdParams.numIntRfReadByExu
172  private val numFpRfReadByExu = fpSchdParams.numFpRfReadByExu + memSchdParams.numFpRfReadByExu
173  private val numVfRfReadByExu = vfSchdParams.numVfRfReadByExu + memSchdParams.numVfRfReadByExu
174  // Todo: limit read port
175  private val numIntR = numIntRfReadByExu
176  private val numFpR = numFpRfReadByExu
177  private val numVfR = numVfRfReadByExu
178  println(s"[DataPath] RegFile read req needed by Exu: Int(${numIntRfReadByExu}), Fp(${numFpRfReadByExu}), Vf(${numVfRfReadByExu})")
179  println(s"[DataPath] RegFile read port: Int(${numIntR}), Fp(${numFpR}), Vf(${numVfR})")
180
181  private val schdParams = params.allSchdParams
182
183  private val pcReadValid = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathValid))
184  private val pcReadFtqPtr = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqPtr))
185  private val pcReadFtqOffset = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqOffset))
186  private val targetPCRdata = io.fromPcTargetMem.toDataPathTargetPC
187  private val pcRdata = io.fromPcTargetMem.toDataPathPC
188  private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W)))
189  private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W)))
190  private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool()))
191  private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W)))
192  private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W)))
193
194  private val fpRfRaddr = Wire(Vec(params.numPregRd(FpData()), UInt(fpSchdParams.pregIdxWidth.W)))
195  private val fpRfRdata = Wire(Vec(params.numPregRd(FpData()), UInt(fpSchdParams.rfDataWidth.W)))
196  private val fpRfWen = Wire(Vec(io.fromFpWb.length, Bool()))
197  private val fpRfWaddr = Wire(Vec(io.fromFpWb.length, UInt(fpSchdParams.pregIdxWidth.W)))
198  private val fpRfWdata = Wire(Vec(io.fromFpWb.length, UInt(fpSchdParams.rfDataWidth.W)))
199
200  private val vfRfSplitNum = VLEN / XLEN
201  private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W)))
202  private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W)))
203  private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool())))
204  private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W)))
205  private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W)))
206
207  val pcReadFtqPtrFormIQ = fromIntIQ.flatten.filter(x => x.bits.exuParams.needPc)
208  assert(pcReadFtqPtrFormIQ.size == pcReadFtqPtr.size, s"pcReadFtqPtrFormIQ.size ${pcReadFtqPtrFormIQ.size} not equal pcReadFtqPtr.size ${pcReadFtqPtr.size}")
209  pcReadValid.zip(pcReadFtqPtrFormIQ.map(_.valid)).map(x => x._1 := x._2)
210  pcReadFtqPtr.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqIdx.get)).map(x => x._1 := x._2)
211  pcReadFtqOffset.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqOffset.get)).map(x => x._1 := x._2)
212  io.fromPcTargetMem.fromDataPathValid := pcReadValid
213  io.fromPcTargetMem.fromDataPathFtqPtr := pcReadFtqPtr
214  io.fromPcTargetMem.fromDataPathFtqOffset := pcReadFtqOffset
215
216  private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] =
217    if (env.AlwaysBasicDiff || env.EnableDifftest) {
218      Some(Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W))))
219    } else { None }
220  private val fpDebugRead: Option[(Vec[UInt], Vec[UInt])] =
221    if (env.AlwaysBasicDiff || env.EnableDifftest) {
222      Some(Wire(Vec(32, UInt(fpSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W))))
223    } else { None }
224  private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] =
225    if (env.AlwaysBasicDiff || env.EnableDifftest) {
226      Some(Wire(Vec(32 + 32 + 1, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(32 + 32 + 1, UInt(VLEN.W))))
227    } else { None }
228
229  private val fpDebugReadData: Option[Vec[UInt]] =
230    if (env.AlwaysBasicDiff || env.EnableDifftest) {
231      Some(Wire(Vec(32, UInt(XLEN.W))))
232    } else { None }
233  private val vecDebugReadData: Option[Vec[UInt]] =
234    if (env.AlwaysBasicDiff || env.EnableDifftest) {
235      Some(Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0))
236    } else { None }
237  private val vconfigDebugReadData: Option[UInt] =
238    if (env.AlwaysBasicDiff || env.EnableDifftest) {
239      Some(Wire(UInt(64.W)))
240    } else { None }
241
242
243  fpDebugReadData.foreach(_ := vfDebugRead
244    .get._2
245    .slice(0, 32)
246    .map(_(63, 0))
247  ) // fp only used [63, 0]
248  vecDebugReadData.foreach(_ := vfDebugRead
249    .get._2
250    .slice(32, 64)
251    .map(x => Seq(x(63, 0), x(127, 64))).flatten
252  )
253  vconfigDebugReadData.foreach(_ := vfDebugRead
254    .get._2(64)(63, 0)
255  )
256
257  io.debugVconfig.foreach(_ := vconfigDebugReadData.get)
258
259  IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata,
260    bankNum = 4,
261    debugReadAddr = intDebugRead.map(_._1),
262    debugReadData = intDebugRead.map(_._2))
263  FpRegFile("FpRegFile", fpSchdParams.numPregs, fpRfRaddr, fpRfRdata, fpRfWen, fpRfWaddr, fpRfWdata,
264    bankNum = 1,
265    debugReadAddr = fpDebugRead.map(_._1),
266    debugReadData = fpDebugRead.map(_._2))
267  VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata,
268    debugReadAddr = vfDebugRead.map(_._1),
269    debugReadData = vfDebugRead.map(_._2))
270
271  intRfWaddr := io.fromIntWb.map(_.addr).toSeq
272  intRfWdata := io.fromIntWb.map(_.data).toSeq
273  intRfWen := io.fromIntWb.map(_.wen).toSeq
274
275  for (portIdx <- intRfRaddr.indices) {
276    if (intRFReadArbiter.io.out.isDefinedAt(portIdx))
277      intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr
278    else
279      intRfRaddr(portIdx) := 0.U
280  }
281
282  fpRfWaddr := io.fromFpWb.map(_.addr).toSeq
283  fpRfWdata := io.fromFpWb.map(_.data).toSeq
284  fpRfWen := io.fromFpWb.map(_.wen).toSeq
285
286  for (portIdx <- fpRfRaddr.indices) {
287    if (fpRFReadArbiter.io.out.isDefinedAt(portIdx))
288      fpRfRaddr(portIdx) := fpRFReadArbiter.io.out(portIdx).bits.addr
289    else
290      fpRfRaddr(portIdx) := 0.U
291  }
292
293  vfRfWaddr := io.fromVfWb.map(x => RegEnable(x.addr, x.wen)).toSeq
294  vfRfWdata := io.fromVfWb.map(x => RegEnable(x.data, x.wen)).toSeq
295  vfRfWen.foreach(_.zip(io.fromVfWb.map(x => RegNext(x.wen))).foreach { case (wenSink, wenSource) => wenSink := wenSource } )// Todo: support fp multi-write
296
297  for (portIdx <- vfRfRaddr.indices) {
298    if (vfRFReadArbiter.io.out.isDefinedAt(portIdx))
299      vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr
300    else
301      vfRfRaddr(portIdx) := 0.U
302  }
303
304
305  intDebugRead.foreach { case (addr, _) =>
306    addr := io.debugIntRat.get
307  }
308
309  vfDebugRead.foreach { case (addr, _) =>
310    addr := io.debugFpRat.get ++ io.debugVecRat.get :+ io.debugVconfigRat.get
311  }
312  println(s"[DataPath] " +
313    s"has intDebugRead: ${intDebugRead.nonEmpty}, " +
314    s"has vfDebugRead: ${vfDebugRead.nonEmpty}")
315
316  val s1_addrOHs = Reg(MixedVec(
317    fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType).toSeq)).toSeq
318  ))
319  val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec(
320    toExu.map(x => MixedVec(x.map(_.valid.cloneType).toSeq)).toSeq
321  ))
322  val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType).toSeq)).toSeq))
323  val s1_immInfo = Reg(MixedVec(toExu.map(x => MixedVec(x.map(x => new ImmInfo).toSeq)).toSeq))
324  s1_immInfo.zip(fromIQ).map { case (s1Vec, s0Vec) =>
325    s1Vec.zip(s0Vec).map { case (s1, s0) =>
326      s1.imm := Mux(s0.valid, s0.bits.common.imm, s1.imm)
327      s1.immType := Mux(s0.valid, s0.bits.immType, s1.immType)
328    }
329  }
330  io.og1ImmInfo.zip(s1_immInfo.flatten).map{ case(out, reg) =>
331    out := reg
332  }
333  val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType).toSeq))))
334  val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire)).toSeq)))
335
336  val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq))))
337  val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq))))
338
339  val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs))
340
341  println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}")
342  s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U)))
343  s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) =>
344      iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) =>
345        val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[IntRD]) else x).flatten
346        assert(iuRdata.size == realIuCfg.size, s"iuRdata.size(${iuRdata.size}) != realIuCfg.size(${realIuCfg.size})")
347        iuRdata.zip(realIuCfg)
348          .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[IntRD] }
349          .foreach { case (sink, cfg) => sink := intRfRdata(cfg.port) }
350      }
351  }
352
353  println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}")
354  s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U)))
355  s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) =>
356      iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) =>
357        val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[VfRD]) else x).flatten
358        assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size")
359        iuRdata.zip(realIuCfg)
360          .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VfRD] }
361          .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.port) }
362      }
363  }
364
365  val og0_cancel_no_load = VecInit(og0FailedVec2.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1).toSeq)
366  val exuParamsNoLoad = fromIQ.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu)
367  val is_0latency = Wire(Vec(og0_cancel_no_load.size, Bool()))
368  is_0latency := exuParamsNoLoad.map(x => is0latency(x._1.bits.common.fuType))
369  val og0_cancel_delay = RegNext(VecInit(og0_cancel_no_load.zip(is_0latency).map(x => x._1 && x._2)))
370  val isVfScheduler = VecInit(exuParamsNoLoad.map(x => x._2.schdType.isInstanceOf[VfScheduler].B))
371  val og0_cancel_delay_for_mem = VecInit(og0_cancel_delay.zip(isVfScheduler).map(x => x._1 && !x._2))
372  for (i <- fromIQ.indices) {
373    for (j <- fromIQ(i).indices) {
374      // IQ(s0) --[Ctrl]--> s1Reg ---------- begin
375      // refs
376      val s1_valid = s1_toExuValid(i)(j)
377      val s1_ready = s1_toExuReady(i)(j)
378      val s1_data = s1_toExuData(i)(j)
379      val s1_addrOH = s1_addrOHs(i)(j)
380      val s0 = fromIQ(i)(j) // s0
381
382      val srcNotBlock = Wire(Bool())
383      srcNotBlock := s0.bits.common.dataSources.zip(intRdArbWinner(i)(j) zip vfRdArbWinner(i)(j)).map { case (source, win) =>
384        !source.readReg || win._1 && win._2
385      }.fold(true.B)(_ && _)
386//      if (fromIQ(i)(j).bits.exuParams.schdType.isInstanceOf[IntScheduler] && (fromIQ(i)(j).bits.exuParams.numRegSrc == 2)) {
387//        val src0VfBlock = s0.bits.common.dataSources(0).readReg && !vfRdArbWinner(i)(j)(0)
388//        val src1VfBlock = s0.bits.common.dataSources(1).readReg && !vfRdArbWinner(i)(j)(1)
389//        val src1IntBlock = s0.bits.common.dataSources(0).readReg && s0.bits.common.dataSources(1).readReg && !intRdArbWinner(i)(j)(1)
390//        val src0IntBlock = (s0.bits.common.dataSources(0).readReg || s0.bits.common.dataSources(1).readReg) && !intRdArbWinner(i)(j)(0)
391//        srcNotBlock := !src0VfBlock && !src1VfBlock && !src1IntBlock && !src0IntBlock
392//      }
393      val notBlock = srcNotBlock && intWbNotBlock(i)(j) && vfWbNotBlock(i)(j)
394      val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush)))
395      val s1_cancel = og1FailedVec2(i)(j)
396      val s0_cancel = Wire(Bool())
397      val og0_cancel_delay_need = if (s0.bits.exuParams.schdType.isInstanceOf[MemScheduler]) og0_cancel_delay_for_mem else og0_cancel_delay
398      if (s0.bits.exuParams.isIQWakeUpSink) {
399        val exuOHNoLoad = s0.bits.common.l1ExuOH.get.map(x => x.asTypeOf(Vec(x.getWidth, Bool())).zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1))
400        s0_cancel := exuOHNoLoad.zip(s0.bits.common.dataSources).map{
401          case (exuOH, dataSource) => (VecInit(exuOH).asUInt & og0_cancel_delay_need.asUInt).orR && dataSource.readForward
402        }.reduce(_ || _) && s0.valid
403      } else s0_cancel := false.B
404      val s0_ldCancel = LoadShouldCancel(s0.bits.common.loadDependency, io.ldCancel)
405      when (s0.fire && !s1_flush && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel) {
406        s1_valid := s0.valid
407        s1_data.fromIssueBundle(s0.bits) // no src data here
408//        if (fromIQ(i)(j).bits.exuParams.schdType.isInstanceOf[IntScheduler] && (fromIQ(i)(j).bits.exuParams.numRegSrc == 2)) {
409//          s1_data.dataSources(1).value := Mux(!s0.bits.common.dataSources(0).readReg && s0.bits.common.dataSources(1).readReg, DataSource.anotherReg, s0.bits.common.dataSources(1).value)
410//        }
411        s1_addrOH := s0.bits.addrOH
412      }.otherwise {
413        s1_valid := false.B
414      }
415      s0.ready := (s1_ready || !s1_valid) && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel
416      // IQ(s0) --[Ctrl]--> s1Reg ---------- end
417    }
418  }
419
420  private val fromIQFire = fromIQ.map(_.map(_.fire))
421  private val toExuFire = toExu.map(_.map(_.fire))
422  toIQs.zipWithIndex.foreach {
423    case(toIQ, iqIdx) =>
424      toIQ.zipWithIndex.foreach {
425        case (toIU, iuIdx) =>
426          // IU: issue unit
427          val og0resp = toIU.og0resp
428          og0FailedVec2(iqIdx)(iuIdx) := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx))
429          og0resp.valid                 := og0FailedVec2(iqIdx)(iuIdx)
430          og0resp.bits.robIdx           := fromIQ(iqIdx)(iuIdx).bits.common.robIdx
431          og0resp.bits.uopIdx.foreach(_ := fromIQ(iqIdx)(iuIdx).bits.common.vpu.get.vuopIdx)
432          og0resp.bits.resp             := RespType.block
433          og0resp.bits.fuType           := fromIQ(iqIdx)(iuIdx).bits.common.fuType
434
435          val og1resp = toIU.og1resp
436          og1FailedVec2(iqIdx)(iuIdx)   := s1_toExuValid(iqIdx)(iuIdx) && !toExuFire(iqIdx)(iuIdx)
437          og1resp.valid                 := s1_toExuValid(iqIdx)(iuIdx)
438          og1resp.bits.robIdx           := s1_toExuData(iqIdx)(iuIdx).robIdx
439          og1resp.bits.uopIdx.foreach(_ := s1_toExuData(iqIdx)(iuIdx).vpu.get.vuopIdx)
440          // respType:  fuIdle      ->IQ entry clear
441          //            fuUncertain ->IQ entry no action
442          //            fuBusy      ->IQ entry issued set false, then re-issue
443          // Only hyu, lda and sta are fuUncertain at OG1 stage
444          og1resp.bits.resp             := Mux(!og1FailedVec2(iqIdx)(iuIdx),
445            if (toIU.issueQueueParams match { case x => x.isMemAddrIQ && !x.isVecMemIQ || x.inVfSchd}) RespType.uncertain else RespType.success,
446            RespType.block
447          )
448          og1resp.bits.fuType           := s1_toExuData(iqIdx)(iuIdx).fuType
449      }
450  }
451
452  io.og0CancelOH := VecInit(fromFlattenIQ.map(x => x.valid && !x.fire)).asUInt
453  io.og1CancelOH := VecInit(toFlattenExu.map(x => x.valid && !x.fire)).asUInt
454
455  io.cancelToBusyTable.zipWithIndex.foreach { case (cancel, i) =>
456    cancel.valid := fromFlattenIQ(i).valid && !fromFlattenIQ(i).fire
457    cancel.bits.rfWen := fromFlattenIQ(i).bits.common.rfWen.getOrElse(false.B)
458    cancel.bits.fpWen := fromFlattenIQ(i).bits.common.fpWen.getOrElse(false.B)
459    cancel.bits.vecWen := fromFlattenIQ(i).bits.common.vecWen.getOrElse(false.B)
460    cancel.bits.pdest := fromFlattenIQ(i).bits.common.pdest
461  }
462
463  if (backendParams.debugEn){
464    dontTouch(og0_cancel_no_load)
465    dontTouch(is_0latency)
466    dontTouch(og0_cancel_delay)
467    dontTouch(isVfScheduler)
468    dontTouch(og0_cancel_delay_for_mem)
469  }
470  for (i <- toExu.indices) {
471    for (j <- toExu(i).indices) {
472      // s1Reg --[Ctrl]--> exu(s1) ---------- begin
473      // refs
474      val sinkData = toExu(i)(j).bits
475      // assign
476      toExu(i)(j).valid := s1_toExuValid(i)(j)
477      s1_toExuReady(i)(j) := toExu(i)(j).ready
478      sinkData := s1_toExuData(i)(j)
479      // s1Reg --[Ctrl]--> exu(s1) ---------- end
480
481      // s1Reg --[Data]--> exu(s1) ---------- begin
482      // data source1: preg read data
483      for (k <- sinkData.src.indices) {
484        val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k)
485
486        val readRfMap: Seq[(Bool, UInt)] = (Seq(None) :+
487          (if (s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty)
488            Some(SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k))
489          else None) :+
490          (if (s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VfRegSrcDataSet).nonEmpty)
491            Some(SrcType.isVfp(s1_srcType(i)(j)(k))-> s1_vfPregRData(i)(j)(k))
492          else None)
493        ).filter(_.nonEmpty).map(_.get)
494        if (readRfMap.nonEmpty)
495          sinkData.src(k) := Mux1H(readRfMap)
496      }
497      if (sinkData.params.hasJmpFu) {
498        val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params)
499        sinkData.pc.get := pcRdata(index)
500      }
501      if (sinkData.params.needTarget) {
502        val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params)
503        sinkData.predictInfo.get.target := targetPCRdata(index)
504      }
505    }
506  }
507
508  if (env.AlwaysBasicDiff || env.EnableDifftest) {
509    val delayedCnt = 2
510    val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt)
511    difftestArchIntRegState.coreid := io.hartId
512    difftestArchIntRegState.value := intDebugRead.get._2
513
514    val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt)
515    difftestArchFpRegState.coreid := io.hartId
516    difftestArchFpRegState.value := fpDebugReadData.get
517
518    val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt)
519    difftestArchVecRegState.coreid := io.hartId
520    difftestArchVecRegState.value := vecDebugReadData.get
521  }
522
523  val int_regcache_size = 48
524  val int_regcache_tag = RegInit(VecInit(Seq.fill(int_regcache_size)(0.U(intSchdParams.pregIdxWidth.W))))
525  val int_regcache_enqPtr = RegInit(0.U(log2Up(int_regcache_size).W))
526  int_regcache_enqPtr := int_regcache_enqPtr + PopCount(intRfWen)
527  for (i <- intRfWen.indices) {
528    when (intRfWen(i)) {
529      int_regcache_tag(int_regcache_enqPtr + PopCount(intRfWen.take(i))) := intRfWaddr(i)
530    }
531  }
532
533  val vf_regcache_size = 48
534  val vf_regcache_tag = RegInit(VecInit(Seq.fill(vf_regcache_size)(0.U(vfSchdParams.pregIdxWidth.W))))
535  val vf_regcache_enqPtr = RegInit(0.U(log2Up(vf_regcache_size).W))
536  vf_regcache_enqPtr := vf_regcache_enqPtr + PopCount(vfRfWen.head)
537  for (i <- vfRfWen.indices) {
538    when (vfRfWen.head(i)) {
539      vf_regcache_tag(vf_regcache_enqPtr + PopCount(vfRfWen.head.take(i))) := vfRfWaddr(i)
540    }
541  }
542
543  XSPerfHistogram(s"IntRegFileRead_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1)
544  XSPerfHistogram(s"FpRegFileRead_hist", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1)
545  XSPerfHistogram(s"VfRegFileRead_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1)
546  XSPerfHistogram(s"IntRegFileWrite_hist", PopCount(intRFWriteReq.flatten), true.B, 0, 20, 1)
547  XSPerfHistogram(s"FpRegFileWrite_hist", PopCount(fpRFWriteReq.flatten), true.B, 0, 20, 1)
548  XSPerfHistogram(s"VfRegFileWrite_hist", PopCount(vfRFWriteReq.flatten), true.B, 0, 20, 1)
549
550  val int_regcache_part32 = (1 until 33).map(i => int_regcache_tag(int_regcache_enqPtr - i.U))
551  val int_regcache_part24 = (1 until 24).map(i => int_regcache_tag(int_regcache_enqPtr - i.U))
552  val int_regcache_part16 = (1 until 17).map(i => int_regcache_tag(int_regcache_enqPtr - i.U))
553  val int_regcache_part8 = (1 until 9).map(i => int_regcache_tag(int_regcache_enqPtr - i.U))
554
555  val int_regcache_48_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_tag.map(_ === x.bits.addr).reduce(_ || _))
556  val int_regcache_8_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part8.map(_ === x.bits.addr).reduce(_ || _))
557  val int_regcache_16_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part16.map(_ === x.bits.addr).reduce(_ || _))
558  val int_regcache_24_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part24.map(_ === x.bits.addr).reduce(_ || _))
559  val int_regcache_32_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part32.map(_ === x.bits.addr).reduce(_ || _))
560  XSPerfAccumulate("IntRegCache48Hit", PopCount(int_regcache_48_hit_vec))
561  XSPerfAccumulate("IntRegCache8Hit", PopCount(int_regcache_8_hit_vec))
562  XSPerfAccumulate("IntRegCache16Hit", PopCount(int_regcache_16_hit_vec))
563  XSPerfAccumulate("IntRegCache24Hit", PopCount(int_regcache_24_hit_vec))
564  XSPerfAccumulate("IntRegCache32Hit", PopCount(int_regcache_32_hit_vec))
565  XSPerfHistogram("IntRegCache48Hit_hist", PopCount(int_regcache_48_hit_vec), true.B, 0, 16, 2)
566
567  XSPerfAccumulate(s"IntRFReadBeforeArb", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)))
568  XSPerfAccumulate(s"IntRFReadAfterArb", PopCount(intRFReadArbiter.io.out.map(_.valid)))
569  XSPerfAccumulate(s"FpRFReadBeforeArb", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid)))
570  XSPerfAccumulate(s"FpRFReadAfterArb", PopCount(fpRFReadArbiter.io.out.map(_.valid)))
571  XSPerfAccumulate(s"VfRFReadBeforeArb", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)))
572  XSPerfAccumulate(s"VfRFReadAfterArb", PopCount(vfRFReadArbiter.io.out.map(_.valid)))
573  XSPerfAccumulate(s"IntUopBeforeArb", PopCount(fromIntIQ.flatten.map(_.valid)))
574  XSPerfAccumulate(s"IntUopAfterArb", PopCount(fromIntIQ.flatten.map(_.fire)))
575  XSPerfAccumulate(s"MemUopBeforeArb", PopCount(fromMemIQ.flatten.map(_.valid)))
576  XSPerfAccumulate(s"MemUopAfterArb", PopCount(fromMemIQ.flatten.map(_.fire)))
577  XSPerfAccumulate(s"VfUopBeforeArb", PopCount(fromVfIQ.flatten.map(_.valid)))
578  XSPerfAccumulate(s"VfUopAfterArb", PopCount(fromVfIQ.flatten.map(_.fire)))
579
580  XSPerfHistogram(s"IntRFReadBeforeArb_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2)
581  XSPerfHistogram(s"IntRFReadAfterArb_hist", PopCount(intRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2)
582  XSPerfHistogram(s"FpRFReadBeforeArb_hist", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2)
583  XSPerfHistogram(s"FpRFReadAfterArb_hist", PopCount(fpRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2)
584  XSPerfHistogram(s"VfRFReadBeforeArb_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2)
585  XSPerfHistogram(s"VfRFReadAfterArb_hist", PopCount(vfRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2)
586  XSPerfHistogram(s"IntUopBeforeArb_hist", PopCount(fromIntIQ.flatten.map(_.valid)), true.B, 0, 8, 2)
587  XSPerfHistogram(s"IntUopAfterArb_hist", PopCount(fromIntIQ.flatten.map(_.fire)), true.B, 0, 8, 2)
588  XSPerfHistogram(s"MemUopBeforeArb_hist", PopCount(fromMemIQ.flatten.map(_.valid)), true.B, 0, 8, 2)
589  XSPerfHistogram(s"MemUopAfterArb_hist", PopCount(fromMemIQ.flatten.map(_.fire)), true.B, 0, 8, 2)
590  XSPerfHistogram(s"VfUopBeforeArb_hist", PopCount(fromVfIQ.flatten.map(_.valid)), true.B, 0, 8, 2)
591  XSPerfHistogram(s"VfUopAfterArb_hist", PopCount(fromVfIQ.flatten.map(_.fire)), true.B, 0, 8, 2)
592}
593
594class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle {
595  // params
596  private val intSchdParams = params.schdParams(IntScheduler())
597  private val fpSchdParams = params.schdParams(FpScheduler())
598  private val vfSchdParams = params.schdParams(VfScheduler())
599  private val memSchdParams = params.schdParams(MemScheduler())
600  // bundles
601  val hartId = Input(UInt(8.W))
602
603  val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect))
604
605  val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle())))))
606
607  val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] =
608    Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle)))
609
610  val fromFpIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] =
611    Flipped(MixedVec(fpSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle)))
612
613  val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] =
614    Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle)))
615
616  val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle)))
617
618  val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle))
619
620  val toFpIQ = MixedVec(fpSchdParams.issueBlockParams.map(_.genOGRespBundle))
621
622  val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle))
623
624  val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle))
625
626  val og0CancelOH = Output(ExuOH(backendParams.numExu))
627
628  val og1CancelOH = Output(ExuOH(backendParams.numExu))
629
630  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
631
632  val cancelToBusyTable = Vec(backendParams.numExu, ValidIO(new CancelSignal))
633
634  val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle
635
636  val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(fpSchdParams.genExuInputBundle)
637
638  val toVecExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle)
639
640  val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle
641
642  val og1ImmInfo: Vec[ImmInfo] = Output(Vec(params.allExuParams.size, new ImmInfo))
643
644  val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle)
645
646  val fromFpWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genFpWriteBackBundle)
647
648  val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle)
649
650  val fromPcTargetMem = Flipped(new PcToDataPathIO(params))
651
652  val debugIntRat     = if (params.debugEn) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None
653  val debugFpRat      = if (params.debugEn) Some(Input(Vec(32, UInt(fpSchdParams.pregIdxWidth.W)))) else None
654  val debugVecRat     = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None
655  val debugVconfigRat = if (params.debugEn) Some(Input(UInt(vfSchdParams.pregIdxWidth.W))) else None
656  val debugVconfig    = if (params.debugEn) Some(Output(UInt(XLEN.W))) else None
657}
658