1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule} 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility._ 9import utils.SeqUtils._ 10import utils._ 11import xiangshan._ 12import xiangshan.backend.BackendParams 13import xiangshan.backend.Bundles._ 14import xiangshan.backend.decode.ImmUnion 15import xiangshan.backend.datapath.DataConfig._ 16import xiangshan.backend.datapath.RdConfig._ 17import xiangshan.backend.issue.{FpScheduler, ImmExtractor, IntScheduler, MemScheduler, VfScheduler} 18import xiangshan.backend.issue.EntryBundles._ 19import xiangshan.backend.regfile._ 20import xiangshan.backend.regcache._ 21import xiangshan.backend.PcToDataPathIO 22import xiangshan.backend.fu.FuType.is0latency 23import xiangshan.mem.{SqPtr, LqPtr} 24 25class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { 26 override def shouldBeInlined: Boolean = false 27 28 private implicit val dpParams: BackendParams = params 29 lazy val module = new DataPathImp(this) 30 31 println(s"[DataPath] Preg Params: ") 32 println(s"[DataPath] Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ") 33 println(s"[DataPath] Fp R(${params.getRfReadSize(FpData())}), W(${params.getRfWriteSize(FpData())}) ") 34 println(s"[DataPath] Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ") 35 println(s"[DataPath] V0 R(${params.getRfReadSize(V0Data())}), W(${params.getRfWriteSize(V0Data())}) ") 36 println(s"[DataPath] Vl R(${params.getRfReadSize(VlData())}), W(${params.getRfWriteSize(VlData())}) ") 37} 38 39class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams) 40 extends LazyModuleImp(wrapper) with HasXSParameter { 41 42 val io = IO(new DataPathIO()) 43 44 private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu) 45 private val (fromFpIQ, toFpIQ, toFpExu) = (io.fromFpIQ, io.toFpIQ, io.toFpExu) 46 private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu) 47 private val (fromVfIQ, toVfIQ, toVfExu ) = (io.fromVfIQ, io.toVfIQ, io.toVecExu) 48 49 println(s"[DataPath] IntIQ(${fromIntIQ.size}), FpIQ(${fromFpIQ.size}), VecIQ(${fromVfIQ.size}), MemIQ(${fromMemIQ.size})") 50 println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), FpExu(${fromFpIQ.map(_.size).sum}), VecExu(${fromVfIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})") 51 52 // just refences for convience 53 private val fromIQ: Seq[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = (fromIntIQ ++ fromFpIQ ++ fromVfIQ ++ fromMemIQ).toSeq 54 55 private val toIQs = toIntIQ ++ toFpIQ ++ toVfIQ ++ toMemIQ 56 57 private val toExu: Seq[MixedVec[DecoupledIO[ExuInput]]] = (toIntExu ++ toFpExu ++ toVfExu ++ toMemExu).toSeq 58 59 private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten 60 61 private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten 62 63 private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams)) 64 private val fpWbBusyArbiter = Module(new FpRFWBCollideChecker(backendParams)) 65 private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams)) 66 private val v0WbBusyArbiter = Module(new V0RFWBCollideChecker(backendParams)) 67 private val vlWbBusyArbiter = Module(new VlRFWBCollideChecker(backendParams)) 68 69 private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams)) 70 private val fpRFReadArbiter = Module(new FpRFReadArbiter(backendParams)) 71 private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams)) 72 private val v0RFReadArbiter = Module(new V0RFReadArbiter(backendParams)) 73 private val vlRFReadArbiter = Module(new VlRFReadArbiter(backendParams)) 74 75 private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 76 private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 77 78 // port -> win 79 private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 80 private val fpRdArbWinner: Seq2[MixedVec[Bool]] = fpRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 81 private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 82 private val v0RdArbWinner: Seq2[MixedVec[Bool]] = v0RFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 83 private val vlRdArbWinner: Seq2[MixedVec[Bool]] = vlRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 84 85 private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 86 private val fpWbNotBlock: Seq[MixedVec[Bool]] = fpWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 87 private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 88 private val v0WbNotBlock: Seq[MixedVec[Bool]] = v0WbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 89 private val vlWbNotBlock: Seq[MixedVec[Bool]] = vlWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 90 91 private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR)) 92 private val fpRdNotBlock: Seq2[Bool] = fpRdArbWinner.map(_.map(_.asUInt.andR)) 93 private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR)) 94 private val v0RdNotBlock: Seq2[Bool] = v0RdArbWinner.map(_.map(_.asUInt.andR)) 95 private val vlRdNotBlock: Seq2[Bool] = vlRdArbWinner.map(_.map(_.asUInt.andR)) 96 97 private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 98 private val fpRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 99 private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 100 private val v0RFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 101 private val vlRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getRfReadValidBundle(xx.valid)).toSeq).toSeq 102 103 private val allDataSources: Seq[Seq[Vec[DataSource]]] = fromIQ.map(x => x.map(xx => xx.bits.common.dataSources).toSeq) 104 private val allNumRegSrcs: Seq[Seq[Int]] = fromIQ.map(x => x.map(xx => xx.bits.exuParams.numRegSrc).toSeq) 105 106 intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 107 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 108 val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData()) 109 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 110 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 111 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 112 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 113 } else { 114 arbInSeq(srcIdx).valid := false.B 115 arbInSeq(srcIdx).bits.addr := 0.U 116 } 117 } 118 } 119 } 120 fpRFReadArbiter.io.in.zip(fpRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 121 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 122 val srcIndices: Seq[Int] = FpRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 123 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 124 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 125 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 126 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 127 } else { 128 arbInSeq(srcIdx).valid := false.B 129 arbInSeq(srcIdx).bits.addr := 0.U 130 } 131 } 132 } 133 } 134 135 vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 136 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 137 val srcIndices: Seq[Int] = VecRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 138 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 139 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 140 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 141 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 142 } else { 143 arbInSeq(srcIdx).valid := false.B 144 arbInSeq(srcIdx).bits.addr := 0.U 145 } 146 } 147 } 148 } 149 150 v0RFReadArbiter.io.in.zip(v0RFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 151 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 152 val srcIndices: Seq[Int] = V0RegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 153 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 154 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 155 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 156 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 157 } else { 158 arbInSeq(srcIdx).valid := false.B 159 arbInSeq(srcIdx).bits.addr := 0.U 160 } 161 } 162 } 163 } 164 165 vlRFReadArbiter.io.in.zip(vlRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 166 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 167 val srcIndices: Seq[Int] = VlRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 168 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 169 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 170 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid && allDataSources(iqIdx)(exuIdx)(srcIdx).readReg 171 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 172 } else { 173 arbInSeq(srcIdx).valid := false.B 174 arbInSeq(srcIdx).bits.addr := 0.U 175 } 176 } 177 } 178 } 179 180 private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B)).toSeq).toSeq 181 private val fpRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.fpWen.getOrElse(false.B)).toSeq).toSeq 182 private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.vecWen.getOrElse(false.B)).toSeq).toSeq 183 private val v0RFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.v0Wen.getOrElse(false.B)).toSeq).toSeq 184 private val vlRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.vlWen.getOrElse(false.B)).toSeq).toSeq 185 186 intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 187 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 188 arbIn.valid := inRFWriteReq 189 } 190 } 191 192 fpWbBusyArbiter.io.in.zip(fpRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 193 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 194 arbIn.valid := inRFWriteReq 195 } 196 } 197 198 vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 199 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 200 arbIn.valid := inRFWriteReq 201 } 202 } 203 204 v0WbBusyArbiter.io.in.zip(v0RFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 205 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 206 arbIn.valid := inRFWriteReq 207 } 208 } 209 210 vlWbBusyArbiter.io.in.zip(vlRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 211 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 212 arbIn.valid := inRFWriteReq 213 } 214 } 215 216 private val intSchdParams = params.schdParams(IntScheduler()) 217 private val fpSchdParams = params.schdParams(FpScheduler()) 218 private val vfSchdParams = params.schdParams(VfScheduler()) 219 private val memSchdParams = params.schdParams(MemScheduler()) 220 221 private val schdParams = params.allSchdParams 222 223 private val pcReadValid = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathValid)) 224 private val pcReadFtqPtr = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqPtr)) 225 private val pcReadFtqOffset = Wire(chiselTypeOf(io.fromPcTargetMem.fromDataPathFtqOffset)) 226 private val targetPCRdata = io.fromPcTargetMem.toDataPathTargetPC 227 private val pcRdata = io.fromPcTargetMem.toDataPathPC 228 private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W))) 229 private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W))) 230 private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool())) 231 private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W))) 232 private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W))) 233 234 private val fpRfRaddr = Wire(Vec(params.numPregRd(FpData()), UInt(fpSchdParams.pregIdxWidth.W))) 235 private val fpRfRdata = Wire(Vec(params.numPregRd(FpData()), UInt(fpSchdParams.rfDataWidth.W))) 236 private val fpRfWen = Wire(Vec(io.fromFpWb.length, Bool())) 237 private val fpRfWaddr = Wire(Vec(io.fromFpWb.length, UInt(fpSchdParams.pregIdxWidth.W))) 238 private val fpRfWdata = Wire(Vec(io.fromFpWb.length, UInt(fpSchdParams.rfDataWidth.W))) 239 240 private val vfRfSplitNum = VLEN / XLEN 241 private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W))) 242 private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W))) 243 private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool()))) 244 private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W))) 245 private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W))) 246 247 private val v0RfSplitNum = VLEN / XLEN 248 private val v0RfRaddr = Wire(Vec(params.numPregRd(V0Data()), UInt(log2Up(V0PhyRegs).W))) 249 private val v0RfRdata = Wire(Vec(params.numPregRd(V0Data()), UInt(V0Data().dataWidth.W))) 250 private val v0RfWen = Wire(Vec(v0RfSplitNum, Vec(io.fromV0Wb.length, Bool()))) 251 private val v0RfWaddr = Wire(Vec(io.fromV0Wb.length, UInt(log2Up(V0PhyRegs).W))) 252 private val v0RfWdata = Wire(Vec(io.fromV0Wb.length, UInt(V0Data().dataWidth.W))) 253 254 private val vlRfRaddr = Wire(Vec(params.numPregRd(VlData()), UInt(log2Up(VlPhyRegs).W))) 255 private val vlRfRdata = Wire(Vec(params.numPregRd(VlData()), UInt(VlData().dataWidth.W))) 256 private val vlRfWen = Wire(Vec(io.fromVlWb.length, Bool())) 257 private val vlRfWaddr = Wire(Vec(io.fromVlWb.length, UInt(log2Up(VlPhyRegs).W))) 258 private val vlRfWdata = Wire(Vec(io.fromVlWb.length, UInt(VlData().dataWidth.W))) 259 260 val pcReadFtqPtrFormIQ = fromIntIQ.flatten.filter(x => x.bits.exuParams.needPc) 261 assert(pcReadFtqPtrFormIQ.size == pcReadFtqPtr.size, s"pcReadFtqPtrFormIQ.size ${pcReadFtqPtrFormIQ.size} not equal pcReadFtqPtr.size ${pcReadFtqPtr.size}") 262 pcReadValid.zip(pcReadFtqPtrFormIQ.map(_.valid)).map(x => x._1 := x._2) 263 pcReadFtqPtr.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqIdx.get)).map(x => x._1 := x._2) 264 pcReadFtqOffset.zip(pcReadFtqPtrFormIQ.map(_.bits.common.ftqOffset.get)).map(x => x._1 := x._2) 265 io.fromPcTargetMem.fromDataPathValid := pcReadValid 266 io.fromPcTargetMem.fromDataPathFtqPtr := pcReadFtqPtr 267 io.fromPcTargetMem.fromDataPathFtqOffset := pcReadFtqOffset 268 269 private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] = 270 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W))))) 271 private val fpDebugRead: Option[(Vec[UInt], Vec[UInt])] = 272 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(32, UInt(fpSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W))))) 273 private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] = 274 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(31, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(31, UInt(VLEN.W))))) 275 private val v0DebugRead: Option[(Vec[UInt], Vec[UInt])] = 276 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(1, UInt(log2Up(V0PhyRegs).W))), Wire(Vec(1, UInt(V0Data().dataWidth.W))))) 277 private val vlDebugRead: Option[(Vec[UInt], Vec[UInt])] = 278 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, (Wire(Vec(1, UInt(log2Up(VlPhyRegs).W))), Wire(Vec(1, UInt(VlData().dataWidth.W))))) 279 280 private val fpDebugReadData: Option[Vec[UInt]] = 281 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, Wire(Vec(32, UInt(XLEN.W)))) 282 private val vecDebugReadData: Option[Vec[UInt]] = 283 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0)) 284 private val vlDebugReadData: Option[UInt] = 285 OptionWrapper(env.AlwaysBasicDiff || env.EnableDifftest, Wire(UInt(VlData().dataWidth.W))) 286 287 288 fpDebugReadData.foreach(_ := fpDebugRead 289 .get._2 290 .slice(0, 32) 291 .map(_(63, 0)) 292 ) // fp only used [63, 0] 293 vecDebugReadData.foreach(_ := 294 v0DebugRead 295 .get._2 296 .slice(0, 1) 297 .map(x => Seq(x(63, 0), x(127, 64))).flatten ++ 298 vfDebugRead 299 .get._2 300 .slice(0, 31) 301 .map(x => Seq(x(63, 0), x(127, 64))).flatten 302 ) 303 vlDebugReadData.foreach(_ := vlDebugRead 304 .get._2(0) 305 ) 306 307 io.debugVl.foreach(_ := vlDebugReadData.get) 308 309 IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata, 310 bankNum = 1, 311 debugReadAddr = intDebugRead.map(_._1), 312 debugReadData = intDebugRead.map(_._2) 313 ) 314 FpRegFile("FpRegFile", fpSchdParams.numPregs, fpRfRaddr, fpRfRdata, fpRfWen, fpRfWaddr, fpRfWdata, 315 bankNum = 1, 316 debugReadAddr = fpDebugRead.map(_._1), 317 debugReadData = fpDebugRead.map(_._2) 318 ) 319 VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata, 320 debugReadAddr = vfDebugRead.map(_._1), 321 debugReadData = vfDebugRead.map(_._2) 322 ) 323 VfRegFile("V0RegFile", V0PhyRegs, v0RfSplitNum, v0RfRaddr, v0RfRdata, v0RfWen, v0RfWaddr, v0RfWdata, 324 debugReadAddr = v0DebugRead.map(_._1), 325 debugReadData = v0DebugRead.map(_._2) 326 ) 327 FpRegFile("VlRegFile", VlPhyRegs, vlRfRaddr, vlRfRdata, vlRfWen, vlRfWaddr, vlRfWdata, 328 bankNum = 1, 329 debugReadAddr = vlDebugRead.map(_._1), 330 debugReadData = vlDebugRead.map(_._2) 331 ) 332 333 intRfWaddr := io.fromIntWb.map(x => RegEnable(x.addr, x.wen)).toSeq 334 intRfWdata := io.fromIntWb.map(x => RegEnable(x.data, x.wen)).toSeq 335 intRfWen := RegNext(VecInit(io.fromIntWb.map(_.wen).toSeq)) 336 337 for (portIdx <- intRfRaddr.indices) { 338 if (intRFReadArbiter.io.out.isDefinedAt(portIdx)) 339 intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr 340 else 341 intRfRaddr(portIdx) := 0.U 342 } 343 344 fpRfWaddr := io.fromFpWb.map(x => RegEnable(x.addr, x.wen)).toSeq 345 fpRfWdata := io.fromFpWb.map(x => RegEnable(x.data, x.wen)).toSeq 346 fpRfWen := RegNext(VecInit(io.fromFpWb.map(_.wen).toSeq)) 347 348 for (portIdx <- fpRfRaddr.indices) { 349 if (fpRFReadArbiter.io.out.isDefinedAt(portIdx)) 350 fpRfRaddr(portIdx) := fpRFReadArbiter.io.out(portIdx).bits.addr 351 else 352 fpRfRaddr(portIdx) := 0.U 353 } 354 355 vfRfWaddr := io.fromVfWb.map(x => RegEnable(x.addr, x.wen)).toSeq 356 vfRfWdata := io.fromVfWb.map(x => RegEnable(x.data, x.wen)).toSeq 357 vfRfWen.foreach(_.zip(io.fromVfWb.map(x => RegNext(x.wen))).foreach { case (wenSink, wenSource) => wenSink := wenSource } ) 358 359 for (portIdx <- vfRfRaddr.indices) { 360 if (vfRFReadArbiter.io.out.isDefinedAt(portIdx)) 361 vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr 362 else 363 vfRfRaddr(portIdx) := 0.U 364 } 365 366 v0RfWaddr := io.fromV0Wb.map(_.addr).toSeq 367 v0RfWdata := io.fromV0Wb.map(_.data).toSeq 368 v0RfWen.foreach(_.zip(io.fromV0Wb.map(_.wen)).foreach { case (wenSink, wenSource) => wenSink := wenSource } ) 369 370 for (portIdx <- v0RfRaddr.indices) { 371 if (v0RFReadArbiter.io.out.isDefinedAt(portIdx)) 372 v0RfRaddr(portIdx) := v0RFReadArbiter.io.out(portIdx).bits.addr 373 else 374 v0RfRaddr(portIdx) := 0.U 375 } 376 377 vlRfWaddr := io.fromVlWb.map(_.addr).toSeq 378 vlRfWdata := io.fromVlWb.map(_.data).toSeq 379 vlRfWen := io.fromVlWb.map(_.wen).toSeq 380 381 for (portIdx <- vlRfRaddr.indices) { 382 if (vlRFReadArbiter.io.out.isDefinedAt(portIdx)) 383 vlRfRaddr(portIdx) := vlRFReadArbiter.io.out(portIdx).bits.addr 384 else 385 vlRfRaddr(portIdx) := 0.U 386 } 387 388 389 intDebugRead.foreach { case (addr, _) => 390 addr := io.debugIntRat.get 391 } 392 393 fpDebugRead.foreach { case (addr, _) => 394 addr := io.debugFpRat.get 395 } 396 397 vfDebugRead.foreach { case (addr, _) => 398 addr := io.debugVecRat.get 399 } 400 v0DebugRead.foreach { case (addr, _) => 401 addr := io.debugV0Rat.get 402 } 403 vlDebugRead.foreach { case (addr, _) => 404 addr := io.debugVlRat.get 405 } 406 407 println(s"[DataPath] " + 408 s"has intDebugRead: ${intDebugRead.nonEmpty}, " + 409 s"has fpDebugRead: ${fpDebugRead.nonEmpty}, " + 410 s"has vecDebugRead: ${vfDebugRead.nonEmpty}, " + 411 s"has v0DebugRead: ${v0DebugRead.nonEmpty}, " + 412 s"has vlDebugRead: ${vlDebugRead.nonEmpty}") 413 414 // regcache 415 private val regCache = Module(new RegCache()) 416 417 def IssueBundle2RCReadPort(issue: DecoupledIO[IssueQueueIssueBundle]): Vec[RCReadPort] = { 418 val readPorts = Wire(Vec(issue.bits.exuParams.numIntSrc, new RCReadPort(params.intSchdParams.get.rfDataWidth, RegCacheIdxWidth))) 419 readPorts.zipWithIndex.foreach{ case (r, idx) => 420 r.ren := issue.valid && issue.bits.common.dataSources(idx).readRegCache 421 r.addr := issue.bits.rcIdx.get(idx) 422 r.data := DontCare 423 } 424 readPorts 425 } 426 427 private val regCacheReadReq = fromIntIQ.flatten.filter(_.bits.exuParams.numIntSrc > 0).flatMap(IssueBundle2RCReadPort(_)) ++ 428 fromMemIQ.flatten.filter(_.bits.exuParams.numIntSrc > 0).flatMap(IssueBundle2RCReadPort(_)) 429 private val regCacheReadData = regCache.io.readPorts.map(_.data) 430 431 println(s"[DataPath] regCache readPorts size: ${regCache.io.readPorts.size}, regCacheReadReq size: ${regCacheReadReq.size}") 432 require(regCache.io.readPorts.size == regCacheReadReq.size, "reg cache's readPorts size should be equal to regCacheReadReq") 433 434 regCache.io.readPorts.zip(regCacheReadReq).foreach{ case (r, req) => 435 r.ren := req.ren 436 r.addr := req.addr 437 } 438 439 val s1_RCReadData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 440 s1_RCReadData.foreach(_.foreach(_.foreach(_ := 0.U))) 441 s1_RCReadData.zip(toExu).filter(_._2.map(_.bits.params.isIntExeUnit).reduce(_ || _)).flatMap(_._1).flatten 442 .zip(regCacheReadData.take(params.getIntExuRCReadSize)).foreach{ case (s1_data, rdata) => 443 s1_data := rdata 444 } 445 s1_RCReadData.zip(toExu).filter(_._2.map(x => x.bits.params.isMemExeUnit && x.bits.params.readIntRf).reduce(_ || _)).flatMap(_._1).flatten 446 .zip(regCacheReadData.takeRight(params.getMemExuRCReadSize)).foreach{ case (s1_data, rdata) => 447 s1_data := rdata 448 } 449 450 println(s"[DataPath] s1_RCReadData.int.size: ${s1_RCReadData.zip(toExu).filter(_._2.map(_.bits.params.isIntExeUnit).reduce(_ || _)).flatMap(_._1).flatten.size}, RCRdata.int.size: ${params.getIntExuRCReadSize}") 451 println(s"[DataPath] s1_RCReadData.mem.size: ${s1_RCReadData.zip(toExu).filter(_._2.map(x => x.bits.params.isMemExeUnit && x.bits.params.readIntRf).reduce(_ || _)).flatMap(_._1).flatten.size}, RCRdata.mem.size: ${params.getMemExuRCReadSize}") 452 453 io.toWakeupQueueRCIdx := regCache.io.toWakeupQueueRCIdx 454 io.toBypassNetworkRCData := s1_RCReadData 455 regCache.io.writePorts := io.fromBypassNetwork 456 457 val s1_addrOHs = Reg(MixedVec( 458 fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType).toSeq)).toSeq 459 )) 460 val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec( 461 toExu.map(x => MixedVec(x.map(_.valid.cloneType).toSeq)).toSeq 462 )) 463 val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType).toSeq)).toSeq)) 464 val s1_immInfo = Reg(MixedVec(toExu.map(x => MixedVec(x.map(x => new ImmInfo).toSeq)).toSeq)) 465 s1_immInfo.zip(fromIQ).map { case (s1Vec, s0Vec) => 466 s1Vec.zip(s0Vec).map { case (s1, s0) => 467 s1.imm := Mux(s0.valid, s0.bits.common.imm, s1.imm) 468 s1.immType := Mux(s0.valid, s0.bits.immType, s1.immType) 469 } 470 } 471 io.og1ImmInfo.zip(s1_immInfo.flatten).map{ case(out, reg) => 472 out := reg 473 } 474 val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType).toSeq)))) 475 val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire)).toSeq))) 476 477 val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 478 val s1_fpPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 479 val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 480 val s1_v0PregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 481 val s1_vlPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType).toSeq)))) 482 483 val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs)) 484 485 println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}") 486 s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 487 s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 488 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 489 iuRdata.zip(iuCfg) 490 .filter { case (_, cfg) => cfg.count(_.isInstanceOf[IntRD]) > 0 } 491 .foreach { case (sink, cfg) => sink := intRfRdata(cfg.find(_.isInstanceOf[IntRD]).get.port) } 492 } 493 } 494 495 println(s"[DataPath] s1_fpPregRData.flatten.flatten.size: ${s1_fpPregRData.flatten.flatten.size}, fpRfRdata.size: ${fpRfRdata.size}") 496 s1_fpPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 497 s1_fpPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 498 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 499 iuRdata.zip(iuCfg) 500 .filter { case (_, cfg) => cfg.count(_.isInstanceOf[FpRD]) > 0 } 501 .foreach { case (sink, cfg) => sink := fpRfRdata(cfg.find(_.isInstanceOf[FpRD]).get.port) } 502 } 503 } 504 505 println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}") 506 s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 507 s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 508 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 509 iuRdata.zip(iuCfg) 510 .filter { case (_, cfg) => cfg.count(_.isInstanceOf[VfRD]) > 0 } 511 .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.find(_.isInstanceOf[VfRD]).get.port) } 512 } 513 } 514 515 println(s"[DataPath] s1_v0PregRData.flatten.flatten.size: ${s1_v0PregRData.flatten.flatten.size}, v0RfRdata.size: ${v0RfRdata.size}") 516 s1_v0PregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 517 s1_v0PregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 518 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 519 iuRdata.zip(iuCfg) 520 .filter { case (_, cfg) => cfg.count(_.isInstanceOf[V0RD]) > 0 } 521 .foreach { case (sink, cfg) => sink := v0RfRdata(cfg.find(_.isInstanceOf[V0RD]).get.port) } 522 } 523 } 524 525 println(s"[DataPath] s1_vlPregRData.flatten.flatten.size: ${s1_vlPregRData.flatten.flatten.size}, vlRfRdata.size: ${vlRfRdata.size}") 526 s1_vlPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 527 s1_vlPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 528 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 529 iuRdata.zip(iuCfg) 530 .filter { case (_, cfg) => cfg.count(_.isInstanceOf[VlRD]) > 0 } 531 .foreach { case (sink, cfg) => sink := vlRfRdata(cfg.find(_.isInstanceOf[VlRD]).get.port) } 532 } 533 } 534 535 val og0_cancel_no_load = VecInit(og0FailedVec2.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1).toSeq) 536 val exuParamsNoLoad = fromIQ.flatten.zip(params.allExuParams).filter(!_._2.hasLoadFu) 537 val is_0latency = Wire(Vec(og0_cancel_no_load.size, Bool())) 538 is_0latency := exuParamsNoLoad.map(x => is0latency(x._1.bits.common.fuType)) 539 val og0_cancel_delay = RegNext(VecInit(og0_cancel_no_load.zip(is_0latency).map(x => x._1 && x._2))) 540 val isVfScheduler = VecInit(exuParamsNoLoad.map(x => x._2.schdType.isInstanceOf[VfScheduler].B)) 541 val og0_cancel_delay_for_mem = VecInit(og0_cancel_delay.zip(isVfScheduler).map(x => x._1 && !x._2)) 542 for (i <- fromIQ.indices) { 543 for (j <- fromIQ(i).indices) { 544 // IQ(s0) --[Ctrl]--> s1Reg ---------- begin 545 // refs 546 val s1_valid = s1_toExuValid(i)(j) 547 val s1_ready = s1_toExuReady(i)(j) 548 val s1_data = s1_toExuData(i)(j) 549 val s1_addrOH = s1_addrOHs(i)(j) 550 val s0 = fromIQ(i)(j) // s0 551 552 val srcNotBlock = Wire(Bool()) 553 srcNotBlock := s0.bits.common.dataSources.zip(intRdArbWinner(i)(j) zip fpRdArbWinner(i)(j) zip vfRdArbWinner(i)(j) zip v0RdArbWinner(i)(j) zip vlRdArbWinner(i)(j)).map { 554 case (source, ((((win_int, win_fp), win_vf), win_v0), win_vl)) => 555 !source.readReg || win_int && win_fp && win_vf && win_v0 && win_vl 556 }.fold(true.B)(_ && _) 557 val notBlock = srcNotBlock && intWbNotBlock(i)(j) && fpWbNotBlock(i)(j) && vfWbNotBlock(i)(j) && v0WbNotBlock(i)(j) && vlWbNotBlock(i)(j) 558 val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush))) 559 val s1_cancel = og1FailedVec2(i)(j) 560 val s0_cancel = Wire(Bool()) 561 val og0_cancel_delay_need = if (s0.bits.exuParams.schdType.isInstanceOf[MemScheduler]) og0_cancel_delay_for_mem else og0_cancel_delay 562 if (s0.bits.exuParams.isIQWakeUpSink) { 563 val exuOHNoLoad = s0.bits.common.l1ExuOH.get.map(x => x.asTypeOf(Vec(x.getWidth, Bool())).zip(params.allExuParams).filter(!_._2.hasLoadFu).map(_._1)) 564 s0_cancel := exuOHNoLoad.zip(s0.bits.common.dataSources).map{ 565 case (exuOH, dataSource) => (VecInit(exuOH).asUInt & og0_cancel_delay_need.asUInt).orR && dataSource.readForward 566 }.reduce(_ || _) && s0.valid 567 } else s0_cancel := false.B 568 val s0_ldCancel = LoadShouldCancel(s0.bits.common.loadDependency, io.ldCancel) 569 when (s0.fire && !s1_flush && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel) { 570 s1_valid := s0.valid 571 }.otherwise { 572 s1_valid := false.B 573 } 574 when (s0.valid) { 575 s1_data.fromIssueBundle(s0.bits) // no src data here 576 s1_addrOH := s0.bits.addrOH 577 } 578 s0.ready := (s1_ready || !s1_valid) && notBlock && !s1_cancel && !s0_ldCancel && !s0_cancel 579 // IQ(s0) --[Ctrl]--> s1Reg ---------- end 580 } 581 } 582 583 private val fromIQFire = fromIQ.map(_.map(_.fire)) 584 private val toExuFire = toExu.map(_.map(_.fire)) 585 toIQs.zipWithIndex.foreach { 586 case(toIQ, iqIdx) => 587 toIQ.zipWithIndex.foreach { 588 case (toIU, iuIdx) => 589 // IU: issue unit 590 val og0resp = toIU.og0resp 591 og0FailedVec2(iqIdx)(iuIdx) := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx)) 592 og0resp.valid := og0FailedVec2(iqIdx)(iuIdx) 593 og0resp.bits.robIdx := fromIQ(iqIdx)(iuIdx).bits.common.robIdx 594 og0resp.bits.uopIdx.foreach(_ := fromIQ(iqIdx)(iuIdx).bits.common.vpu.get.vuopIdx) 595 og0resp.bits.sqIdx.foreach(_ := 0.U.asTypeOf(new SqPtr)) 596 og0resp.bits.lqIdx.foreach(_ := 0.U.asTypeOf(new LqPtr)) 597 og0resp.bits.resp := RespType.block 598 og0resp.bits.fuType := fromIQ(iqIdx)(iuIdx).bits.common.fuType 599 600 val og1resp = toIU.og1resp 601 og1FailedVec2(iqIdx)(iuIdx) := s1_toExuValid(iqIdx)(iuIdx) && !toExuFire(iqIdx)(iuIdx) 602 og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) 603 og1resp.bits.robIdx := s1_toExuData(iqIdx)(iuIdx).robIdx 604 og1resp.bits.uopIdx.foreach(_ := s1_toExuData(iqIdx)(iuIdx).vpu.get.vuopIdx) 605 og1resp.bits.sqIdx.foreach(_ := 0.U.asTypeOf(new SqPtr)) 606 og1resp.bits.lqIdx.foreach(_ := 0.U.asTypeOf(new LqPtr)) 607 // respType: fuIdle ->IQ entry clear 608 // fuUncertain ->IQ entry no action 609 // fuBusy ->IQ entry issued set false, then re-issue 610 // hyu, lda and sta are fuUncertain at OG1 stage 611 // and all vector arith exu should check success in og2 stage 612 og1resp.bits.resp := Mux(og1FailedVec2(iqIdx)(iuIdx), 613 RespType.block, 614 if (toIU.issueQueueParams match { case x => x.isLdAddrIQ || x.isStAddrIQ || x.isHyAddrIQ || x.isVecLduIQ || x.isVecStuIQ || x.inVfSchd}) 615 RespType.uncertain 616 else 617 RespType.success, 618 ) 619 og1resp.bits.fuType := s1_toExuData(iqIdx)(iuIdx).fuType 620 } 621 } 622 623 io.og0Cancel := og0FailedVec2.flatten.zip(params.allExuParams).map{ case (cancel, params) => 624 if (params.isIQWakeUpSource && params.latencyCertain && params.wakeUpFuLatancySet.contains(0)) cancel else false.B 625 }.toSeq 626 io.og1Cancel := toFlattenExu.map(x => x.valid && !x.fire) 627 628 629 if (backendParams.debugEn){ 630 dontTouch(og0_cancel_no_load) 631 dontTouch(is_0latency) 632 dontTouch(og0_cancel_delay) 633 dontTouch(isVfScheduler) 634 dontTouch(og0_cancel_delay_for_mem) 635 } 636 for (i <- toExu.indices) { 637 for (j <- toExu(i).indices) { 638 // s1Reg --[Ctrl]--> exu(s1) ---------- begin 639 // refs 640 val sinkData = toExu(i)(j).bits 641 // assign 642 toExu(i)(j).valid := s1_toExuValid(i)(j) 643 s1_toExuReady(i)(j) := toExu(i)(j).ready 644 sinkData := s1_toExuData(i)(j) 645 // s1Reg --[Ctrl]--> exu(s1) ---------- end 646 647 // s1Reg --[Data]--> exu(s1) ---------- begin 648 // data source1: preg read data 649 for (k <- sinkData.src.indices) { 650 val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k) 651 val readRfMap: Seq[(Bool, UInt)] = ( 652 if (k == 3) {( 653 Seq(None) 654 :+ 655 OptionWrapper(s1_v0PregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(V0RegSrcDataSet).nonEmpty, 656 (SrcType.isV0(s1_srcType(i)(j)(k)) -> s1_v0PregRData(i)(j)(k))) 657 )} 658 else if (k == 4) {( 659 Seq(None) 660 :+ 661 OptionWrapper(s1_vlPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VlRegSrcDataSet).nonEmpty, 662 (SrcType.isVp(s1_srcType(i)(j)(k)) -> s1_vlPregRData(i)(j)(k))) 663 )} 664 else {( 665 Seq(None) 666 :+ 667 OptionWrapper(s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty, 668 (SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k))) 669 :+ 670 OptionWrapper(s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VecRegSrcDataSet).nonEmpty, 671 (SrcType.isVp(s1_srcType(i)(j)(k)) -> s1_vfPregRData(i)(j)(k))) 672 :+ 673 OptionWrapper(s1_fpPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(FpRegSrcDataSet).nonEmpty, 674 (SrcType.isFp(s1_srcType(i)(j)(k)) -> s1_fpPregRData(i)(j)(k))) 675 )} 676 ).filter(_.nonEmpty).map(_.get) 677 678 if (readRfMap.nonEmpty) 679 sinkData.src(k) := Mux1H(readRfMap) 680 } 681 if (sinkData.params.hasJmpFu) { 682 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 683 sinkData.pc.get := pcRdata(index) 684 } 685 if (sinkData.params.needTarget) { 686 val index = pcReadFtqPtrFormIQ.map(_.bits.exuParams).indexOf(sinkData.params) 687 sinkData.predictInfo.get.target := targetPCRdata(index) 688 } 689 } 690 } 691 692 if (env.AlwaysBasicDiff || env.EnableDifftest) { 693 val delayedCnt = 2 694 val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt) 695 difftestArchIntRegState.coreid := io.hartId 696 difftestArchIntRegState.value := intDebugRead.get._2 697 698 val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt) 699 difftestArchFpRegState.coreid := io.hartId 700 difftestArchFpRegState.value := fpDebugReadData.get 701 702 val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt) 703 difftestArchVecRegState.coreid := io.hartId 704 difftestArchVecRegState.value := vecDebugReadData.get 705 } 706 707 val int_regcache_size = 48 708 val int_regcache_tag = RegInit(VecInit(Seq.fill(int_regcache_size)(0.U(intSchdParams.pregIdxWidth.W)))) 709 val int_regcache_enqPtr = RegInit(0.U(log2Up(int_regcache_size).W)) 710 int_regcache_enqPtr := int_regcache_enqPtr + PopCount(intRfWen) 711 for (i <- intRfWen.indices) { 712 when (intRfWen(i)) { 713 int_regcache_tag(int_regcache_enqPtr + PopCount(intRfWen.take(i))) := intRfWaddr(i) 714 } 715 } 716 717 val vf_regcache_size = 48 718 val vf_regcache_tag = RegInit(VecInit(Seq.fill(vf_regcache_size)(0.U(vfSchdParams.pregIdxWidth.W)))) 719 val vf_regcache_enqPtr = RegInit(0.U(log2Up(vf_regcache_size).W)) 720 vf_regcache_enqPtr := vf_regcache_enqPtr + PopCount(vfRfWen.head) 721 for (i <- vfRfWen.indices) { 722 when (vfRfWen.head(i)) { 723 vf_regcache_tag(vf_regcache_enqPtr + PopCount(vfRfWen.head.take(i))) := vfRfWaddr(i) 724 } 725 } 726 727 XSPerfHistogram(s"IntRegFileRead_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 728 XSPerfHistogram(s"FpRegFileRead_hist", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 729 XSPerfHistogram(s"VfRegFileRead_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 20, 1) 730 XSPerfHistogram(s"IntRegFileWrite_hist", PopCount(intRFWriteReq.flatten), true.B, 0, 20, 1) 731 XSPerfHistogram(s"FpRegFileWrite_hist", PopCount(fpRFWriteReq.flatten), true.B, 0, 20, 1) 732 XSPerfHistogram(s"VfRegFileWrite_hist", PopCount(vfRFWriteReq.flatten), true.B, 0, 20, 1) 733 734 val int_regcache_part32 = (1 until 33).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 735 val int_regcache_part24 = (1 until 24).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 736 val int_regcache_part16 = (1 until 17).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 737 val int_regcache_part8 = (1 until 9).map(i => int_regcache_tag(int_regcache_enqPtr - i.U)) 738 739 val int_regcache_48_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_tag.map(_ === x.bits.addr).reduce(_ || _)) 740 val int_regcache_8_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part8.map(_ === x.bits.addr).reduce(_ || _)) 741 val int_regcache_16_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part16.map(_ === x.bits.addr).reduce(_ || _)) 742 val int_regcache_24_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part24.map(_ === x.bits.addr).reduce(_ || _)) 743 val int_regcache_32_hit_vec = intRFReadArbiter.io.in.flatten.flatten.map(x => x.valid && int_regcache_part32.map(_ === x.bits.addr).reduce(_ || _)) 744 XSPerfAccumulate("IntRegCache48Hit", PopCount(int_regcache_48_hit_vec)) 745 XSPerfAccumulate("IntRegCache8Hit", PopCount(int_regcache_8_hit_vec)) 746 XSPerfAccumulate("IntRegCache16Hit", PopCount(int_regcache_16_hit_vec)) 747 XSPerfAccumulate("IntRegCache24Hit", PopCount(int_regcache_24_hit_vec)) 748 XSPerfAccumulate("IntRegCache32Hit", PopCount(int_regcache_32_hit_vec)) 749 XSPerfHistogram("IntRegCache48Hit_hist", PopCount(int_regcache_48_hit_vec), true.B, 0, 16, 2) 750 751 XSPerfAccumulate(s"IntRFReadBeforeArb", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 752 XSPerfAccumulate(s"IntRFReadAfterArb", PopCount(intRFReadArbiter.io.out.map(_.valid))) 753 XSPerfAccumulate(s"FpRFReadBeforeArb", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 754 XSPerfAccumulate(s"FpRFReadAfterArb", PopCount(fpRFReadArbiter.io.out.map(_.valid))) 755 XSPerfAccumulate(s"VfRFReadBeforeArb", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid))) 756 XSPerfAccumulate(s"VfRFReadAfterArb", PopCount(vfRFReadArbiter.io.out.map(_.valid))) 757 XSPerfAccumulate(s"IntUopBeforeArb", PopCount(fromIntIQ.flatten.map(_.valid))) 758 XSPerfAccumulate(s"IntUopAfterArb", PopCount(fromIntIQ.flatten.map(_.fire))) 759 XSPerfAccumulate(s"MemUopBeforeArb", PopCount(fromMemIQ.flatten.map(_.valid))) 760 XSPerfAccumulate(s"MemUopAfterArb", PopCount(fromMemIQ.flatten.map(_.fire))) 761 XSPerfAccumulate(s"VfUopBeforeArb", PopCount(fromVfIQ.flatten.map(_.valid))) 762 XSPerfAccumulate(s"VfUopAfterArb", PopCount(fromVfIQ.flatten.map(_.fire))) 763 764 XSPerfHistogram(s"IntRFReadBeforeArb_hist", PopCount(intRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 765 XSPerfHistogram(s"IntRFReadAfterArb_hist", PopCount(intRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 766 XSPerfHistogram(s"FpRFReadBeforeArb_hist", PopCount(fpRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 767 XSPerfHistogram(s"FpRFReadAfterArb_hist", PopCount(fpRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 768 XSPerfHistogram(s"VfRFReadBeforeArb_hist", PopCount(vfRFReadArbiter.io.in.flatten.flatten.map(_.valid)), true.B, 0, 16, 2) 769 XSPerfHistogram(s"VfRFReadAfterArb_hist", PopCount(vfRFReadArbiter.io.out.map(_.valid)), true.B, 0, 16, 2) 770 XSPerfHistogram(s"IntUopBeforeArb_hist", PopCount(fromIntIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 771 XSPerfHistogram(s"IntUopAfterArb_hist", PopCount(fromIntIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 772 XSPerfHistogram(s"MemUopBeforeArb_hist", PopCount(fromMemIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 773 XSPerfHistogram(s"MemUopAfterArb_hist", PopCount(fromMemIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 774 XSPerfHistogram(s"VfUopBeforeArb_hist", PopCount(fromVfIQ.flatten.map(_.valid)), true.B, 0, 8, 2) 775 XSPerfHistogram(s"VfUopAfterArb_hist", PopCount(fromVfIQ.flatten.map(_.fire)), true.B, 0, 8, 2) 776 777 // datasource perf counter (after arbiter) 778 fromIQ.foreach(iq => iq.foreach{exu => 779 val exuParams = exu.bits.exuParams 780 if (exuParams.isIntExeUnit) { 781 for (i <- 0 until 2) { 782 XSPerfAccumulate(s"INT_ExuId${exuParams.exuIdx}_src${i}_dataSource_forward", exu.fire && exu.bits.common.dataSources(i).readForward) 783 XSPerfAccumulate(s"INT_ExuId${exuParams.exuIdx}_src${i}_dataSource_bypass", exu.fire && exu.bits.common.dataSources(i).readBypass) 784 XSPerfAccumulate(s"INT_ExuId${exuParams.exuIdx}_src${i}_dataSource_regcache", exu.fire && exu.bits.common.dataSources(i).readRegCache) 785 XSPerfAccumulate(s"INT_ExuId${exuParams.exuIdx}_src${i}_dataSource_reg", exu.fire && exu.bits.common.dataSources(i).readReg) 786 XSPerfAccumulate(s"INT_ExuId${exuParams.exuIdx}_src${i}_dataSource_zero", exu.fire && exu.bits.common.dataSources(i).readZero) 787 } 788 } 789 if (exuParams.isMemExeUnit && exuParams.readIntRf) { 790 XSPerfAccumulate(s"MEM_ExuId${exuParams.exuIdx}_src0_dataSource_forward", exu.fire && exu.bits.common.dataSources(0).readForward) 791 XSPerfAccumulate(s"MEM_ExuId${exuParams.exuIdx}_src0_dataSource_bypass", exu.fire && exu.bits.common.dataSources(0).readBypass) 792 XSPerfAccumulate(s"MEM_ExuId${exuParams.exuIdx}_src0_dataSource_regcache", exu.fire && exu.bits.common.dataSources(0).readRegCache) 793 XSPerfAccumulate(s"MEM_ExuId${exuParams.exuIdx}_src0_dataSource_reg", exu.fire && exu.bits.common.dataSources(0).readReg) 794 XSPerfAccumulate(s"MEM_ExuId${exuParams.exuIdx}_src0_dataSource_zero", exu.fire && exu.bits.common.dataSources(0).readZero) 795 } 796 }) 797} 798 799class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 800 // params 801 private val intSchdParams = params.schdParams(IntScheduler()) 802 private val fpSchdParams = params.schdParams(FpScheduler()) 803 private val vfSchdParams = params.schdParams(VfScheduler()) 804 private val memSchdParams = params.schdParams(MemScheduler()) 805 // bundles 806 val hartId = Input(UInt(8.W)) 807 808 val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect)) 809 810 val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle()))))) 811 812 val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 813 Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 814 815 val fromFpIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 816 Flipped(MixedVec(fpSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 817 818 val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 819 Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 820 821 val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 822 823 val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle)) 824 825 val toFpIQ = MixedVec(fpSchdParams.issueBlockParams.map(_.genOGRespBundle)) 826 827 val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle)) 828 829 val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) 830 831 val og0Cancel = Output(ExuVec()) 832 833 val og1Cancel = Output(ExuVec()) 834 835 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 836 837 val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle 838 839 val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(fpSchdParams.genExuInputBundle) 840 841 val toVecExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle) 842 843 val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle 844 845 val og1ImmInfo: Vec[ImmInfo] = Output(Vec(params.allExuParams.size, new ImmInfo)) 846 847 val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle) 848 849 val fromFpWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genFpWriteBackBundle) 850 851 val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle) 852 853 val fromV0Wb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genV0WriteBackBundle) 854 855 val fromVlWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVlWriteBackBundle) 856 857 val fromPcTargetMem = Flipped(new PcToDataPathIO(params)) 858 859 val fromBypassNetwork: Vec[RCWritePort] = Vec(params.getIntExuRCWriteSize + params.getMemExuRCWriteSize, 860 new RCWritePort(params.intSchdParams.get.rfDataWidth, RegCacheIdxWidth, params.intSchdParams.get.pregIdxWidth, params.debugEn) 861 ) 862 863 val toBypassNetworkRCData: MixedVec[MixedVec[Vec[UInt]]] = MixedVec( 864 Seq(intSchdParams, fpSchdParams, vfSchdParams, memSchdParams).map(schd => schd.issueBlockParams.map(iq => 865 MixedVec(iq.exuBlockParams.map(exu => Output(Vec(exu.numRegSrc, UInt(exu.srcDataBitsMax.W))))) 866 )).flatten 867 ) 868 869 val toWakeupQueueRCIdx: Vec[UInt] = Vec(params.getIntExuRCWriteSize + params.getMemExuRCWriteSize, 870 Output(UInt(RegCacheIdxWidth.W)) 871 ) 872 873 val debugIntRat = if (params.debugEn) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None 874 val debugFpRat = if (params.debugEn) Some(Input(Vec(32, UInt(fpSchdParams.pregIdxWidth.W)))) else None 875 val debugVecRat = if (params.debugEn) Some(Input(Vec(31, UInt(vfSchdParams.pregIdxWidth.W)))) else None 876 val debugV0Rat = if (params.debugEn) Some(Input(Vec(1, UInt(log2Up(V0PhyRegs).W)))) else None 877 val debugVlRat = if (params.debugEn) Some(Input(Vec(1, UInt(log2Up(VlPhyRegs).W)))) else None 878 val debugVl = if (params.debugEn) Some(Output(UInt(VlData().dataWidth.W))) else None 879} 880