xref: /XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala (revision bb2f3f51dd67f6e16e0cc1ffe43368c9fc7e4aef) 
1package xiangshan.backend.datapath
2
3import chisel3.util.log2Up
4
5object DataConfig {
6  sealed abstract class DataConfig (
7    val name: String,
8    val dataWidth: Int,
9  ) {
10    override def toString: String = name
11  }
12
13  case class IntData() extends DataConfig("int", 64)
14  case class FpData() extends DataConfig("fp", 64)
15  case class VecData() extends DataConfig("vec", 128)
16  case class ImmData(len: Int) extends DataConfig("int", len)
17  case class VAddrData() extends DataConfig("vaddr", 39) // Todo: associate it with the width of vaddr
18  case class V0Data() extends DataConfig("v0", 128)
19  case class VlData() extends DataConfig("vl", log2Up(VecData().dataWidth) + 1 ) // 8
20  case class FakeIntData() extends DataConfig("fakeint", 64)
21  case class NoData() extends DataConfig("nodata", 0)
22
23  def RegSrcDataSet   : Set[DataConfig] = Set(IntData(), FpData(), VecData(), V0Data(), VlData())
24  def IntRegSrcDataSet: Set[DataConfig] = Set(IntData())
25  def FpRegSrcDataSet : Set[DataConfig] = Set(FpData())
26  def VecRegSrcDataSet : Set[DataConfig] = Set(VecData())
27  def V0RegSrcDataSet : Set[DataConfig] = Set(V0Data())
28  def VlRegSrcDataSet : Set[DataConfig] = Set(VlData())
29
30
31  def RegDataMaxWidth : Int = RegSrcDataSet.map(_.dataWidth).max
32}
33