1package xiangshan.backend.datapath 2 3import chisel3.util.log2Up 4 5object DataConfig { 6 sealed abstract class DataConfig ( 7 val name: String, 8 val dataWidth: Int, 9 ) { 10 override def toString: String = name 11 } 12 13 case class IntData() extends DataConfig("int", 64) 14 case class FpData() extends DataConfig("fp", 64) 15 case class VecData() extends DataConfig("vec", 128) 16 case class ImmData(len: Int) extends DataConfig("int", len) 17 case class VAddrData() extends DataConfig("vaddr", 39) // Todo: associate it with the width of vaddr 18 case class MaskSrcData() extends DataConfig("masksrc", VecData().dataWidth) // 128 19 // case class MaskDstData() extends DataConfig("maskdst", VecData().dataWidth / 8) // 16 20 case class VConfigData() extends DataConfig("vconfig", log2Up(VecData().dataWidth) + 1 ) // 8 21 case class FakeIntData() extends DataConfig("fakeint", 64) 22 case class NoData() extends DataConfig("nodata", 0) 23 24 def RegSrcDataSet : Set[DataConfig] = Set(IntData(), FpData(), VecData(), MaskSrcData(), VConfigData()) 25 def IntRegSrcDataSet: Set[DataConfig] = Set(IntData()) 26 def FpRegSrcDataSet : Set[DataConfig] = Set(FpData()) 27 def VecRegSrcDataSet: Set[DataConfig] = Set(VecData()) 28 def VfRegSrcDataSet : Set[DataConfig] = Set(VecData()) 29 def V0RegSrcDataSet : Set[DataConfig] = Set(MaskSrcData()) 30 def VlRegSrcDataSet : Set[DataConfig] = Set(VConfigData()) 31 32 33 def RegDataMaxWidth : Int = RegSrcDataSet.map(_.dataWidth).max 34} 35