xref: /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/LsInfo.scala (revision e4d4d30585412eb8ac83b5c75599a348356342a2) 
1package xiangshan.backend.ctrlblock
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import xiangshan.XSBundle
7
8class DebugMdpInfo(implicit p: Parameters) extends XSBundle{
9  val ssid = UInt(SSIDWidth.W)
10  val waitAllStore = Bool()
11}
12
13class DebugLsInfo(implicit p: Parameters) extends XSBundle{
14  val s1 = new Bundle{
15    val isTlbFirstMiss = Bool() // in s1
16    val isBankConflict = Bool() // in s1
17    val isLoadToLoadForward = Bool()
18    val isReplayFast = Bool()
19  }
20  val s2 = new Bundle{
21    val isDcacheFirstMiss = Bool() // in s2 (predicted result is in s1 when using WPU, real result is in s2)
22    val isForwardFail = Bool() // in s2
23    val isReplaySlow = Bool()
24    val isLoadReplayTLBMiss = Bool()
25    val isLoadReplayCacheMiss = Bool()
26  }
27  val replayCnt = UInt(XLEN.W)
28
29  def s1SignalEnable(ena: DebugLsInfo) = {
30    when(ena.s1.isTlbFirstMiss) { s1.isTlbFirstMiss := true.B }
31    when(ena.s1.isBankConflict) { s1.isBankConflict := true.B }
32    when(ena.s1.isLoadToLoadForward) { s1.isLoadToLoadForward := true.B }
33    when(ena.s1.isReplayFast) {
34      s1.isReplayFast := true.B
35      replayCnt := replayCnt + 1.U
36    }
37  }
38
39  def s2SignalEnable(ena: DebugLsInfo) = {
40    when(ena.s2.isDcacheFirstMiss) { s2.isDcacheFirstMiss := true.B }
41    when(ena.s2.isForwardFail) { s2.isForwardFail := true.B }
42    when(ena.s2.isLoadReplayTLBMiss) { s2.isLoadReplayTLBMiss := true.B }
43    when(ena.s2.isLoadReplayCacheMiss) { s2.isLoadReplayCacheMiss := true.B }
44    when(ena.s2.isReplaySlow) {
45      s2.isReplaySlow := true.B
46      replayCnt := replayCnt + 1.U
47    }
48  }
49}
50
51object DebugLsInfo{
52  def init(implicit p: Parameters): DebugLsInfo = {
53    val lsInfo = Wire(new DebugLsInfo)
54    lsInfo.s1.isTlbFirstMiss := false.B
55    lsInfo.s1.isBankConflict := false.B
56    lsInfo.s1.isLoadToLoadForward := false.B
57    lsInfo.s1.isReplayFast := false.B
58    lsInfo.s2.isDcacheFirstMiss := false.B
59    lsInfo.s2.isForwardFail := false.B
60    lsInfo.s2.isReplaySlow := false.B
61    lsInfo.s2.isLoadReplayTLBMiss := false.B
62    lsInfo.s2.isLoadReplayCacheMiss := false.B
63    lsInfo.replayCnt := 0.U
64    lsInfo
65  }
66}
67
68class DebugLsInfoBundle(implicit p: Parameters) extends DebugLsInfo {
69  // unified processing at the end stage of load/store  ==> s2  ==> bug that will write error robIdx data
70  val s1_robIdx = UInt(log2Ceil(RobSize).W)
71  val s2_robIdx = UInt(log2Ceil(RobSize).W)
72}
73
74class DebugLSIO(implicit p: Parameters) extends XSBundle {
75  val debugLsInfo = Vec(backendParams.LduCnt + backendParams.HyuCnt + backendParams.StaCnt + backendParams.HyuCnt, Output(new DebugLsInfoBundle))
76}
77
78class LsTopdownInfo(implicit p: Parameters) extends XSBundle {
79  val s1 = new Bundle {
80    val robIdx = UInt(log2Ceil(RobSize).W)
81    val vaddr_valid = Bool()
82    val vaddr_bits = UInt(VAddrBits.W)
83  }
84  val s2 = new Bundle {
85    val robIdx = UInt(log2Ceil(RobSize).W)
86    val paddr_valid = Bool()
87    val paddr_bits = UInt(PAddrBits.W)
88    val cache_miss_en = Bool()
89    val first_real_miss = Bool()
90  }
91
92  def s1SignalEnable(ena: LsTopdownInfo) = {
93    when(ena.s1.vaddr_valid) {
94      s1.vaddr_valid := true.B
95      s1.vaddr_bits := ena.s1.vaddr_bits
96    }
97  }
98
99  def s2SignalEnable(ena: LsTopdownInfo) = {
100    when(ena.s2.paddr_valid) {
101      s2.paddr_valid := true.B
102      s2.paddr_bits := ena.s2.paddr_bits
103    }
104    when(ena.s2.cache_miss_en) {
105      s2.first_real_miss := ena.s2.first_real_miss
106    }
107  }
108}
109
110object LsTopdownInfo {
111  def init(implicit p: Parameters): LsTopdownInfo = 0.U.asTypeOf(new LsTopdownInfo)
112}