1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 6import org.chipsalliance.cde.config.Parameters 7import utility.SyncDataModuleTemplate 8import xiangshan.HasXSParameter 9import xiangshan.frontend.{FtqPtr, IfuToBackendIO} 10 11class GPAMem(implicit p: Parameters) extends LazyModule { 12 override def shouldBeInlined: Boolean = false 13 14 lazy val module = new GPAMemImp(this) 15} 16 17class GPAMemImp(override val wrapper: GPAMem)(implicit p: Parameters) extends LazyModuleImp(wrapper) with HasXSParameter { 18 val io = IO(new GPAMemIO) 19 20 private val PageOffsetWidth = 12 21 22 private val mem = Module (new SyncDataModuleTemplate(Vec(2, UInt(GPAddrBits.W)), FtqSize, numRead = 1, numWrite = 1, hasRen = true)) 23 24 mem.io.wen.head := io.fromIFU.gpaddrMem_wen 25 mem.io.waddr.head := io.fromIFU.gpaddrMem_waddr 26 mem.io.wdata.head := io.fromIFU.gpaddrMem_wdata 27 28 mem.io.ren.get.head := io.exceptionReadAddr.valid 29 mem.io.raddr.head := io.exceptionReadAddr.bits.ftqPtr.value 30 31 private val ftqOffset = RegEnable(io.exceptionReadAddr.bits.ftqOffset, io.exceptionReadAddr.valid) 32 33 private val gpa0base = mem.io.rdata.head.head 34 private val gpa1base = mem.io.rdata.head.last 35 private val gpa0 = gpa0base + Cat(ftqOffset, 0.U(instOffsetBits)) 36 private val gpa1 = gpa1base + Cat(ftqOffset, 0.U(instOffsetBits)) 37 38 private val gpa0basePage = getGPAPage(gpa0base) 39 private val gpa0page = getGPAPage(gpa0) 40 private val gpa = Mux(gpa0basePage === gpa0page, gpa0, gpa1) 41 42 io.exceptionReadData := gpa 43 44 def getGPAPage(vaddr: UInt): UInt = { 45 require(vaddr.getWidth == GPAddrBits, s"The width of gpa should be $GPAddrBits") 46 vaddr(GPAddrBits - 1, PageOffsetWidth) 47 } 48} 49 50class GPAMemIO(implicit val p: Parameters) extends Bundle with HasXSParameter { 51 val fromIFU = Flipped(new IfuToBackendIO()) 52 53 val exceptionReadAddr = Input(ValidIO(new Bundle { 54 val ftqPtr = new FtqPtr() 55 val ftqOffset = UInt(log2Up(PredictWidth).W) 56 })) 57 58 val exceptionReadData = Output(UInt(GPAddrBits.W)) 59} 60