1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 6import org.chipsalliance.cde.config.Parameters 7import utility.SyncDataModuleTemplate 8import xiangshan.HasXSParameter 9import xiangshan.frontend.{FtqPtr, IfuToBackendIO} 10 11class GPAMem(implicit p: Parameters) extends LazyModule { 12 override def shouldBeInlined: Boolean = false 13 14 lazy val module = new GPAMemImp(this) 15} 16 17class GPAMemImp(override val wrapper: GPAMem)(implicit p: Parameters) extends LazyModuleImp(wrapper) with HasXSParameter { 18 val io = IO(new GPAMemIO) 19 20 private val mem = Module (new SyncDataModuleTemplate(UInt(GPAddrBits.W), FtqSize, numRead = 1, numWrite = 1, hasRen = true)) 21 22 mem.io.wen.head := io.fromIFU.gpaddrMem_wen 23 mem.io.waddr.head := io.fromIFU.gpaddrMem_waddr 24 mem.io.wdata.head := io.fromIFU.gpaddrMem_wdata 25 26 mem.io.ren.get.head := io.exceptionReadAddr.valid 27 mem.io.raddr.head := io.exceptionReadAddr.bits.ftqPtr.value 28 29 private val ftqOffset = RegEnable(io.exceptionReadAddr.bits.ftqOffset, io.exceptionReadAddr.valid) 30 31 private val gpabase = mem.io.rdata.head 32 private val gpa = gpabase + Cat(ftqOffset, 0.U(instOffsetBits.W)) 33 34 io.exceptionReadData := gpa 35 36 def getGPAPage(vaddr: UInt): UInt = { 37 require(vaddr.getWidth == GPAddrBits, s"The width of gpa should be $GPAddrBits") 38 vaddr(GPAddrBits - 1, PageOffsetWidth) 39 } 40} 41 42class GPAMemIO(implicit val p: Parameters) extends Bundle with HasXSParameter { 43 val fromIFU = Flipped(new IfuToBackendIO()) 44 45 val exceptionReadAddr = Input(ValidIO(new Bundle { 46 val ftqPtr = new FtqPtr() 47 val ftqOffset = UInt(log2Up(PredictWidth).W) 48 })) 49 50 val exceptionReadData = Output(UInt(GPAddrBits.W)) 51} 52