1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24import yunsuan.vector.VIFuParam 25import xiangshan.backend.trace._ 26 27object Bundles { 28 /** 29 * Connect Same Name Port like bundleSource := bundleSinkBudle. 30 * 31 * There is no limit to the number of ports on both sides. 32 * 33 * Don't forget to connect the remaining ports! 34 */ 35 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 36 bundleSource.elements.foreach { case (name, data) => 37 if (bundleSink.elements.contains(name)) 38 data := bundleSink.elements(name) 39 } 40 } 41 // frontend -> backend 42 class StaticInst(implicit p: Parameters) extends XSBundle { 43 val instr = UInt(32.W) 44 val pc = UInt(VAddrBits.W) 45 val foldpc = UInt(MemPredPCWidth.W) 46 val exceptionVec = ExceptionVec() 47 val trigger = TriggerAction() 48 val preDecodeInfo = new PreDecodeInfo 49 val pred_taken = Bool() 50 val crossPageIPFFix = Bool() 51 val ftqPtr = new FtqPtr 52 val ftqOffset = UInt(log2Up(PredictWidth).W) 53 54 def connectCtrlFlow(source: CtrlFlow): Unit = { 55 this.instr := source.instr 56 this.pc := source.pc 57 this.foldpc := source.foldpc 58 this.exceptionVec := source.exceptionVec 59 this.trigger := source.trigger 60 this.preDecodeInfo := source.pd 61 this.pred_taken := source.pred_taken 62 this.crossPageIPFFix := source.crossPageIPFFix 63 this.ftqPtr := source.ftqPtr 64 this.ftqOffset := source.ftqOffset 65 } 66 } 67 68 // StaticInst --[Decode]--> DecodedInst 69 class DecodedInst(implicit p: Parameters) extends XSBundle { 70 def numSrc = backendParams.numSrc 71 // passed from StaticInst 72 val instr = UInt(32.W) 73 val pc = UInt(VAddrBits.W) 74 val foldpc = UInt(MemPredPCWidth.W) 75 val exceptionVec = ExceptionVec() 76 val trigger = TriggerAction() 77 val preDecodeInfo = new PreDecodeInfo 78 val pred_taken = Bool() 79 val crossPageIPFFix = Bool() 80 val ftqPtr = new FtqPtr 81 val ftqOffset = UInt(log2Up(PredictWidth).W) 82 // decoded 83 val srcType = Vec(numSrc, SrcType()) 84 val lsrc = Vec(numSrc, UInt(LogicRegsWidth.W)) 85 val ldest = UInt(LogicRegsWidth.W) 86 val fuType = FuType() 87 val fuOpType = FuOpType() 88 val rfWen = Bool() 89 val fpWen = Bool() 90 val vecWen = Bool() 91 val v0Wen = Bool() 92 val vlWen = Bool() 93 val isXSTrap = Bool() 94 val waitForward = Bool() // no speculate execution 95 val blockBackward = Bool() 96 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 97 val canRobCompress = Bool() 98 val selImm = SelImm() 99 val imm = UInt(ImmUnion.maxLen.W) 100 val fpu = new FPUCtrlSignals 101 val vpu = new VPUCtrlSignals 102 val vlsInstr = Bool() 103 val wfflags = Bool() 104 val isMove = Bool() 105 val uopIdx = UopIdx() 106 val uopSplitType = UopSplitType() 107 val isVset = Bool() 108 val firstUop = Bool() 109 val lastUop = Bool() 110 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 111 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 112 val commitType = CommitType() // Todo: remove it 113 val needFrm = new NeedFrmBundle 114 115 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 116 117 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 118 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 119 120 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 121 val decoder: Seq[UInt] = ListLookup( 122 inst, XDecode.decodeDefault.map(bitPatToUInt), 123 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 124 ) 125 allSignals zip decoder foreach { case (s, d) => s := d } 126 debug_fuType.foreach(_ := fuType) 127 this 128 } 129 130 def isSoftPrefetch: Bool = { 131 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 132 } 133 134 def connectStaticInst(source: StaticInst): Unit = { 135 for ((name, data) <- this.elements) { 136 if (source.elements.contains(name)) { 137 data := source.elements(name) 138 } 139 } 140 } 141 } 142 143 class TrapInstInfo(implicit p: Parameters) extends XSBundle { 144 val instr = UInt(32.W) 145 val ftqPtr = new FtqPtr 146 val ftqOffset = UInt(log2Up(PredictWidth).W) 147 148 def needFlush(ftqPtr: FtqPtr, ftqOffset: UInt): Bool ={ 149 val sameFlush = this.ftqPtr === ftqPtr && this.ftqOffset > ftqOffset 150 sameFlush || isAfter(this.ftqPtr, ftqPtr) 151 } 152 153 def fromDecodedInst(decodedInst: DecodedInst): this.type = { 154 this.instr := decodedInst.instr 155 this.ftqPtr := decodedInst.ftqPtr 156 this.ftqOffset := decodedInst.ftqOffset 157 this 158 } 159 } 160 161 // DecodedInst --[Rename]--> DynInst 162 class DynInst(implicit p: Parameters) extends XSBundle { 163 def numSrc = backendParams.numSrc 164 // passed from StaticInst 165 val instr = UInt(32.W) 166 val pc = UInt(VAddrBits.W) 167 val foldpc = UInt(MemPredPCWidth.W) 168 val exceptionVec = ExceptionVec() 169 val hasException = Bool() 170 val trigger = TriggerAction() 171 val preDecodeInfo = new PreDecodeInfo 172 val pred_taken = Bool() 173 val crossPageIPFFix = Bool() 174 val ftqPtr = new FtqPtr 175 val ftqOffset = UInt(log2Up(PredictWidth).W) 176 // passed from DecodedInst 177 val srcType = Vec(numSrc, SrcType()) 178 val ldest = UInt(LogicRegsWidth.W) 179 val fuType = FuType() 180 val fuOpType = FuOpType() 181 val rfWen = Bool() 182 val fpWen = Bool() 183 val vecWen = Bool() 184 val v0Wen = Bool() 185 val vlWen = Bool() 186 val isXSTrap = Bool() 187 val waitForward = Bool() // no speculate execution 188 val blockBackward = Bool() 189 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 190 val canRobCompress = Bool() 191 val selImm = SelImm() 192 val imm = UInt(32.W) 193 val fpu = new FPUCtrlSignals 194 val vpu = new VPUCtrlSignals 195 val vlsInstr = Bool() 196 val wfflags = Bool() 197 val isMove = Bool() 198 val uopIdx = UopIdx() 199 val isVset = Bool() 200 val firstUop = Bool() 201 val lastUop = Bool() 202 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 203 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 204 val commitType = CommitType() 205 // rename 206 val srcState = Vec(numSrc, SrcState()) 207 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 208 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 209 val pdest = UInt(PhyRegIdxWidth.W) 210 // reg cache 211 val useRegCache = Vec(backendParams.numIntRegSrc, Bool()) 212 val regCacheIdx = Vec(backendParams.numIntRegSrc, UInt(RegCacheIdxWidth.W)) 213 val robIdx = new RobPtr 214 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 215 val dirtyFs = Bool() 216 val dirtyVs = Bool() 217 val traceBlockInPipe = new TracePipe(log2Up(RenameWidth * 2)) 218 219 val eliminatedMove = Bool() 220 // Take snapshot at this CFI inst 221 val snapshot = Bool() 222 val debugInfo = new PerfDebugInfo 223 val storeSetHit = Bool() // inst has been allocated an store set 224 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 225 // Load wait is needed 226 // load inst will not be executed until former store (predicted by mdp) addr calcuated 227 val loadWaitBit = Bool() 228 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 229 // load inst will not be executed until ALL former store addr calcuated 230 val loadWaitStrict = Bool() 231 val ssid = UInt(SSIDWidth.W) 232 // Todo 233 val lqIdx = new LqPtr 234 val sqIdx = new SqPtr 235 // debug module 236 val singleStep = Bool() 237 // schedule 238 val replayInst = Bool() 239 240 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 241 242 val numLsElem = NumLsElem() 243 244 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 245 246 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 247 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 248 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 249 250 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 251 def isSvinval(flush: Bool) = FuType.isFence(fuType) && 252 Cat(Seq(FenceOpType.sfence, FenceOpType.hfence_v, FenceOpType.hfence_g).map(_ === fuOpType)).orR && !flush 253 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 254 def isNotSvinval = !FuType.isFence(fuType) 255 256 def isHls: Bool = { 257 fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType) 258 } 259 260 def srcIsReady: Vec[Bool] = { 261 VecInit(this.srcType.zip(this.srcState).map { 262 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 263 }) 264 } 265 266 def clearExceptions( 267 exceptionBits: Seq[Int] = Seq(), 268 flushPipe : Boolean = false, 269 replayInst : Boolean = false 270 ): DynInst = { 271 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 272 if (!flushPipe) { this.flushPipe := false.B } 273 if (!replayInst) { this.replayInst := false.B } 274 this 275 } 276 277 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen || v0Wen || vlWen 278 } 279 280 trait BundleSource { 281 var wakeupSource = "undefined" 282 var idx = 0 283 } 284 285 /** 286 * 287 * @param pregIdxWidth index width of preg 288 * @param exuIndices exu indices of wakeup bundle 289 */ 290 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int])(implicit p: Parameters) extends XSBundle { 291 val rfWen = Bool() 292 val fpWen = Bool() 293 val vecWen = Bool() 294 val v0Wen = Bool() 295 val vlWen = Bool() 296 val pdest = UInt(pregIdxWidth.W) 297 298 /** 299 * @param successor Seq[(psrc, srcType)] 300 * @return Seq[if wakeup psrc] 301 */ 302 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 303 successor.map { case (thatPsrc, srcType) => 304 val pdestMatch = pdest === thatPsrc 305 pdestMatch && ( 306 SrcType.isFp(srcType) && this.fpWen || 307 SrcType.isXp(srcType) && this.rfWen || 308 SrcType.isVp(srcType) && this.vecWen 309 ) && valid 310 } 311 } 312 def wakeUpV0(successor: (UInt, UInt), valid: Bool): Bool = { 313 val (thatPsrc, srcType) = successor 314 val pdestMatch = pdest === thatPsrc 315 pdestMatch && ( 316 SrcType.isV0(srcType) && this.v0Wen 317 ) && valid 318 } 319 def wakeUpVl(successor: (UInt, UInt), valid: Bool): Bool = { 320 val (thatPsrc, srcType) = successor 321 val pdestMatch = pdest === thatPsrc 322 pdestMatch && ( 323 SrcType.isVp(srcType) && this.vlWen 324 ) && valid 325 } 326 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 327 successor.map { case (thatPsrc, srcType) => 328 val pdestMatch = pdest === thatPsrc 329 pdestMatch && ( 330 SrcType.isFp(srcType) && this.fpWen || 331 SrcType.isXp(srcType) && this.rfWen || 332 SrcType.isVp(srcType) && this.vecWen 333 ) 334 } 335 } 336 def wakeUpV0FromIQ(successor: (UInt, UInt)): Bool = { 337 val (thatPsrc, srcType) = successor 338 val pdestMatch = pdest === thatPsrc 339 pdestMatch && ( 340 SrcType.isV0(srcType) && this.v0Wen 341 ) 342 } 343 def wakeUpVlFromIQ(successor: (UInt, UInt)): Bool = { 344 val (thatPsrc, srcType) = successor 345 val pdestMatch = pdest === thatPsrc 346 pdestMatch && ( 347 SrcType.isVp(srcType) && this.vlWen 348 ) 349 } 350 351 def hasOnlyOneSource: Boolean = exuIndices.size == 1 352 353 def hasMultiSources: Boolean = exuIndices.size > 1 354 355 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 356 357 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 358 359 def exuIdx: Int = { 360 require(hasOnlyOneSource) 361 this.exuIndices.head 362 } 363 } 364 365 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams)(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 366 367 } 368 369 class IssueQueueIQWakeUpBundle( 370 exuIdx: Int, 371 backendParams: BackendParams, 372 copyWakeupOut: Boolean = false, 373 copyNum: Int = 0 374 )(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 375 val loadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 376 val is0Lat = Bool() 377 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 378 val rcDest = OptionWrapper(params.needWriteRegCache, UInt(RegCacheIdxWidth.W)) 379 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 380 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 381 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 382 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 383 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 384 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 385 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 386 387 def fromExuInput(exuInput: ExuInput): Unit = { 388 this.rfWen := exuInput.rfWen.getOrElse(false.B) 389 this.fpWen := exuInput.fpWen.getOrElse(false.B) 390 this.vecWen := exuInput.vecWen.getOrElse(false.B) 391 this.v0Wen := exuInput.v0Wen.getOrElse(false.B) 392 this.vlWen := exuInput.vlWen.getOrElse(false.B) 393 this.pdest := exuInput.pdest 394 } 395 } 396 397 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 398 // vtype 399 val vill = Bool() 400 val vma = Bool() // 1: agnostic, 0: undisturbed 401 val vta = Bool() // 1: agnostic, 0: undisturbed 402 val vsew = VSew() 403 val vlmul = VLmul() // 1/8~8 --> -3~3 404 405 // spec vtype 406 val specVill = Bool() 407 val specVma = Bool() // 1: agnostic, 0: undisturbed 408 val specVta = Bool() // 1: agnostic, 0: undisturbed 409 val specVsew = VSew() 410 val specVlmul = VLmul() // 1/8~8 --> -3~3 411 412 val vm = Bool() // 0: need v0.t 413 val vstart = Vl() 414 415 // float rounding mode 416 val frm = Frm() 417 // scalar float instr and vector float reduction 418 val fpu = Fpu() 419 // vector fix int rounding mode 420 val vxrm = Vxrm() 421 // vector uop index, exclude other non-vector uop 422 val vuopIdx = UopIdx() 423 val lastUop = Bool() 424 // maybe used if data dependancy 425 val vmask = UInt(V0Data().dataWidth.W) 426 val vl = Vl() 427 428 // vector load/store 429 val nf = Nf() 430 val veew = VEew() 431 432 val isReverse = Bool() // vrsub, vrdiv 433 val isExt = Bool() 434 val isNarrow = Bool() 435 val isDstMask = Bool() // vvm, vvvm, mmm 436 val isOpMask = Bool() // vmand, vmnand 437 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 438 439 val isDependOldvd = Bool() // some instruction's computation depends on oldvd 440 val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum 441 442 def vtype: VType = { 443 val res = Wire(VType()) 444 res.illegal := this.vill 445 res.vma := this.vma 446 res.vta := this.vta 447 res.vsew := this.vsew 448 res.vlmul := this.vlmul 449 res 450 } 451 452 def specVType: VType = { 453 val res = Wire(VType()) 454 res.illegal := this.specVill 455 res.vma := this.specVma 456 res.vta := this.specVta 457 res.vsew := this.specVsew 458 res.vlmul := this.specVlmul 459 res 460 } 461 462 def vconfig: VConfig = { 463 val res = Wire(VConfig()) 464 res.vtype := this.vtype 465 res.vl := this.vl 466 res 467 } 468 469 def connectVType(source: VType): Unit = { 470 this.vill := source.illegal 471 this.vma := source.vma 472 this.vta := source.vta 473 this.vsew := source.vsew 474 this.vlmul := source.vlmul 475 } 476 } 477 478 class NeedFrmBundle(implicit p: Parameters) extends XSBundle { 479 val scalaNeedFrm = Bool() 480 val vectorNeedFrm = Bool() 481 } 482 483 // DynInst --[IssueQueue]--> DataPath 484 class IssueQueueIssueBundle( 485 iqParams: IssueBlockParams, 486 val exuParams: ExeUnitParams, 487 )(implicit 488 p: Parameters 489 ) extends XSBundle { 490 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 491 492 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 493 rfReadDataCfgSet.map((set: Set[DataConfig]) => 494 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 495 ) 496 )) 497 498 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 499 val rcIdx = OptionWrapper(exuParams.needReadRegCache, Vec(exuParams.numRegSrc, UInt(RegCacheIdxWidth.W))) // used to select regcache data 500 val immType = SelImm() // used to select imm extractor 501 val common = new ExuInput(exuParams) 502 val addrOH = UInt(iqParams.numEntries.W) 503 504 def exuIdx = exuParams.exuIdx 505 def getSource: SchedulerType = exuParams.getWBSource 506 507 def getRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 508 rf.zip(srcType).map { 509 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 510 makeValid(issueValid, rfRd.head) 511 }.toSeq 512 } 513 } 514 515 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 516 val issueQueueParams = this.params 517 val og0resp = Valid(new EntryDeqRespBundle) 518 val og1resp = Valid(new EntryDeqRespBundle) 519 } 520 521 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 522 private val intCertainLat = params.intLatencyCertain 523 private val fpCertainLat = params.fpLatencyCertain 524 private val vfCertainLat = params.vfLatencyCertain 525 private val v0CertainLat = params.v0LatencyCertain 526 private val vlCertainLat = params.vlLatencyCertain 527 private val intLat = params.intLatencyValMax 528 private val fpLat = params.fpLatencyValMax 529 private val vfLat = params.vfLatencyValMax 530 private val v0Lat = params.v0LatencyValMax 531 private val vlLat = params.vlLatencyValMax 532 533 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 534 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 535 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 536 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 537 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 538 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 539 val fpDeqRespSet = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 540 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 541 val v0DeqRespSet = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 542 val vlDeqRespSet = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 543 } 544 545 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 546 private val intCertainLat = params.intLatencyCertain 547 private val fpCertainLat = params.fpLatencyCertain 548 private val vfCertainLat = params.vfLatencyCertain 549 private val v0CertainLat = params.v0LatencyCertain 550 private val vlCertainLat = params.vlLatencyCertain 551 private val intLat = params.intLatencyValMax 552 private val fpLat = params.fpLatencyValMax 553 private val vfLat = params.vfLatencyValMax 554 private val v0Lat = params.v0LatencyValMax 555 private val vlLat = params.vlLatencyValMax 556 557 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 558 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 559 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 560 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 561 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 562 } 563 564 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 565 private val intCertainLat = params.intLatencyCertain 566 private val fpCertainLat = params.fpLatencyCertain 567 private val vfCertainLat = params.vfLatencyCertain 568 private val v0CertainLat = params.v0LatencyCertain 569 private val vlCertainLat = params.vlLatencyCertain 570 571 val intConflict = OptionWrapper(intCertainLat, Bool()) 572 val fpConflict = OptionWrapper(fpCertainLat, Bool()) 573 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 574 val v0Conflict = OptionWrapper(v0CertainLat, Bool()) 575 val vlConflict = OptionWrapper(vlCertainLat, Bool()) 576 } 577 578 class ImmInfo extends Bundle { 579 val imm = UInt(32.W) 580 val immType = SelImm() 581 } 582 583 // DataPath --[ExuInput]--> Exu 584 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 585 val fuType = FuType() 586 val fuOpType = FuOpType() 587 val src = Vec(params.numRegSrc, UInt(params.srcDataBitsMax.W)) 588 val imm = UInt(32.W) 589 val robIdx = new RobPtr 590 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 591 val isFirstIssue = Bool() // Only used by store yet 592 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 593 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 594 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 595 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 596 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 597 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 598 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 599 val pdest = UInt(params.wbPregIdxWidth.W) 600 val rfWen = if (params.needIntWen) Some(Bool()) else None 601 val fpWen = if (params.needFpWen) Some(Bool()) else None 602 val vecWen = if (params.needVecWen) Some(Bool()) else None 603 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 604 val vlWen = if (params.needVlWen) Some(Bool()) else None 605 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 606 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 607 val flushPipe = if (params.flushPipe) Some(Bool()) else None 608 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 609 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 610 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 611 Some(new FtqPtr) else None 612 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 613 Some(UInt(log2Up(PredictWidth).W)) else None 614 val predictInfo = if (params.needPdInfo) Some(new Bundle { 615 val target = UInt(VAddrData().dataWidth.W) 616 val taken = Bool() 617 }) else None 618 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 619 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 620 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 621 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 622 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 623 // only vector load store need 624 val numLsElem = OptionWrapper(params.hasVecLsFu, NumLsElem()) 625 626 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 627 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 628 val dataSources = Vec(params.numRegSrc, DataSource()) 629 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 630 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 631 val loadDependency = OptionWrapper(params.needLoadDependency, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 632 633 val perfDebugInfo = new PerfDebugInfo() 634 635 def exuIdx = this.params.exuIdx 636 637 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 638 if (params.isIQWakeUpSink) { 639 require( 640 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 641 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 642 ) 643 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 644 case(exuOH: Vec[Bool], srcTimer: UInt) => 645 (exuOH.asUInt & og0CancelOH).orR && srcTimer === 1.U 646 }.reduce(_ | _) 647 l1Cancel 648 } else { 649 false.B 650 } 651 } 652 653 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 654 // src is assigned to rfReadData 655 this.fuType := source.common.fuType 656 this.fuOpType := source.common.fuOpType 657 this.imm := source.common.imm 658 this.robIdx := source.common.robIdx 659 this.pdest := source.common.pdest 660 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 661 this.iqIdx := source.common.iqIdx // Only used by mem feedback 662 this.dataSources := source.common.dataSources 663 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 664 this.rfWen .foreach(_ := source.common.rfWen.get) 665 this.fpWen .foreach(_ := source.common.fpWen.get) 666 this.vecWen .foreach(_ := source.common.vecWen.get) 667 this.v0Wen .foreach(_ := source.common.v0Wen.get) 668 this.vlWen .foreach(_ := source.common.vlWen.get) 669 this.fpu .foreach(_ := source.common.fpu.get) 670 this.vpu .foreach(_ := source.common.vpu.get) 671 this.flushPipe .foreach(_ := source.common.flushPipe.get) 672 this.pc .foreach(_ := source.common.pc.get) 673 this.preDecode .foreach(_ := source.common.preDecode.get) 674 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 675 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 676 this.predictInfo .foreach(_ := source.common.predictInfo.get) 677 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 678 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 679 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 680 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 681 this.ssid .foreach(_ := source.common.ssid.get) 682 this.lqIdx .foreach(_ := source.common.lqIdx.get) 683 this.sqIdx .foreach(_ := source.common.sqIdx.get) 684 this.numLsElem .foreach(_ := source.common.numLsElem.get) 685 this.srcTimer .foreach(_ := source.common.srcTimer.get) 686 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 687 } 688 } 689 690 // ExuInput --[FuncUnit]--> ExuOutput 691 class ExuOutput( 692 val params: ExeUnitParams, 693 )(implicit 694 val p: Parameters 695 ) extends Bundle with BundleSource with HasXSParameter { 696 val data = Vec(params.wbPathNum, UInt(params.destDataBitsMax.W)) 697 val pdest = UInt(params.wbPregIdxWidth.W) 698 val robIdx = new RobPtr 699 val intWen = if (params.needIntWen) Some(Bool()) else None 700 val fpWen = if (params.needFpWen) Some(Bool()) else None 701 val vecWen = if (params.needVecWen) Some(Bool()) else None 702 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 703 val vlWen = if (params.needVlWen) Some(Bool()) else None 704 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 705 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 706 val wflags = if (params.writeFflags) Some(Bool()) else None 707 val vxsat = if (params.writeVxsat) Some(Bool()) else None 708 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 709 val flushPipe = if (params.flushPipe) Some(Bool()) else None 710 val replay = if (params.replayInst) Some(Bool()) else None 711 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 712 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 713 Some(new SqPtr()) else None 714 val trigger = if (params.trigger) Some(TriggerAction()) else None 715 // uop info 716 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 717 // vldu used only 718 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 719 val vpu = new VPUCtrlSignals 720 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 721 val vdIdx = UInt(3.W) 722 val vdIdxInField = UInt(3.W) 723 val isIndexed = Bool() 724 val isMasked = Bool() 725 }) 726 val debug = new DebugBundle 727 val debugInfo = new PerfDebugInfo 728 } 729 730 // ExuOutput + DynInst --> WriteBackBundle 731 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 732 val rfWen = Bool() 733 val fpWen = Bool() 734 val vecWen = Bool() 735 val v0Wen = Bool() 736 val vlWen = Bool() 737 val pdest = UInt(params.pregIdxWidth(backendParams).W) 738 val data = UInt(params.dataWidth.W) 739 val robIdx = new RobPtr()(p) 740 val flushPipe = Bool() 741 val replayInst = Bool() 742 val redirect = ValidIO(new Redirect) 743 val fflags = UInt(5.W) 744 val vxsat = Bool() 745 val exceptionVec = ExceptionVec() 746 val debug = new DebugBundle 747 val debugInfo = new PerfDebugInfo 748 749 this.wakeupSource = s"WB(${params.toString})" 750 751 def fromExuOutput(source: ExuOutput, wbType: String) = { 752 val typeMap = Map("int" -> 0, "fp" -> 1, "vf" -> 2, "v0" -> 3, "vl" -> 4) 753 this.rfWen := source.intWen.getOrElse(false.B) 754 this.fpWen := source.fpWen.getOrElse(false.B) 755 this.vecWen := source.vecWen.getOrElse(false.B) 756 this.v0Wen := source.v0Wen.getOrElse(false.B) 757 this.vlWen := source.vlWen.getOrElse(false.B) 758 this.pdest := source.pdest 759 this.data := source.data(source.params.wbIndex(typeMap(wbType))) 760 this.robIdx := source.robIdx 761 this.flushPipe := source.flushPipe.getOrElse(false.B) 762 this.replayInst := source.replay.getOrElse(false.B) 763 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 764 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 765 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 766 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 767 this.debug := source.debug 768 this.debugInfo := source.debugInfo 769 } 770 771 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 772 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 773 rfWrite.wen := this.rfWen && fire 774 rfWrite.addr := this.pdest 775 rfWrite.data := this.data 776 rfWrite.intWen := this.rfWen 777 rfWrite.fpWen := false.B 778 rfWrite.vecWen := false.B 779 rfWrite.v0Wen := false.B 780 rfWrite.vlWen := false.B 781 rfWrite 782 } 783 784 def asFpRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 785 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(FpData()).addrWidth))) 786 rfWrite.wen := this.fpWen && fire 787 rfWrite.addr := this.pdest 788 rfWrite.data := this.data 789 rfWrite.intWen := false.B 790 rfWrite.fpWen := this.fpWen 791 rfWrite.vecWen := false.B 792 rfWrite.v0Wen := false.B 793 rfWrite.vlWen := false.B 794 rfWrite 795 } 796 797 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 798 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 799 rfWrite.wen := this.vecWen && fire 800 rfWrite.addr := this.pdest 801 rfWrite.data := this.data 802 rfWrite.intWen := false.B 803 rfWrite.fpWen := false.B 804 rfWrite.vecWen := this.vecWen 805 rfWrite.v0Wen := false.B 806 rfWrite.vlWen := false.B 807 rfWrite 808 } 809 810 def asV0RfWriteBundle(fire: Bool): RfWritePortWithConfig = { 811 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(V0Data()).addrWidth))) 812 rfWrite.wen := this.v0Wen && fire 813 rfWrite.addr := this.pdest 814 rfWrite.data := this.data 815 rfWrite.intWen := false.B 816 rfWrite.fpWen := false.B 817 rfWrite.vecWen := false.B 818 rfWrite.v0Wen := this.v0Wen 819 rfWrite.vlWen := false.B 820 rfWrite 821 } 822 823 def asVlRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 824 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VlData()).addrWidth))) 825 rfWrite.wen := this.vlWen && fire 826 rfWrite.addr := this.pdest 827 rfWrite.data := this.data 828 rfWrite.intWen := false.B 829 rfWrite.fpWen := false.B 830 rfWrite.vecWen := false.B 831 rfWrite.v0Wen := false.B 832 rfWrite.vlWen := this.vlWen 833 rfWrite 834 } 835 } 836 837 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 838 // / 839 // [IssueQueue]--> ExuInput -- 840 class ExuBypassBundle( 841 val params: ExeUnitParams, 842 )(implicit p: Parameters) extends XSBundle { 843 val intWen = Bool() 844 val data = UInt(params.destDataBitsMax.W) 845 val pdest = UInt(params.wbPregIdxWidth.W) 846 } 847 848 class ExceptionInfo(implicit p: Parameters) extends XSBundle { 849 val pc = UInt(VAddrData().dataWidth.W) 850 val instr = UInt(32.W) 851 val commitType = CommitType() 852 val exceptionVec = ExceptionVec() 853 val gpaddr = UInt(GPAddrBits.W) 854 val singleStep = Bool() 855 val crossPageIPFFix = Bool() 856 val isInterrupt = Bool() 857 val isHls = Bool() 858 val vls = Bool() 859 val trigger = TriggerAction() 860 } 861 862 object UopIdx { 863 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 864 } 865 866 object FuLatency { 867 def apply(): UInt = UInt(width.W) 868 869 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 870 } 871 872 object ExuOH { 873 def apply(exuNum: Int): UInt = UInt(exuNum.W) 874 875 def apply()(implicit p: Parameters): UInt = UInt(width.W) 876 877 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 878 } 879 880 object ExuVec { 881 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 882 883 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 884 885 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 886 } 887 888 class CancelSignal(implicit p: Parameters) extends XSBundle { 889 val rfWen = Bool() 890 val fpWen = Bool() 891 val vecWen = Bool() 892 val v0Wen = Bool() 893 val vlWen = Bool() 894 val pdest = UInt(PhyRegIdxWidth.W) 895 } 896 897 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 898 val uop = new DynInst 899 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 900 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 901 val isFirstIssue = Bool() 902 val flowNum = OptionWrapper(isVector, NumLsElem()) 903 904 def src_rs1 = src(0) 905 def src_stride = src(1) 906 def src_vs3 = src(2) 907 def src_mask = if (isVector) src(3) else 0.U 908 def src_vl = if (isVector) src(4) else 0.U 909 } 910 911 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 912 val uop = new DynInst 913 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 914 val mask = if (isVector) Some(UInt(VLEN.W)) else None 915 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 916 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 917 val debug = new DebugBundle 918 919 def isVls = FuType.isVls(uop.fuType) 920 } 921 922 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 923 val uop = new DynInst 924 val flag = UInt(1.W) 925 } 926 927 object LoadShouldCancel { 928 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 929 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(0)}.reduce(_ || _)) 930 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 931 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 932 } 933 } 934} 935