1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24import yunsuan.vector.VIFuParam 25 26object Bundles { 27 /** 28 * Connect Same Name Port like bundleSource := bundleSinkBudle. 29 * 30 * There is no limit to the number of ports on both sides. 31 * 32 * Don't forget to connect the remaining ports! 33 */ 34 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 35 bundleSource.elements.foreach { case (name, data) => 36 if (bundleSink.elements.contains(name)) 37 data := bundleSink.elements(name) 38 } 39 } 40 // frontend -> backend 41 class StaticInst(implicit p: Parameters) extends XSBundle { 42 val instr = UInt(32.W) 43 val pc = UInt(VAddrBits.W) 44 val foldpc = UInt(MemPredPCWidth.W) 45 val exceptionVec = ExceptionVec() 46 val trigger = new TriggerCf 47 val preDecodeInfo = new PreDecodeInfo 48 val pred_taken = Bool() 49 val crossPageIPFFix = Bool() 50 val ftqPtr = new FtqPtr 51 val ftqOffset = UInt(log2Up(PredictWidth).W) 52 53 def connectCtrlFlow(source: CtrlFlow): Unit = { 54 this.instr := source.instr 55 this.pc := source.pc 56 this.foldpc := source.foldpc 57 this.exceptionVec := source.exceptionVec 58 this.trigger := source.trigger 59 this.preDecodeInfo := source.pd 60 this.pred_taken := source.pred_taken 61 this.crossPageIPFFix := source.crossPageIPFFix 62 this.ftqPtr := source.ftqPtr 63 this.ftqOffset := source.ftqOffset 64 } 65 } 66 67 // StaticInst --[Decode]--> DecodedInst 68 class DecodedInst(implicit p: Parameters) extends XSBundle { 69 def numSrc = backendParams.numSrc 70 // passed from StaticInst 71 val instr = UInt(32.W) 72 val pc = UInt(VAddrBits.W) 73 val foldpc = UInt(MemPredPCWidth.W) 74 val exceptionVec = ExceptionVec() 75 val trigger = new TriggerCf 76 val preDecodeInfo = new PreDecodeInfo 77 val pred_taken = Bool() 78 val crossPageIPFFix = Bool() 79 val ftqPtr = new FtqPtr 80 val ftqOffset = UInt(log2Up(PredictWidth).W) 81 // decoded 82 val srcType = Vec(numSrc, SrcType()) 83 val lsrc = Vec(numSrc, UInt(LogicRegsWidth.W)) 84 val ldest = UInt(LogicRegsWidth.W) 85 val fuType = FuType() 86 val fuOpType = FuOpType() 87 val rfWen = Bool() 88 val fpWen = Bool() 89 val vecWen = Bool() 90 val v0Wen = Bool() 91 val vlWen = Bool() 92 val isXSTrap = Bool() 93 val waitForward = Bool() // no speculate execution 94 val blockBackward = Bool() 95 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 96 val canRobCompress = Bool() 97 val selImm = SelImm() 98 val imm = UInt(ImmUnion.maxLen.W) 99 val fpu = new FPUCtrlSignals 100 val vpu = new VPUCtrlSignals 101 val vlsInstr = Bool() 102 val wfflags = Bool() 103 val isMove = Bool() 104 val uopIdx = UopIdx() 105 val uopSplitType = UopSplitType() 106 val isVset = Bool() 107 val firstUop = Bool() 108 val lastUop = Bool() 109 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 110 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 111 val commitType = CommitType() // Todo: remove it 112 113 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 114 115 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 116 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 117 118 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 119 val decoder: Seq[UInt] = ListLookup( 120 inst, XDecode.decodeDefault.map(bitPatToUInt), 121 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 122 ) 123 allSignals zip decoder foreach { case (s, d) => s := d } 124 debug_fuType.foreach(_ := fuType) 125 this 126 } 127 128 def isSoftPrefetch: Bool = { 129 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 130 } 131 132 def connectStaticInst(source: StaticInst): Unit = { 133 for ((name, data) <- this.elements) { 134 if (source.elements.contains(name)) { 135 data := source.elements(name) 136 } 137 } 138 } 139 } 140 141 // DecodedInst --[Rename]--> DynInst 142 class DynInst(implicit p: Parameters) extends XSBundle { 143 def numSrc = backendParams.numSrc 144 // passed from StaticInst 145 val instr = UInt(32.W) 146 val pc = UInt(VAddrBits.W) 147 val foldpc = UInt(MemPredPCWidth.W) 148 val exceptionVec = ExceptionVec() 149 val hasException = Bool() 150 val trigger = new TriggerCf 151 val preDecodeInfo = new PreDecodeInfo 152 val pred_taken = Bool() 153 val crossPageIPFFix = Bool() 154 val ftqPtr = new FtqPtr 155 val ftqOffset = UInt(log2Up(PredictWidth).W) 156 // passed from DecodedInst 157 val srcType = Vec(numSrc, SrcType()) 158 val ldest = UInt(LogicRegsWidth.W) 159 val fuType = FuType() 160 val fuOpType = FuOpType() 161 val rfWen = Bool() 162 val fpWen = Bool() 163 val vecWen = Bool() 164 val v0Wen = Bool() 165 val vlWen = Bool() 166 val isXSTrap = Bool() 167 val waitForward = Bool() // no speculate execution 168 val blockBackward = Bool() 169 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 170 val canRobCompress = Bool() 171 val selImm = SelImm() 172 val imm = UInt(32.W) 173 val fpu = new FPUCtrlSignals 174 val vpu = new VPUCtrlSignals 175 val vlsInstr = Bool() 176 val wfflags = Bool() 177 val isMove = Bool() 178 val uopIdx = UopIdx() 179 val isVset = Bool() 180 val firstUop = Bool() 181 val lastUop = Bool() 182 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 183 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 184 val commitType = CommitType() 185 // rename 186 val srcState = Vec(numSrc, SrcState()) 187 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 188 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 189 val pdest = UInt(PhyRegIdxWidth.W) 190 // reg cache 191 val useRegCache = Vec(backendParams.numIntRegSrc, Bool()) 192 val regCacheIdx = Vec(backendParams.numIntRegSrc, UInt(RegCacheIdxWidth.W)) 193 val robIdx = new RobPtr 194 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 195 val dirtyFs = Bool() 196 val dirtyVs = Bool() 197 198 val eliminatedMove = Bool() 199 // Take snapshot at this CFI inst 200 val snapshot = Bool() 201 val debugInfo = new PerfDebugInfo 202 val storeSetHit = Bool() // inst has been allocated an store set 203 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 204 // Load wait is needed 205 // load inst will not be executed until former store (predicted by mdp) addr calcuated 206 val loadWaitBit = Bool() 207 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 208 // load inst will not be executed until ALL former store addr calcuated 209 val loadWaitStrict = Bool() 210 val ssid = UInt(SSIDWidth.W) 211 // Todo 212 val lqIdx = new LqPtr 213 val sqIdx = new SqPtr 214 // debug module 215 val singleStep = Bool() 216 // schedule 217 val replayInst = Bool() 218 219 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 220 221 val numLsElem = NumLsElem() 222 223 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 224 225 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 226 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 227 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 228 229 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 230 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 231 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 232 def isNotSvinval = !FuType.isFence(fuType) 233 234 def isHls: Bool = { 235 fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType) 236 } 237 238 def srcIsReady: Vec[Bool] = { 239 VecInit(this.srcType.zip(this.srcState).map { 240 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 241 }) 242 } 243 244 def clearExceptions( 245 exceptionBits: Seq[Int] = Seq(), 246 flushPipe : Boolean = false, 247 replayInst : Boolean = false 248 ): DynInst = { 249 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 250 if (!flushPipe) { this.flushPipe := false.B } 251 if (!replayInst) { this.replayInst := false.B } 252 this 253 } 254 255 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen || v0Wen || vlWen 256 } 257 258 trait BundleSource { 259 var wakeupSource = "undefined" 260 var idx = 0 261 } 262 263 /** 264 * 265 * @param pregIdxWidth index width of preg 266 * @param exuIndices exu indices of wakeup bundle 267 */ 268 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int])(implicit p: Parameters) extends XSBundle { 269 val rfWen = Bool() 270 val fpWen = Bool() 271 val vecWen = Bool() 272 val v0Wen = Bool() 273 val vlWen = Bool() 274 val pdest = UInt(pregIdxWidth.W) 275 276 /** 277 * @param successor Seq[(psrc, srcType)] 278 * @return Seq[if wakeup psrc] 279 */ 280 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 281 successor.map { case (thatPsrc, srcType) => 282 val pdestMatch = pdest === thatPsrc 283 pdestMatch && ( 284 SrcType.isFp(srcType) && this.fpWen || 285 SrcType.isXp(srcType) && this.rfWen || 286 SrcType.isVp(srcType) && this.vecWen 287 ) && valid 288 } 289 } 290 def wakeUpV0(successor: (UInt, UInt), valid: Bool): Bool = { 291 val (thatPsrc, srcType) = successor 292 val pdestMatch = pdest === thatPsrc 293 pdestMatch && ( 294 SrcType.isV0(srcType) && this.v0Wen 295 ) && valid 296 } 297 def wakeUpVl(successor: (UInt, UInt), valid: Bool): Bool = { 298 val (thatPsrc, srcType) = successor 299 val pdestMatch = pdest === thatPsrc 300 pdestMatch && ( 301 SrcType.isVp(srcType) && this.vlWen 302 ) && valid 303 } 304 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 305 successor.map { case (thatPsrc, srcType) => 306 val pdestMatch = pdest === thatPsrc 307 pdestMatch && ( 308 SrcType.isFp(srcType) && this.fpWen || 309 SrcType.isXp(srcType) && this.rfWen || 310 SrcType.isVp(srcType) && this.vecWen 311 ) 312 } 313 } 314 def wakeUpV0FromIQ(successor: (UInt, UInt)): Bool = { 315 val (thatPsrc, srcType) = successor 316 val pdestMatch = pdest === thatPsrc 317 pdestMatch && ( 318 SrcType.isV0(srcType) && this.v0Wen 319 ) 320 } 321 def wakeUpVlFromIQ(successor: (UInt, UInt)): Bool = { 322 val (thatPsrc, srcType) = successor 323 val pdestMatch = pdest === thatPsrc 324 pdestMatch && ( 325 SrcType.isVp(srcType) && this.vlWen 326 ) 327 } 328 329 def hasOnlyOneSource: Boolean = exuIndices.size == 1 330 331 def hasMultiSources: Boolean = exuIndices.size > 1 332 333 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 334 335 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 336 337 def exuIdx: Int = { 338 require(hasOnlyOneSource) 339 this.exuIndices.head 340 } 341 } 342 343 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams)(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 344 345 } 346 347 class IssueQueueIQWakeUpBundle( 348 exuIdx: Int, 349 backendParams: BackendParams, 350 copyWakeupOut: Boolean = false, 351 copyNum: Int = 0 352 )(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 353 val loadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 354 val is0Lat = Bool() 355 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 356 val rcDest = OptionWrapper(params.needWriteRegCache, UInt(RegCacheIdxWidth.W)) 357 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 358 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 359 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 360 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 361 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 362 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 363 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 364 365 def fromExuInput(exuInput: ExuInput): Unit = { 366 this.rfWen := exuInput.rfWen.getOrElse(false.B) 367 this.fpWen := exuInput.fpWen.getOrElse(false.B) 368 this.vecWen := exuInput.vecWen.getOrElse(false.B) 369 this.v0Wen := exuInput.v0Wen.getOrElse(false.B) 370 this.vlWen := exuInput.vlWen.getOrElse(false.B) 371 this.pdest := exuInput.pdest 372 } 373 } 374 375 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 376 // vtype 377 val vill = Bool() 378 val vma = Bool() // 1: agnostic, 0: undisturbed 379 val vta = Bool() // 1: agnostic, 0: undisturbed 380 val vsew = VSew() 381 val vlmul = VLmul() // 1/8~8 --> -3~3 382 383 // spec vtype 384 val specVill = Bool() 385 val specVma = Bool() // 1: agnostic, 0: undisturbed 386 val specVta = Bool() // 1: agnostic, 0: undisturbed 387 val specVsew = VSew() 388 val specVlmul = VLmul() // 1/8~8 --> -3~3 389 390 val vm = Bool() // 0: need v0.t 391 val vstart = Vl() 392 393 // float rounding mode 394 val frm = Frm() 395 // scalar float instr and vector float reduction 396 val fpu = Fpu() 397 // vector fix int rounding mode 398 val vxrm = Vxrm() 399 // vector uop index, exclude other non-vector uop 400 val vuopIdx = UopIdx() 401 val lastUop = Bool() 402 // maybe used if data dependancy 403 val vmask = UInt(V0Data().dataWidth.W) 404 val vl = Vl() 405 406 // vector load/store 407 val nf = Nf() 408 val veew = VEew() 409 410 val isReverse = Bool() // vrsub, vrdiv 411 val isExt = Bool() 412 val isNarrow = Bool() 413 val isDstMask = Bool() // vvm, vvvm, mmm 414 val isOpMask = Bool() // vmand, vmnand 415 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 416 417 val isDependOldvd = Bool() // some instruction's computation depends on oldvd 418 val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum 419 420 def vtype: VType = { 421 val res = Wire(VType()) 422 res.illegal := this.vill 423 res.vma := this.vma 424 res.vta := this.vta 425 res.vsew := this.vsew 426 res.vlmul := this.vlmul 427 res 428 } 429 430 def specVType: VType = { 431 val res = Wire(VType()) 432 res.illegal := this.specVill 433 res.vma := this.specVma 434 res.vta := this.specVta 435 res.vsew := this.specVsew 436 res.vlmul := this.specVlmul 437 res 438 } 439 440 def vconfig: VConfig = { 441 val res = Wire(VConfig()) 442 res.vtype := this.vtype 443 res.vl := this.vl 444 res 445 } 446 447 def connectVType(source: VType): Unit = { 448 this.vill := source.illegal 449 this.vma := source.vma 450 this.vta := source.vta 451 this.vsew := source.vsew 452 this.vlmul := source.vlmul 453 } 454 } 455 456 // DynInst --[IssueQueue]--> DataPath 457 class IssueQueueIssueBundle( 458 iqParams: IssueBlockParams, 459 val exuParams: ExeUnitParams, 460 )(implicit 461 p: Parameters 462 ) extends XSBundle { 463 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 464 465 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 466 rfReadDataCfgSet.map((set: Set[DataConfig]) => 467 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 468 ) 469 )) 470 471 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 472 val rcIdx = OptionWrapper(exuParams.needReadRegCache, Vec(exuParams.numRegSrc, UInt(RegCacheIdxWidth.W))) // used to select regcache data 473 val immType = SelImm() // used to select imm extractor 474 val common = new ExuInput(exuParams) 475 val addrOH = UInt(iqParams.numEntries.W) 476 477 def exuIdx = exuParams.exuIdx 478 def getSource: SchedulerType = exuParams.getWBSource 479 480 def getRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 481 rf.zip(srcType).map { 482 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 483 makeValid(issueValid, rfRd.head) 484 }.toSeq 485 } 486 } 487 488 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 489 val issueQueueParams = this.params 490 val og0resp = Valid(new EntryDeqRespBundle) 491 val og1resp = Valid(new EntryDeqRespBundle) 492 } 493 494 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 495 private val intCertainLat = params.intLatencyCertain 496 private val fpCertainLat = params.fpLatencyCertain 497 private val vfCertainLat = params.vfLatencyCertain 498 private val v0CertainLat = params.v0LatencyCertain 499 private val vlCertainLat = params.vlLatencyCertain 500 private val intLat = params.intLatencyValMax 501 private val fpLat = params.fpLatencyValMax 502 private val vfLat = params.vfLatencyValMax 503 private val v0Lat = params.v0LatencyValMax 504 private val vlLat = params.vlLatencyValMax 505 506 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 507 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 508 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 509 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 510 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 511 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 512 val fpDeqRespSet = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 513 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 514 val v0DeqRespSet = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 515 val vlDeqRespSet = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 516 } 517 518 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 519 private val intCertainLat = params.intLatencyCertain 520 private val fpCertainLat = params.fpLatencyCertain 521 private val vfCertainLat = params.vfLatencyCertain 522 private val v0CertainLat = params.v0LatencyCertain 523 private val vlCertainLat = params.vlLatencyCertain 524 private val intLat = params.intLatencyValMax 525 private val fpLat = params.fpLatencyValMax 526 private val vfLat = params.vfLatencyValMax 527 private val v0Lat = params.v0LatencyValMax 528 private val vlLat = params.vlLatencyValMax 529 530 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 531 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 532 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 533 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 534 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 535 } 536 537 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 538 private val intCertainLat = params.intLatencyCertain 539 private val fpCertainLat = params.fpLatencyCertain 540 private val vfCertainLat = params.vfLatencyCertain 541 private val v0CertainLat = params.v0LatencyCertain 542 private val vlCertainLat = params.vlLatencyCertain 543 544 val intConflict = OptionWrapper(intCertainLat, Bool()) 545 val fpConflict = OptionWrapper(fpCertainLat, Bool()) 546 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 547 val v0Conflict = OptionWrapper(v0CertainLat, Bool()) 548 val vlConflict = OptionWrapper(vlCertainLat, Bool()) 549 } 550 551 class ImmInfo extends Bundle { 552 val imm = UInt(32.W) 553 val immType = SelImm() 554 } 555 556 // DataPath --[ExuInput]--> Exu 557 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 558 val fuType = FuType() 559 val fuOpType = FuOpType() 560 val src = Vec(params.numRegSrc, UInt(params.srcDataBitsMax.W)) 561 val imm = UInt(32.W) 562 val robIdx = new RobPtr 563 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 564 val isFirstIssue = Bool() // Only used by store yet 565 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 566 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 567 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 568 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 569 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 570 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 571 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 572 val pdest = UInt(params.wbPregIdxWidth.W) 573 val rfWen = if (params.needIntWen) Some(Bool()) else None 574 val fpWen = if (params.needFpWen) Some(Bool()) else None 575 val vecWen = if (params.needVecWen) Some(Bool()) else None 576 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 577 val vlWen = if (params.needVlWen) Some(Bool()) else None 578 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 579 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 580 val flushPipe = if (params.flushPipe) Some(Bool()) else None 581 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 582 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 583 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 584 Some(new FtqPtr) else None 585 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 586 Some(UInt(log2Up(PredictWidth).W)) else None 587 val predictInfo = if (params.needPdInfo) Some(new Bundle { 588 val target = UInt(VAddrData().dataWidth.W) 589 val taken = Bool() 590 }) else None 591 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 592 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 593 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 594 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 595 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 596 // only vector load store need 597 val numLsElem = OptionWrapper(params.hasVecLsFu, NumLsElem()) 598 599 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 600 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 601 val dataSources = Vec(params.numRegSrc, DataSource()) 602 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 603 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 604 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 605 606 val perfDebugInfo = new PerfDebugInfo() 607 608 def exuIdx = this.params.exuIdx 609 610 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 611 if (params.isIQWakeUpSink) { 612 require( 613 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 614 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 615 ) 616 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 617 case(exuOH: Vec[Bool], srcTimer: UInt) => 618 (exuOH.asUInt & og0CancelOH).orR && srcTimer === 1.U 619 }.reduce(_ | _) 620 l1Cancel 621 } else { 622 false.B 623 } 624 } 625 626 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 627 // src is assigned to rfReadData 628 this.fuType := source.common.fuType 629 this.fuOpType := source.common.fuOpType 630 this.imm := source.common.imm 631 this.robIdx := source.common.robIdx 632 this.pdest := source.common.pdest 633 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 634 this.iqIdx := source.common.iqIdx // Only used by mem feedback 635 this.dataSources := source.common.dataSources 636 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 637 this.rfWen .foreach(_ := source.common.rfWen.get) 638 this.fpWen .foreach(_ := source.common.fpWen.get) 639 this.vecWen .foreach(_ := source.common.vecWen.get) 640 this.v0Wen .foreach(_ := source.common.v0Wen.get) 641 this.vlWen .foreach(_ := source.common.vlWen.get) 642 this.fpu .foreach(_ := source.common.fpu.get) 643 this.vpu .foreach(_ := source.common.vpu.get) 644 this.flushPipe .foreach(_ := source.common.flushPipe.get) 645 this.pc .foreach(_ := source.common.pc.get) 646 this.preDecode .foreach(_ := source.common.preDecode.get) 647 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 648 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 649 this.predictInfo .foreach(_ := source.common.predictInfo.get) 650 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 651 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 652 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 653 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 654 this.ssid .foreach(_ := source.common.ssid.get) 655 this.lqIdx .foreach(_ := source.common.lqIdx.get) 656 this.sqIdx .foreach(_ := source.common.sqIdx.get) 657 this.numLsElem .foreach(_ := source.common.numLsElem.get) 658 this.srcTimer .foreach(_ := source.common.srcTimer.get) 659 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 660 } 661 } 662 663 // ExuInput --[FuncUnit]--> ExuOutput 664 class ExuOutput( 665 val params: ExeUnitParams, 666 )(implicit 667 val p: Parameters 668 ) extends Bundle with BundleSource with HasXSParameter { 669 val data = Vec(params.wbPathNum, UInt(params.destDataBitsMax.W)) 670 val pdest = UInt(params.wbPregIdxWidth.W) 671 val robIdx = new RobPtr 672 val intWen = if (params.needIntWen) Some(Bool()) else None 673 val fpWen = if (params.needFpWen) Some(Bool()) else None 674 val vecWen = if (params.needVecWen) Some(Bool()) else None 675 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 676 val vlWen = if (params.needVlWen) Some(Bool()) else None 677 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 678 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 679 val wflags = if (params.writeFflags) Some(Bool()) else None 680 val vxsat = if (params.writeVxsat) Some(Bool()) else None 681 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 682 val flushPipe = if (params.flushPipe) Some(Bool()) else None 683 val replay = if (params.replayInst) Some(Bool()) else None 684 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 685 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 686 Some(new SqPtr()) else None 687 val trigger = if (params.trigger) Some(new TriggerCf) else None 688 // uop info 689 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 690 // vldu used only 691 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 692 val vpu = new VPUCtrlSignals 693 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 694 val vdIdx = UInt(3.W) 695 val vdIdxInField = UInt(3.W) 696 val isIndexed = Bool() 697 val isMasked = Bool() 698 }) 699 val debug = new DebugBundle 700 val debugInfo = new PerfDebugInfo 701 } 702 703 // ExuOutput + DynInst --> WriteBackBundle 704 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 705 val rfWen = Bool() 706 val fpWen = Bool() 707 val vecWen = Bool() 708 val v0Wen = Bool() 709 val vlWen = Bool() 710 val pdest = UInt(params.pregIdxWidth(backendParams).W) 711 val data = UInt(params.dataWidth.W) 712 val robIdx = new RobPtr()(p) 713 val flushPipe = Bool() 714 val replayInst = Bool() 715 val redirect = ValidIO(new Redirect) 716 val fflags = UInt(5.W) 717 val vxsat = Bool() 718 val exceptionVec = ExceptionVec() 719 val debug = new DebugBundle 720 val debugInfo = new PerfDebugInfo 721 722 this.wakeupSource = s"WB(${params.toString})" 723 724 def fromExuOutput(source: ExuOutput, wbType: String) = { 725 val typeMap = Map("int" -> 0, "fp" -> 1, "vf" -> 2, "v0" -> 3, "vl" -> 4) 726 this.rfWen := source.intWen.getOrElse(false.B) 727 this.fpWen := source.fpWen.getOrElse(false.B) 728 this.vecWen := source.vecWen.getOrElse(false.B) 729 this.v0Wen := source.v0Wen.getOrElse(false.B) 730 this.vlWen := source.vlWen.getOrElse(false.B) 731 this.pdest := source.pdest 732 this.data := source.data(source.params.wbIndex(typeMap(wbType))) 733 this.robIdx := source.robIdx 734 this.flushPipe := source.flushPipe.getOrElse(false.B) 735 this.replayInst := source.replay.getOrElse(false.B) 736 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 737 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 738 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 739 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 740 this.debug := source.debug 741 this.debugInfo := source.debugInfo 742 } 743 744 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 745 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 746 rfWrite.wen := this.rfWen && fire 747 rfWrite.addr := this.pdest 748 rfWrite.data := this.data 749 rfWrite.intWen := this.rfWen 750 rfWrite.fpWen := false.B 751 rfWrite.vecWen := false.B 752 rfWrite.v0Wen := false.B 753 rfWrite.vlWen := false.B 754 rfWrite 755 } 756 757 def asFpRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 758 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(FpData()).addrWidth))) 759 rfWrite.wen := this.fpWen && fire 760 rfWrite.addr := this.pdest 761 rfWrite.data := this.data 762 rfWrite.intWen := false.B 763 rfWrite.fpWen := this.fpWen 764 rfWrite.vecWen := false.B 765 rfWrite.v0Wen := false.B 766 rfWrite.vlWen := false.B 767 rfWrite 768 } 769 770 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 771 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 772 rfWrite.wen := this.vecWen && fire 773 rfWrite.addr := this.pdest 774 rfWrite.data := this.data 775 rfWrite.intWen := false.B 776 rfWrite.fpWen := false.B 777 rfWrite.vecWen := this.vecWen 778 rfWrite.v0Wen := false.B 779 rfWrite.vlWen := false.B 780 rfWrite 781 } 782 783 def asV0RfWriteBundle(fire: Bool): RfWritePortWithConfig = { 784 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(V0Data()).addrWidth))) 785 rfWrite.wen := this.v0Wen && fire 786 rfWrite.addr := this.pdest 787 rfWrite.data := this.data 788 rfWrite.intWen := false.B 789 rfWrite.fpWen := false.B 790 rfWrite.vecWen := false.B 791 rfWrite.v0Wen := this.v0Wen 792 rfWrite.vlWen := false.B 793 rfWrite 794 } 795 796 def asVlRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 797 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VlData()).addrWidth))) 798 rfWrite.wen := this.vlWen && fire 799 rfWrite.addr := this.pdest 800 rfWrite.data := this.data 801 rfWrite.intWen := false.B 802 rfWrite.fpWen := false.B 803 rfWrite.vecWen := false.B 804 rfWrite.v0Wen := false.B 805 rfWrite.vlWen := this.vlWen 806 rfWrite 807 } 808 } 809 810 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 811 // / 812 // [IssueQueue]--> ExuInput -- 813 class ExuBypassBundle( 814 val params: ExeUnitParams, 815 )(implicit p: Parameters) extends XSBundle { 816 val intWen = Bool() 817 val data = UInt(params.destDataBitsMax.W) 818 val pdest = UInt(params.wbPregIdxWidth.W) 819 } 820 821 class ExceptionInfo(implicit p: Parameters) extends XSBundle { 822 val pc = UInt(VAddrData().dataWidth.W) 823 val instr = UInt(32.W) 824 val commitType = CommitType() 825 val exceptionVec = ExceptionVec() 826 val gpaddr = UInt(GPAddrBits.W) 827 val singleStep = Bool() 828 val crossPageIPFFix = Bool() 829 val isInterrupt = Bool() 830 val isHls = Bool() 831 val vls = Bool() 832 val trigger = new TriggerCf 833 } 834 835 object UopIdx { 836 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 837 } 838 839 object FuLatency { 840 def apply(): UInt = UInt(width.W) 841 842 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 843 } 844 845 object ExuOH { 846 def apply(exuNum: Int): UInt = UInt(exuNum.W) 847 848 def apply()(implicit p: Parameters): UInt = UInt(width.W) 849 850 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 851 } 852 853 object ExuVec { 854 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 855 856 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 857 858 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 859 } 860 861 class CancelSignal(implicit p: Parameters) extends XSBundle { 862 val rfWen = Bool() 863 val fpWen = Bool() 864 val vecWen = Bool() 865 val v0Wen = Bool() 866 val vlWen = Bool() 867 val pdest = UInt(PhyRegIdxWidth.W) 868 } 869 870 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 871 val uop = new DynInst 872 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 873 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 874 val isFirstIssue = Bool() 875 val flowNum = OptionWrapper(isVector, NumLsElem()) 876 877 def src_rs1 = src(0) 878 def src_stride = src(1) 879 def src_vs3 = src(2) 880 def src_mask = if (isVector) src(3) else 0.U 881 def src_vl = if (isVector) src(4) else 0.U 882 } 883 884 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 885 val uop = new DynInst 886 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 887 val mask = if (isVector) Some(UInt(VLEN.W)) else None 888 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 889 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 890 val debug = new DebugBundle 891 892 def isVls = FuType.isVls(uop.fuType) 893 } 894 895 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 896 val uop = new DynInst 897 val flag = UInt(1.W) 898 } 899 900 object LoadShouldCancel { 901 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 902 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(0)}.reduce(_ || _)) 903 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 904 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 905 } 906 } 907} 908