1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.OptionWrapper 8import xiangshan._ 9import xiangshan.backend.datapath.DataConfig._ 10import xiangshan.backend.datapath.WbConfig.WbConfig 11import xiangshan.backend.decode.{ImmUnion, XDecode} 12import xiangshan.backend.exu.ExeUnitParams 13import xiangshan.backend.fu.FuType 14import xiangshan.backend.fu.fpu.Bundles.Frm 15import xiangshan.backend.fu.vector.Bundles.{Category, Nf, VConfig, VLmul, VSew, VType, Vl, Vxrm} 16import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, IssueQueueJumpBundle, SchedulerType, StatusArrayDeqRespBundle} 17import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 18import xiangshan.backend.rob.RobPtr 19import xiangshan.frontend._ 20import xiangshan.mem.{LqPtr, SqPtr} 21 22object Bundles { 23 24 // frontend -> backend 25 class StaticInst(implicit p: Parameters) extends XSBundle { 26 val instr = UInt(32.W) 27 val pc = UInt(VAddrBits.W) 28 val foldpc = UInt(MemPredPCWidth.W) 29 val exceptionVec = ExceptionVec() 30 val trigger = new TriggerCf 31 val preDecodeInfo = new PreDecodeInfo 32 val pred_taken = Bool() 33 val crossPageIPFFix = Bool() 34 val ftqPtr = new FtqPtr 35 val ftqOffset = UInt(log2Up(PredictWidth).W) 36 37 def connectCtrlFlow(source: CtrlFlow): Unit = { 38 this.instr := source.instr 39 this.pc := source.pc 40 this.foldpc := source.foldpc 41 this.exceptionVec := source.exceptionVec 42 this.trigger := source.trigger 43 this.preDecodeInfo := source.pd 44 this.pred_taken := source.pred_taken 45 this.crossPageIPFFix := source.crossPageIPFFix 46 this.ftqPtr := source.ftqPtr 47 this.ftqOffset := source.ftqOffset 48 } 49 } 50 51 // StaticInst --[Decode]--> DecodedInst 52 class DecodedInst(implicit p: Parameters) extends XSBundle { 53 def numSrc = backendParams.numSrc 54 // passed from StaticInst 55 val instr = UInt(32.W) 56 val pc = UInt(VAddrBits.W) 57 val foldpc = UInt(MemPredPCWidth.W) 58 val exceptionVec = ExceptionVec() 59 val trigger = new TriggerCf 60 val preDecodeInfo = new PreDecodeInfo 61 val pred_taken = Bool() 62 val crossPageIPFFix = Bool() 63 val ftqPtr = new FtqPtr 64 val ftqOffset = UInt(log2Up(PredictWidth).W) 65 // decoded 66 val srcType = Vec(numSrc, SrcType()) 67 val lsrc = Vec(numSrc, UInt(6.W)) 68 val ldest = UInt(6.W) 69 val fuType = FuType() 70 val fuOpType = FuOpType() 71 val rfWen = Bool() 72 val fpWen = Bool() 73 val vecWen = Bool() 74 val isXSTrap = Bool() 75 val waitForward = Bool() // no speculate execution 76 val blockBackward = Bool() 77 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 78 val selImm = SelImm() 79 val imm = UInt(ImmUnion.maxLen.W) 80 val fpu = new FPUCtrlSignals 81 val vpu = new VPUCtrlSignals 82 val isMove = Bool() 83 val uopIdx = UInt(5.W) 84 val uopSplitType = UopSplitType() 85 val isVset = Bool() 86 val firstUop = Bool() 87 val lastUop = Bool() 88 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 89 val commitType = CommitType() // Todo: remove it 90 91 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 92 isXSTrap, waitForward, blockBackward, flushPipe, uopSplitType, selImm) 93 94 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 95 val decoder: Seq[UInt] = ListLookup( 96 inst, XDecode.decodeDefault.map(bitPatToUInt), 97 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 98 ) 99 allSignals zip decoder foreach { case (s, d) => s := d } 100 this 101 } 102 103 def isSoftPrefetch: Bool = { 104 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 105 } 106 107 def connectStaticInst(source: StaticInst): Unit = { 108 for ((name, data) <- this.elements) { 109 if (source.elements.contains(name)) { 110 data := source.elements(name) 111 } 112 } 113 } 114 } 115 116 // DecodedInst --[Rename]--> DynInst 117 class DynInst(implicit p: Parameters) extends XSBundle { 118 def numSrc = backendParams.numSrc 119 // passed from StaticInst 120 val instr = UInt(32.W) 121 val pc = UInt(VAddrBits.W) 122 val foldpc = UInt(MemPredPCWidth.W) 123 val exceptionVec = ExceptionVec() 124 val trigger = new TriggerCf 125 val preDecodeInfo = new PreDecodeInfo 126 val pred_taken = Bool() 127 val crossPageIPFFix = Bool() 128 val ftqPtr = new FtqPtr 129 val ftqOffset = UInt(log2Up(PredictWidth).W) 130 // passed from DecodedInst 131 val srcType = Vec(numSrc, SrcType()) 132 val lsrc = Vec(numSrc, UInt(6.W)) 133 val ldest = UInt(6.W) 134 val fuType = FuType() 135 val fuOpType = FuOpType() 136 val rfWen = Bool() 137 val fpWen = Bool() 138 val vecWen = Bool() 139 val isXSTrap = Bool() 140 val waitForward = Bool() // no speculate execution 141 val blockBackward = Bool() 142 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 143 val selImm = SelImm() 144 val imm = UInt(XLEN.W) // Todo: check if it need minimized 145 val fpu = new FPUCtrlSignals 146 val vpu = new VPUCtrlSignals 147 val isMove = Bool() 148 val uopIdx = UInt(5.W) 149 val isVset = Bool() 150 val firstUop = Bool() 151 val lastUop = Bool() 152 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 153 val commitType = CommitType() 154 // rename 155 val srcState = Vec(numSrc, SrcState()) 156 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 157 val pdest = UInt(PhyRegIdxWidth.W) 158 val oldPdest = UInt(PhyRegIdxWidth.W) 159 val robIdx = new RobPtr 160 161 val eliminatedMove = Bool() 162 val debugInfo = new PerfDebugInfo 163 val storeSetHit = Bool() // inst has been allocated an store set 164 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 165 // Load wait is needed 166 // load inst will not be executed until former store (predicted by mdp) addr calcuated 167 val loadWaitBit = Bool() 168 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 169 // load inst will not be executed until ALL former store addr calcuated 170 val loadWaitStrict = Bool() 171 val ssid = UInt(SSIDWidth.W) 172 // Todo 173 val lqIdx = new LqPtr 174 val sqIdx = new SqPtr 175 // debug module 176 val singleStep = Bool() 177 // schedule 178 val replayInst = Bool() 179 180 def isLUI: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_U 181 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 182 183 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 184 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 185 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 186 187 def srcIsReady: Vec[Bool] = { 188 VecInit(this.srcType.zip(this.srcState).map { 189 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 190 }) 191 } 192 193 def clearExceptions( 194 exceptionBits: Seq[Int] = Seq(), 195 flushPipe : Boolean = false, 196 replayInst : Boolean = false 197 ): DynInst = { 198 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 199 if (!flushPipe) { this.flushPipe := false.B } 200 if (!replayInst) { this.replayInst := false.B } 201 this 202 } 203 204 def asWakeUpBundle: IssueQueueWakeUpBundle = { 205 val wakeup = Output(new IssueQueueWakeUpBundle(pdest.getWidth)) 206 wakeup.rfWen := this.rfWen 207 wakeup.fpWen := this.fpWen 208 wakeup.vecWen := this.vecWen 209 wakeup.pdest := this.pdest 210 wakeup 211 } 212 213 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 214 } 215 216 trait BundleSource { 217 var source = "not exist" 218 } 219 220 class IssueQueueWakeUpBundle(PregIdxWidth: Int) extends Bundle with BundleSource { 221 val rfWen = Bool() 222 val fpWen = Bool() 223 val vecWen = Bool() 224 val pdest = UInt(PregIdxWidth.W) 225 226 /** 227 * @param successor Seq[(psrc, srcType)] 228 * @return Seq[if wakeup psrc] 229 */ 230 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool]= { 231 successor.map { case (thatPsrc, srcType) => 232 val pdestMatch = pdest === thatPsrc 233 pdestMatch && ( 234 SrcType.isFp(srcType) && this.fpWen || 235 SrcType.isXp(srcType) && this.rfWen || 236 SrcType.isVp(srcType) && this.vecWen 237 ) && valid 238 } 239 } 240 } 241 242 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 243 // vtype 244 val vill = Bool() 245 val vma = Bool() // 1: agnostic, 0: undisturbed 246 val vta = Bool() // 1: agnostic, 0: undisturbed 247 val vsew = VSew() 248 val vlmul = VLmul() // 1/8~8 --> -3~3 249 250 val vm = Bool() // 0: need v0.t 251 val vstart = Vl() 252 253 // float rounding mode 254 val frm = Frm() 255 // vector fix int rounding mode 256 val vxrm = Vxrm() 257 // vector uop index, exclude other non-vector uop 258 val vuopIdx = UopIdx() 259 // maybe used if data dependancy 260 val vmask = UInt(MaskSrcData().dataWidth.W) 261 val vl = Vl() 262 263 // vector load/store 264 val nf = Nf() 265 266 val needScalaSrc = Bool() 267 268 val isReverse = Bool() // vrsub, vrdiv 269 val isExt = Bool() 270 val isNarrow = Bool() 271 val isDstMask = Bool() // vvm, vvvm, mmm 272 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 273 274 def vtype: VType = { 275 val res = Wire(VType()) 276 res.illegal := this.vill 277 res.vma := this.vma 278 res.vta := this.vta 279 res.vsew := this.vsew 280 res.vlmul := this.vlmul 281 res 282 } 283 284 def vconfig: VConfig = { 285 val res = Wire(VConfig()) 286 res.vtype := this.vtype 287 res.vl := this.vl 288 res 289 } 290 } 291 292 // DynInst --[IssueQueue]--> DataPath 293 class IssueQueueIssueBundle( 294 iqParams: IssueBlockParams, 295 exuParams: ExeUnitParams, 296 addrWidth: Int, 297 vaddrBits: Int 298 )(implicit 299 p: Parameters 300 ) extends Bundle { 301 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 302 303 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 304 rfReadDataCfgSet.map((set: Set[DataConfig]) => 305 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, addrWidth)).toSeq) 306 ) 307 )) 308 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 309 val immType = SelImm() // used to select imm extractor 310 val common = new ExuInput(exuParams) 311 val jmp = if (exuParams.needPc) Some(Flipped(new IssueQueueJumpBundle)) else None 312 val addrOH = UInt(iqParams.numEntries.W) 313 314 def getSource: SchedulerType = exuParams.getWBSource 315 def getIntWbBusyBundle = common.rfWen.toSeq 316 def getVfWbBusyBundle = common.getVfWen.toSeq 317 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt) 318 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf) 319 } 320 321 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 322 val issueQueueParams = this.params 323 val og0resp = Valid(new StatusArrayDeqRespBundle) 324 val og1resp = Valid(new StatusArrayDeqRespBundle) 325 } 326 327 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 328 val respType = RSFeedbackType() // update credit if needs replay 329 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 330 val fuType = FuType() 331 } 332 333 class WbFuBusyTableWriteBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 334 val deqResp = Valid(new fuBusyRespBundle) 335 val og0Resp = Valid(new fuBusyRespBundle) 336 val og1Resp = Valid(new fuBusyRespBundle) 337 } 338 339 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 340 private val intCertainLat = params.intLatencyCertain 341 private val vfCertainLat = params.vfLatencyCertain 342 private val intLat = params.intLatencyValMax 343 private val vfLat = params.vfLatencyValMax 344 345 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 346 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 347 } 348 349 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 350 private val intCertainLat = params.intLatencyCertain 351 private val vfCertainLat = params.vfLatencyCertain 352 353 val intConflict = OptionWrapper(intCertainLat, Bool()) 354 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 355 } 356 357 // DataPath --[ExuInput]--> Exu 358 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 359 val fuType = FuType() 360 val fuOpType = FuOpType() 361 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 362 val imm = UInt(XLEN.W) 363 val robIdx = new RobPtr 364 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 365 val isFirstIssue = Bool() // Only used by store yet 366 val pdest = UInt(params.wbPregIdxWidth.W) 367 val rfWen = if (params.writeIntRf) Some(Bool()) else None 368 val fpWen = if (params.writeFpRf) Some(Bool()) else None 369 val vecWen = if (params.writeVecRf) Some(Bool()) else None 370 val fpu = if (params.needFPUCtrl) Some(new FPUCtrlSignals) else None 371 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 372 val flushPipe = if (params.flushPipe) Some(Bool()) else None 373 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 374 val jalrTarget = if (params.hasJmpFu) Some(UInt(VAddrData().dataWidth.W)) else None 375 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 376 val ftqIdx = if (params.needPc || params.replayInst) 377 Some(new FtqPtr) else None 378 val ftqOffset = if (params.needPc || params.replayInst) 379 Some(UInt(log2Up(PredictWidth).W)) else None 380 val predictInfo = if (params.hasPredecode) Some(new Bundle { 381 val target = UInt(VAddrData().dataWidth.W) 382 val taken = Bool() 383 }) else None 384 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 385 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 386 387 def getVfWen = { 388 if (params.writeFpRf) this.fpWen 389 else if(params.writeVecRf) this.vecWen 390 else None 391 } 392 393 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 394 // src is assigned to rfReadData 395 this.fuType := source.common.fuType 396 this.fuOpType := source.common.fuOpType 397 this.imm := source.common.imm 398 this.robIdx := source.common.robIdx 399 this.pdest := source.common.pdest 400 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 401 this.iqIdx := source.common.iqIdx // Only used by mem feedback 402 this.rfWen .foreach(_ := source.common.rfWen.get) 403 this.fpWen .foreach(_ := source.common.fpWen.get) 404 this.vecWen .foreach(_ := source.common.vecWen.get) 405 this.fpu .foreach(_ := source.common.fpu.get) 406 this.vpu .foreach(_ := source.common.vpu.get) 407 this.flushPipe .foreach(_ := source.common.flushPipe.get) 408 this.pc .foreach(_ := source.jmp.get.pc) 409 this.jalrTarget .foreach(_ := source.jmp.get.target) 410 this.preDecode .foreach(_ := source.common.preDecode.get) 411 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 412 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 413 this.predictInfo .foreach(_ := source.common.predictInfo.get) 414 this.lqIdx .foreach(_ := source.common.lqIdx.get) 415 this.sqIdx .foreach(_ := source.common.sqIdx.get) 416 } 417 } 418 419 // ExuInput --[FuncUnit]--> ExuOutput 420 class ExuOutput( 421 val params: ExeUnitParams, 422 )(implicit 423 val p: Parameters 424 ) extends Bundle with BundleSource with HasXSParameter { 425 val data = UInt(params.dataBitsMax.W) 426 val pdest = UInt(params.wbPregIdxWidth.W) 427 val robIdx = new RobPtr 428 val intWen = if (params.writeIntRf) Some(Bool()) else None 429 val fpWen = if (params.writeFpRf) Some(Bool()) else None 430 val vecWen = if (params.writeVecRf) Some(Bool()) else None 431 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 432 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 433 val vxsat = if (params.writeVxsat) Some(Bool()) else None 434 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 435 val flushPipe = if (params.flushPipe) Some(Bool()) else None 436 val replay = if (params.replayInst) Some(Bool()) else None 437 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 438 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 439 Some(new SqPtr()) else None 440 val ftqIdx = if (params.needPc || params.replayInst) 441 Some(new FtqPtr) else None 442 val ftqOffset = if (params.needPc || params.replayInst) 443 Some(UInt(log2Up(PredictWidth).W)) else None 444 // uop info 445 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 446 val debug = new DebugBundle 447 val debugInfo = new PerfDebugInfo 448 } 449 450 // ExuOutput + DynInst --> WriteBackBundle 451 class WriteBackBundle(val params: WbConfig)(implicit p: Parameters) extends Bundle with BundleSource { 452 val rfWen = Bool() 453 val fpWen = Bool() 454 val vecWen = Bool() 455 val pdest = UInt(params.pregIdxWidth.W) 456 val data = UInt(params.dataWidth.W) 457 val robIdx = new RobPtr()(p) 458 val flushPipe = Bool() 459 val replayInst = Bool() 460 val redirect = ValidIO(new Redirect) 461 val fflags = UInt(5.W) 462 val vxsat = Bool() 463 val exceptionVec = ExceptionVec() 464 val debug = new DebugBundle 465 val debugInfo = new PerfDebugInfo 466 467 def fromExuOutput(source: ExuOutput) = { 468 this.rfWen := source.intWen.getOrElse(false.B) 469 this.fpWen := source.fpWen.getOrElse(false.B) 470 this.vecWen := source.vecWen.getOrElse(false.B) 471 this.pdest := source.pdest 472 this.data := source.data 473 this.robIdx := source.robIdx 474 this.flushPipe := source.flushPipe.getOrElse(false.B) 475 this.replayInst := source.replay.getOrElse(false.B) 476 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 477 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 478 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 479 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 480 this.debug := source.debug 481 this.debugInfo := source.debugInfo 482 } 483 484 def asWakeUpBundle: IssueQueueWakeUpBundle = { 485 val wakeup = Output(new IssueQueueWakeUpBundle(params.pregIdxWidth)) 486 wakeup.rfWen := this.rfWen 487 wakeup.fpWen := this.fpWen 488 wakeup.vecWen := this.vecWen 489 wakeup.pdest := this.pdest 490 wakeup.source = this.source 491 wakeup 492 } 493 494 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 495 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 496 rfWrite.wen := this.rfWen && fire 497 rfWrite.addr := this.pdest 498 rfWrite.data := this.data 499 rfWrite.intWen := this.rfWen 500 rfWrite.fpWen := false.B 501 rfWrite.vecWen := false.B 502 rfWrite 503 } 504 505 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 506 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 507 rfWrite.wen := (this.fpWen || this.vecWen) && fire 508 rfWrite.addr := this.pdest 509 rfWrite.data := this.data 510 rfWrite.intWen := false.B 511 rfWrite.fpWen := this.fpWen 512 rfWrite.vecWen := this.vecWen 513 rfWrite 514 } 515 } 516 517 class ExceptionInfo extends Bundle { 518 val pc = UInt(VAddrData().dataWidth.W) 519 val instr = UInt(32.W) 520 val commitType = CommitType() 521 val exceptionVec = ExceptionVec() 522 val singleStep = Bool() 523 val crossPageIPFFix = Bool() 524 val isInterrupt = Bool() 525 } 526 527 object UopIdx { 528 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 529 } 530 531 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 532 val uop = new DynInst 533 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 534 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 535 val isFirstIssue = Bool() 536 } 537 538 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 539 val uop = new DynInst 540 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 541 val debug = new DebugBundle 542 } 543 544 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 545 val uop = new DynInst 546 val flag = UInt(1.W) 547 } 548} 549