1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24import yunsuan.vector.VIFuParam 25 26object Bundles { 27 /** 28 * Connect Same Name Port like bundleSource := bundleSinkBudle. 29 * 30 * There is no limit to the number of ports on both sides. 31 * 32 * Don't forget to connect the remaining ports! 33 */ 34 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 35 bundleSource.elements.foreach { case (name, data) => 36 if (bundleSink.elements.contains(name)) 37 data := bundleSink.elements(name) 38 } 39 } 40 // frontend -> backend 41 class StaticInst(implicit p: Parameters) extends XSBundle { 42 val instr = UInt(32.W) 43 val pc = UInt(VAddrBits.W) 44 val foldpc = UInt(MemPredPCWidth.W) 45 val exceptionVec = ExceptionVec() 46 val trigger = new TriggerCf 47 val preDecodeInfo = new PreDecodeInfo 48 val pred_taken = Bool() 49 val crossPageIPFFix = Bool() 50 val ftqPtr = new FtqPtr 51 val ftqOffset = UInt(log2Up(PredictWidth).W) 52 53 def connectCtrlFlow(source: CtrlFlow): Unit = { 54 this.instr := source.instr 55 this.pc := source.pc 56 this.foldpc := source.foldpc 57 this.exceptionVec := source.exceptionVec 58 this.trigger := source.trigger 59 this.preDecodeInfo := source.pd 60 this.pred_taken := source.pred_taken 61 this.crossPageIPFFix := source.crossPageIPFFix 62 this.ftqPtr := source.ftqPtr 63 this.ftqOffset := source.ftqOffset 64 } 65 } 66 67 // StaticInst --[Decode]--> DecodedInst 68 class DecodedInst(implicit p: Parameters) extends XSBundle { 69 def numSrc = backendParams.numSrc 70 // passed from StaticInst 71 val instr = UInt(32.W) 72 val pc = UInt(VAddrBits.W) 73 val foldpc = UInt(MemPredPCWidth.W) 74 val exceptionVec = ExceptionVec() 75 val trigger = new TriggerCf 76 val preDecodeInfo = new PreDecodeInfo 77 val pred_taken = Bool() 78 val crossPageIPFFix = Bool() 79 val ftqPtr = new FtqPtr 80 val ftqOffset = UInt(log2Up(PredictWidth).W) 81 // decoded 82 val srcType = Vec(numSrc, SrcType()) 83 val lsrc = Vec(numSrc, UInt(LogicRegsWidth.W)) 84 val ldest = UInt(LogicRegsWidth.W) 85 val fuType = FuType() 86 val fuOpType = FuOpType() 87 val rfWen = Bool() 88 val fpWen = Bool() 89 val vecWen = Bool() 90 val v0Wen = Bool() 91 val vlWen = Bool() 92 val isXSTrap = Bool() 93 val waitForward = Bool() // no speculate execution 94 val blockBackward = Bool() 95 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 96 val canRobCompress = Bool() 97 val selImm = SelImm() 98 val imm = UInt(ImmUnion.maxLen.W) 99 val fpu = new FPUCtrlSignals 100 val vpu = new VPUCtrlSignals 101 val vlsInstr = Bool() 102 val wfflags = Bool() 103 val isMove = Bool() 104 val uopIdx = UopIdx() 105 val uopSplitType = UopSplitType() 106 val isVset = Bool() 107 val firstUop = Bool() 108 val lastUop = Bool() 109 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 110 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 111 val commitType = CommitType() // Todo: remove it 112 113 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 114 115 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 116 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 117 118 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 119 val decoder: Seq[UInt] = ListLookup( 120 inst, XDecode.decodeDefault.map(bitPatToUInt), 121 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 122 ) 123 allSignals zip decoder foreach { case (s, d) => s := d } 124 debug_fuType.foreach(_ := fuType) 125 this 126 } 127 128 def isSoftPrefetch: Bool = { 129 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 130 } 131 132 def connectStaticInst(source: StaticInst): Unit = { 133 for ((name, data) <- this.elements) { 134 if (source.elements.contains(name)) { 135 data := source.elements(name) 136 } 137 } 138 } 139 } 140 141 // DecodedInst --[Rename]--> DynInst 142 class DynInst(implicit p: Parameters) extends XSBundle { 143 def numSrc = backendParams.numSrc 144 // passed from StaticInst 145 val instr = UInt(32.W) 146 val pc = UInt(VAddrBits.W) 147 val foldpc = UInt(MemPredPCWidth.W) 148 val exceptionVec = ExceptionVec() 149 val hasException = Bool() 150 val trigger = new TriggerCf 151 val preDecodeInfo = new PreDecodeInfo 152 val pred_taken = Bool() 153 val crossPageIPFFix = Bool() 154 val ftqPtr = new FtqPtr 155 val ftqOffset = UInt(log2Up(PredictWidth).W) 156 // passed from DecodedInst 157 val srcType = Vec(numSrc, SrcType()) 158 val ldest = UInt(LogicRegsWidth.W) 159 val fuType = FuType() 160 val fuOpType = FuOpType() 161 val rfWen = Bool() 162 val fpWen = Bool() 163 val vecWen = Bool() 164 val v0Wen = Bool() 165 val vlWen = Bool() 166 val isXSTrap = Bool() 167 val waitForward = Bool() // no speculate execution 168 val blockBackward = Bool() 169 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 170 val canRobCompress = Bool() 171 val selImm = SelImm() 172 val imm = UInt(32.W) 173 val fpu = new FPUCtrlSignals 174 val vpu = new VPUCtrlSignals 175 val vlsInstr = Bool() 176 val wfflags = Bool() 177 val isMove = Bool() 178 val uopIdx = UopIdx() 179 val isVset = Bool() 180 val firstUop = Bool() 181 val lastUop = Bool() 182 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 183 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 184 val commitType = CommitType() 185 // rename 186 val srcState = Vec(numSrc, SrcState()) 187 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 188 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 189 val pdest = UInt(PhyRegIdxWidth.W) 190 val robIdx = new RobPtr 191 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 192 val dirtyFs = Bool() 193 val dirtyVs = Bool() 194 195 val eliminatedMove = Bool() 196 // Take snapshot at this CFI inst 197 val snapshot = Bool() 198 val debugInfo = new PerfDebugInfo 199 val storeSetHit = Bool() // inst has been allocated an store set 200 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 201 // Load wait is needed 202 // load inst will not be executed until former store (predicted by mdp) addr calcuated 203 val loadWaitBit = Bool() 204 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 205 // load inst will not be executed until ALL former store addr calcuated 206 val loadWaitStrict = Bool() 207 val ssid = UInt(SSIDWidth.W) 208 // Todo 209 val lqIdx = new LqPtr 210 val sqIdx = new SqPtr 211 // debug module 212 val singleStep = Bool() 213 // schedule 214 val replayInst = Bool() 215 216 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 217 218 val numLsElem = NumLsElem() 219 220 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 221 222 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 223 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 224 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 225 226 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 227 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 228 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 229 def isNotSvinval = !FuType.isFence(fuType) 230 231 def isHls: Bool = { 232 fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType) 233 } 234 235 def srcIsReady: Vec[Bool] = { 236 VecInit(this.srcType.zip(this.srcState).map { 237 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 238 }) 239 } 240 241 def clearExceptions( 242 exceptionBits: Seq[Int] = Seq(), 243 flushPipe : Boolean = false, 244 replayInst : Boolean = false 245 ): DynInst = { 246 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 247 if (!flushPipe) { this.flushPipe := false.B } 248 if (!replayInst) { this.replayInst := false.B } 249 this 250 } 251 252 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen || v0Wen || vlWen 253 } 254 255 trait BundleSource { 256 var wakeupSource = "undefined" 257 var idx = 0 258 } 259 260 /** 261 * 262 * @param pregIdxWidth index width of preg 263 * @param exuIndices exu indices of wakeup bundle 264 */ 265 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int])(implicit p: Parameters) extends XSBundle { 266 val rfWen = Bool() 267 val fpWen = Bool() 268 val vecWen = Bool() 269 val v0Wen = Bool() 270 val vlWen = Bool() 271 val pdest = UInt(pregIdxWidth.W) 272 273 /** 274 * @param successor Seq[(psrc, srcType)] 275 * @return Seq[if wakeup psrc] 276 */ 277 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 278 successor.map { case (thatPsrc, srcType) => 279 val pdestMatch = pdest === thatPsrc 280 pdestMatch && ( 281 SrcType.isFp(srcType) && this.fpWen || 282 SrcType.isXp(srcType) && this.rfWen || 283 SrcType.isVp(srcType) && this.vecWen 284 ) && valid 285 } 286 } 287 def wakeUpV0(successor: (UInt, UInt), valid: Bool): Bool = { 288 val (thatPsrc, srcType) = successor 289 val pdestMatch = pdest === thatPsrc 290 pdestMatch && ( 291 SrcType.isV0(srcType) && this.v0Wen 292 ) && valid 293 } 294 def wakeUpVl(successor: (UInt, UInt), valid: Bool): Bool = { 295 val (thatPsrc, srcType) = successor 296 val pdestMatch = pdest === thatPsrc 297 pdestMatch && ( 298 SrcType.isVp(srcType) && this.vlWen 299 ) && valid 300 } 301 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 302 successor.map { case (thatPsrc, srcType) => 303 val pdestMatch = pdest === thatPsrc 304 pdestMatch && ( 305 SrcType.isFp(srcType) && this.fpWen || 306 SrcType.isXp(srcType) && this.rfWen || 307 SrcType.isVp(srcType) && this.vecWen 308 ) 309 } 310 } 311 def wakeUpV0FromIQ(successor: (UInt, UInt)): Bool = { 312 val (thatPsrc, srcType) = successor 313 val pdestMatch = pdest === thatPsrc 314 pdestMatch && ( 315 SrcType.isV0(srcType) && this.v0Wen 316 ) 317 } 318 def wakeUpVlFromIQ(successor: (UInt, UInt)): Bool = { 319 val (thatPsrc, srcType) = successor 320 val pdestMatch = pdest === thatPsrc 321 pdestMatch && ( 322 SrcType.isVp(srcType) && this.vlWen 323 ) 324 } 325 326 def hasOnlyOneSource: Boolean = exuIndices.size == 1 327 328 def hasMultiSources: Boolean = exuIndices.size > 1 329 330 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 331 332 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 333 334 def exuIdx: Int = { 335 require(hasOnlyOneSource) 336 this.exuIndices.head 337 } 338 } 339 340 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams)(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 341 342 } 343 344 class IssueQueueIQWakeUpBundle( 345 exuIdx: Int, 346 backendParams: BackendParams, 347 copyWakeupOut: Boolean = false, 348 copyNum: Int = 0 349 )(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 350 val loadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 351 val is0Lat = Bool() 352 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 353 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 354 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 355 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 356 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 357 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 358 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 359 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 360 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[Vec[Bool]]): Unit = { 361 this.rfWen := exuInput.rfWen.getOrElse(false.B) 362 this.fpWen := exuInput.fpWen.getOrElse(false.B) 363 this.vecWen := exuInput.vecWen.getOrElse(false.B) 364 this.v0Wen := exuInput.v0Wen.getOrElse(false.B) 365 this.vlWen := exuInput.vlWen.getOrElse(false.B) 366 this.pdest := exuInput.pdest 367 } 368 369 def fromExuInput(exuInput: ExuInput): Unit = { 370 this.rfWen := exuInput.rfWen.getOrElse(false.B) 371 this.fpWen := exuInput.fpWen.getOrElse(false.B) 372 this.vecWen := exuInput.vecWen.getOrElse(false.B) 373 this.v0Wen := exuInput.v0Wen.getOrElse(false.B) 374 this.vlWen := exuInput.vlWen.getOrElse(false.B) 375 this.pdest := exuInput.pdest 376 } 377 } 378 379 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 380 // vtype 381 val vill = Bool() 382 val vma = Bool() // 1: agnostic, 0: undisturbed 383 val vta = Bool() // 1: agnostic, 0: undisturbed 384 val vsew = VSew() 385 val vlmul = VLmul() // 1/8~8 --> -3~3 386 387 val vm = Bool() // 0: need v0.t 388 val vstart = Vl() 389 390 // float rounding mode 391 val frm = Frm() 392 // scalar float instr and vector float reduction 393 val fpu = Fpu() 394 // vector fix int rounding mode 395 val vxrm = Vxrm() 396 // vector uop index, exclude other non-vector uop 397 val vuopIdx = UopIdx() 398 val lastUop = Bool() 399 // maybe used if data dependancy 400 val vmask = UInt(V0Data().dataWidth.W) 401 val vl = Vl() 402 403 // vector load/store 404 val nf = Nf() 405 val veew = VEew() 406 407 val isReverse = Bool() // vrsub, vrdiv 408 val isExt = Bool() 409 val isNarrow = Bool() 410 val isDstMask = Bool() // vvm, vvvm, mmm 411 val isOpMask = Bool() // vmand, vmnand 412 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 413 414 val isDependOldvd = Bool() // some instruction's computation depends on oldvd 415 val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum 416 417 def vtype: VType = { 418 val res = Wire(VType()) 419 res.illegal := this.vill 420 res.vma := this.vma 421 res.vta := this.vta 422 res.vsew := this.vsew 423 res.vlmul := this.vlmul 424 res 425 } 426 427 def vconfig: VConfig = { 428 val res = Wire(VConfig()) 429 res.vtype := this.vtype 430 res.vl := this.vl 431 res 432 } 433 434 def connectVType(source: VType): Unit = { 435 this.vill := source.illegal 436 this.vma := source.vma 437 this.vta := source.vta 438 this.vsew := source.vsew 439 this.vlmul := source.vlmul 440 } 441 } 442 443 // DynInst --[IssueQueue]--> DataPath 444 class IssueQueueIssueBundle( 445 iqParams: IssueBlockParams, 446 val exuParams: ExeUnitParams, 447 )(implicit 448 p: Parameters 449 ) extends Bundle { 450 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 451 452 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 453 rfReadDataCfgSet.map((set: Set[DataConfig]) => 454 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 455 ) 456 )) 457 458 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 459 val immType = SelImm() // used to select imm extractor 460 val common = new ExuInput(exuParams) 461 val addrOH = UInt(iqParams.numEntries.W) 462 463 def exuIdx = exuParams.exuIdx 464 def getSource: SchedulerType = exuParams.getWBSource 465 466 def getRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 467 rf.zip(srcType).map { 468 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 469 makeValid(issueValid, rfRd.head) 470 }.toSeq 471 } 472 } 473 474 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 475 val issueQueueParams = this.params 476 val og0resp = Valid(new EntryDeqRespBundle) 477 val og1resp = Valid(new EntryDeqRespBundle) 478 } 479 480 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 481 private val intCertainLat = params.intLatencyCertain 482 private val fpCertainLat = params.fpLatencyCertain 483 private val vfCertainLat = params.vfLatencyCertain 484 private val v0CertainLat = params.v0LatencyCertain 485 private val vlCertainLat = params.vlLatencyCertain 486 private val intLat = params.intLatencyValMax 487 private val fpLat = params.fpLatencyValMax 488 private val vfLat = params.vfLatencyValMax 489 private val v0Lat = params.v0LatencyValMax 490 private val vlLat = params.vlLatencyValMax 491 492 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 493 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 494 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 495 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 496 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 497 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 498 val fpDeqRespSet = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 499 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 500 val v0DeqRespSet = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 501 val vlDeqRespSet = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 502 } 503 504 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 505 private val intCertainLat = params.intLatencyCertain 506 private val fpCertainLat = params.fpLatencyCertain 507 private val vfCertainLat = params.vfLatencyCertain 508 private val v0CertainLat = params.v0LatencyCertain 509 private val vlCertainLat = params.vlLatencyCertain 510 private val intLat = params.intLatencyValMax 511 private val fpLat = params.fpLatencyValMax 512 private val vfLat = params.vfLatencyValMax 513 private val v0Lat = params.v0LatencyValMax 514 private val vlLat = params.vlLatencyValMax 515 516 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 517 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 518 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 519 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 520 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 521 } 522 523 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 524 private val intCertainLat = params.intLatencyCertain 525 private val fpCertainLat = params.fpLatencyCertain 526 private val vfCertainLat = params.vfLatencyCertain 527 private val v0CertainLat = params.v0LatencyCertain 528 private val vlCertainLat = params.vlLatencyCertain 529 530 val intConflict = OptionWrapper(intCertainLat, Bool()) 531 val fpConflict = OptionWrapper(fpCertainLat, Bool()) 532 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 533 val v0Conflict = OptionWrapper(v0CertainLat, Bool()) 534 val vlConflict = OptionWrapper(vlCertainLat, Bool()) 535 } 536 537 class ImmInfo extends Bundle { 538 val imm = UInt(32.W) 539 val immType = SelImm() 540 } 541 542 // DataPath --[ExuInput]--> Exu 543 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 544 val fuType = FuType() 545 val fuOpType = FuOpType() 546 val src = Vec(params.numRegSrc, UInt(params.srcDataBitsMax.W)) 547 val imm = UInt(32.W) 548 val robIdx = new RobPtr 549 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 550 val isFirstIssue = Bool() // Only used by store yet 551 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 552 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 553 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 554 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 555 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 556 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 557 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 558 val pdest = UInt(params.wbPregIdxWidth.W) 559 val rfWen = if (params.needIntWen) Some(Bool()) else None 560 val fpWen = if (params.needFpWen) Some(Bool()) else None 561 val vecWen = if (params.needVecWen) Some(Bool()) else None 562 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 563 val vlWen = if (params.needVlWen) Some(Bool()) else None 564 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 565 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 566 val flushPipe = if (params.flushPipe) Some(Bool()) else None 567 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 568 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 569 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 570 Some(new FtqPtr) else None 571 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 572 Some(UInt(log2Up(PredictWidth).W)) else None 573 val predictInfo = if (params.needPdInfo) Some(new Bundle { 574 val target = UInt(VAddrData().dataWidth.W) 575 val taken = Bool() 576 }) else None 577 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 578 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 579 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 580 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 581 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 582 // only vector load store need 583 val numLsElem = OptionWrapper(params.hasVecLsFu, NumLsElem()) 584 585 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 586 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 587 val dataSources = Vec(params.numRegSrc, DataSource()) 588 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 589 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 590 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 591 592 val perfDebugInfo = new PerfDebugInfo() 593 594 def exuIdx = this.params.exuIdx 595 596 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 597 if (params.isIQWakeUpSink) { 598 require( 599 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 600 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 601 ) 602 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 603 case(exuOH: Vec[Bool], srcTimer: UInt) => 604 (exuOH.asUInt & og0CancelOH).orR && srcTimer === 1.U 605 }.reduce(_ | _) 606 l1Cancel 607 } else { 608 false.B 609 } 610 } 611 612 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 613 // src is assigned to rfReadData 614 this.fuType := source.common.fuType 615 this.fuOpType := source.common.fuOpType 616 this.imm := source.common.imm 617 this.robIdx := source.common.robIdx 618 this.pdest := source.common.pdest 619 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 620 this.iqIdx := source.common.iqIdx // Only used by mem feedback 621 this.dataSources := source.common.dataSources 622 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 623 this.rfWen .foreach(_ := source.common.rfWen.get) 624 this.fpWen .foreach(_ := source.common.fpWen.get) 625 this.vecWen .foreach(_ := source.common.vecWen.get) 626 this.v0Wen .foreach(_ := source.common.v0Wen.get) 627 this.vlWen .foreach(_ := source.common.vlWen.get) 628 this.fpu .foreach(_ := source.common.fpu.get) 629 this.vpu .foreach(_ := source.common.vpu.get) 630 this.flushPipe .foreach(_ := source.common.flushPipe.get) 631 this.pc .foreach(_ := source.common.pc.get) 632 this.preDecode .foreach(_ := source.common.preDecode.get) 633 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 634 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 635 this.predictInfo .foreach(_ := source.common.predictInfo.get) 636 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 637 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 638 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 639 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 640 this.ssid .foreach(_ := source.common.ssid.get) 641 this.lqIdx .foreach(_ := source.common.lqIdx.get) 642 this.sqIdx .foreach(_ := source.common.sqIdx.get) 643 this.numLsElem .foreach(_ := source.common.numLsElem.get) 644 this.srcTimer .foreach(_ := source.common.srcTimer.get) 645 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 646 } 647 } 648 649 // ExuInput --[FuncUnit]--> ExuOutput 650 class ExuOutput( 651 val params: ExeUnitParams, 652 )(implicit 653 val p: Parameters 654 ) extends Bundle with BundleSource with HasXSParameter { 655 val data = Vec(params.wbPathNum, UInt(params.destDataBitsMax.W)) 656 val pdest = UInt(params.wbPregIdxWidth.W) 657 val robIdx = new RobPtr 658 val intWen = if (params.needIntWen) Some(Bool()) else None 659 val fpWen = if (params.needFpWen) Some(Bool()) else None 660 val vecWen = if (params.needVecWen) Some(Bool()) else None 661 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 662 val vlWen = if (params.needVlWen) Some(Bool()) else None 663 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 664 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 665 val wflags = if (params.writeFflags) Some(Bool()) else None 666 val vxsat = if (params.writeVxsat) Some(Bool()) else None 667 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 668 val flushPipe = if (params.flushPipe) Some(Bool()) else None 669 val replay = if (params.replayInst) Some(Bool()) else None 670 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 671 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 672 Some(new SqPtr()) else None 673 val trigger = if (params.trigger) Some(new TriggerCf) else None 674 // uop info 675 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 676 // vldu used only 677 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 678 val vpu = new VPUCtrlSignals 679 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 680 val vdIdx = UInt(3.W) 681 val vdIdxInField = UInt(3.W) 682 val isIndexed = Bool() 683 val isMasked = Bool() 684 }) 685 val debug = new DebugBundle 686 val debugInfo = new PerfDebugInfo 687 } 688 689 // ExuOutput + DynInst --> WriteBackBundle 690 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 691 val rfWen = Bool() 692 val fpWen = Bool() 693 val vecWen = Bool() 694 val v0Wen = Bool() 695 val vlWen = Bool() 696 val pdest = UInt(params.pregIdxWidth(backendParams).W) 697 val data = UInt(params.dataWidth.W) 698 val robIdx = new RobPtr()(p) 699 val flushPipe = Bool() 700 val replayInst = Bool() 701 val redirect = ValidIO(new Redirect) 702 val fflags = UInt(5.W) 703 val vxsat = Bool() 704 val exceptionVec = ExceptionVec() 705 val debug = new DebugBundle 706 val debugInfo = new PerfDebugInfo 707 708 this.wakeupSource = s"WB(${params.toString})" 709 710 def fromExuOutput(source: ExuOutput, wbType: String) = { 711 val typeMap = Map("int" -> 0, "fp" -> 1, "vf" -> 2, "v0" -> 3, "vl" -> 4) 712 this.rfWen := source.intWen.getOrElse(false.B) 713 this.fpWen := source.fpWen.getOrElse(false.B) 714 this.vecWen := source.vecWen.getOrElse(false.B) 715 this.v0Wen := source.v0Wen.getOrElse(false.B) 716 this.vlWen := source.vlWen.getOrElse(false.B) 717 this.pdest := source.pdest 718 this.data := source.data(source.params.wbIndex(typeMap(wbType))) 719 this.robIdx := source.robIdx 720 this.flushPipe := source.flushPipe.getOrElse(false.B) 721 this.replayInst := source.replay.getOrElse(false.B) 722 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 723 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 724 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 725 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 726 this.debug := source.debug 727 this.debugInfo := source.debugInfo 728 } 729 730 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 731 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 732 rfWrite.wen := this.rfWen && fire 733 rfWrite.addr := this.pdest 734 rfWrite.data := this.data 735 rfWrite.intWen := this.rfWen 736 rfWrite.fpWen := false.B 737 rfWrite.vecWen := false.B 738 rfWrite.v0Wen := false.B 739 rfWrite.vlWen := false.B 740 rfWrite 741 } 742 743 def asFpRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 744 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(FpData()).addrWidth))) 745 rfWrite.wen := this.fpWen && fire 746 rfWrite.addr := this.pdest 747 rfWrite.data := this.data 748 rfWrite.intWen := false.B 749 rfWrite.fpWen := this.fpWen 750 rfWrite.vecWen := false.B 751 rfWrite.v0Wen := false.B 752 rfWrite.vlWen := false.B 753 rfWrite 754 } 755 756 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 757 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 758 rfWrite.wen := this.vecWen && fire 759 rfWrite.addr := this.pdest 760 rfWrite.data := this.data 761 rfWrite.intWen := false.B 762 rfWrite.fpWen := false.B 763 rfWrite.vecWen := this.vecWen 764 rfWrite.v0Wen := false.B 765 rfWrite.vlWen := false.B 766 rfWrite 767 } 768 769 def asV0RfWriteBundle(fire: Bool): RfWritePortWithConfig = { 770 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(V0Data()).addrWidth))) 771 rfWrite.wen := this.v0Wen && fire 772 rfWrite.addr := this.pdest 773 rfWrite.data := this.data 774 rfWrite.intWen := false.B 775 rfWrite.fpWen := false.B 776 rfWrite.vecWen := false.B 777 rfWrite.v0Wen := this.v0Wen 778 rfWrite.vlWen := false.B 779 rfWrite 780 } 781 782 def asVlRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 783 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VlData()).addrWidth))) 784 rfWrite.wen := this.vlWen && fire 785 rfWrite.addr := this.pdest 786 rfWrite.data := this.data 787 rfWrite.intWen := false.B 788 rfWrite.fpWen := false.B 789 rfWrite.vecWen := false.B 790 rfWrite.v0Wen := false.B 791 rfWrite.vlWen := this.vlWen 792 rfWrite 793 } 794 } 795 796 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 797 // / 798 // [IssueQueue]--> ExuInput -- 799 class ExuBypassBundle( 800 val params: ExeUnitParams, 801 )(implicit 802 val p: Parameters 803 ) extends Bundle { 804 val data = UInt(params.destDataBitsMax.W) 805 val pdest = UInt(params.wbPregIdxWidth.W) 806 } 807 808 class ExceptionInfo(implicit p: Parameters) extends XSBundle { 809 val pc = UInt(VAddrData().dataWidth.W) 810 val instr = UInt(32.W) 811 val commitType = CommitType() 812 val exceptionVec = ExceptionVec() 813 val gpaddr = UInt(GPAddrBits.W) 814 val singleStep = Bool() 815 val crossPageIPFFix = Bool() 816 val isInterrupt = Bool() 817 val isHls = Bool() 818 val vls = Bool() 819 val trigger = new TriggerCf 820 } 821 822 object UopIdx { 823 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 824 } 825 826 object FuLatency { 827 def apply(): UInt = UInt(width.W) 828 829 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 830 } 831 832 object ExuOH { 833 def apply(exuNum: Int): UInt = UInt(exuNum.W) 834 835 def apply()(implicit p: Parameters): UInt = UInt(width.W) 836 837 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 838 } 839 840 object ExuVec { 841 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 842 843 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 844 845 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 846 } 847 848 class CancelSignal(implicit p: Parameters) extends XSBundle { 849 val rfWen = Bool() 850 val fpWen = Bool() 851 val vecWen = Bool() 852 val v0Wen = Bool() 853 val vlWen = Bool() 854 val pdest = UInt(PhyRegIdxWidth.W) 855 } 856 857 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 858 val uop = new DynInst 859 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 860 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 861 val isFirstIssue = Bool() 862 val flowNum = OptionWrapper(isVector, NumLsElem()) 863 864 def src_rs1 = src(0) 865 def src_stride = src(1) 866 def src_vs3 = src(2) 867 def src_mask = if (isVector) src(3) else 0.U 868 def src_vl = if (isVector) src(4) else 0.U 869 } 870 871 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 872 val uop = new DynInst 873 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 874 val mask = if (isVector) Some(UInt(VLEN.W)) else None 875 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 876 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 877 val debug = new DebugBundle 878 879 def isVls = FuType.isVls(uop.fuType) 880 } 881 882 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 883 val uop = new DynInst 884 val flag = UInt(1.W) 885 } 886 887 object LoadShouldCancel { 888 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 889 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(0)}.reduce(_ || _)) 890 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 891 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 892 } 893 } 894} 895