1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24import yunsuan.vector.VIFuParam 25 26object Bundles { 27 /** 28 * Connect Same Name Port like bundleSource := bundleSinkBudle. 29 * 30 * There is no limit to the number of ports on both sides. 31 * 32 * Don't forget to connect the remaining ports! 33 */ 34 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 35 bundleSource.elements.foreach { case (name, data) => 36 if (bundleSink.elements.contains(name)) 37 data := bundleSink.elements(name) 38 } 39 } 40 // frontend -> backend 41 class StaticInst(implicit p: Parameters) extends XSBundle { 42 val instr = UInt(32.W) 43 val pc = UInt(VAddrBits.W) 44 val foldpc = UInt(MemPredPCWidth.W) 45 val exceptionVec = ExceptionVec() 46 val trigger = new TriggerCf 47 val preDecodeInfo = new PreDecodeInfo 48 val pred_taken = Bool() 49 val crossPageIPFFix = Bool() 50 val ftqPtr = new FtqPtr 51 val ftqOffset = UInt(log2Up(PredictWidth).W) 52 53 def connectCtrlFlow(source: CtrlFlow): Unit = { 54 this.instr := source.instr 55 this.pc := source.pc 56 this.foldpc := source.foldpc 57 this.exceptionVec := source.exceptionVec 58 this.trigger := source.trigger 59 this.preDecodeInfo := source.pd 60 this.pred_taken := source.pred_taken 61 this.crossPageIPFFix := source.crossPageIPFFix 62 this.ftqPtr := source.ftqPtr 63 this.ftqOffset := source.ftqOffset 64 } 65 } 66 67 // StaticInst --[Decode]--> DecodedInst 68 class DecodedInst(implicit p: Parameters) extends XSBundle { 69 def numSrc = backendParams.numSrc 70 // passed from StaticInst 71 val instr = UInt(32.W) 72 val pc = UInt(VAddrBits.W) 73 val foldpc = UInt(MemPredPCWidth.W) 74 val exceptionVec = ExceptionVec() 75 val trigger = new TriggerCf 76 val preDecodeInfo = new PreDecodeInfo 77 val pred_taken = Bool() 78 val crossPageIPFFix = Bool() 79 val ftqPtr = new FtqPtr 80 val ftqOffset = UInt(log2Up(PredictWidth).W) 81 // decoded 82 val srcType = Vec(numSrc, SrcType()) 83 val lsrc = Vec(numSrc, UInt(LogicRegsWidth.W)) 84 val ldest = UInt(LogicRegsWidth.W) 85 val fuType = FuType() 86 val fuOpType = FuOpType() 87 val rfWen = Bool() 88 val fpWen = Bool() 89 val vecWen = Bool() 90 val v0Wen = Bool() 91 val vlWen = Bool() 92 val isXSTrap = Bool() 93 val waitForward = Bool() // no speculate execution 94 val blockBackward = Bool() 95 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 96 val canRobCompress = Bool() 97 val selImm = SelImm() 98 val imm = UInt(ImmUnion.maxLen.W) 99 val fpu = new FPUCtrlSignals 100 val vpu = new VPUCtrlSignals 101 val vlsInstr = Bool() 102 val wfflags = Bool() 103 val isMove = Bool() 104 val uopIdx = UopIdx() 105 val uopSplitType = UopSplitType() 106 val isVset = Bool() 107 val firstUop = Bool() 108 val lastUop = Bool() 109 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 110 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 111 val commitType = CommitType() // Todo: remove it 112 113 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 114 115 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 116 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 117 118 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 119 val decoder: Seq[UInt] = ListLookup( 120 inst, XDecode.decodeDefault.map(bitPatToUInt), 121 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 122 ) 123 allSignals zip decoder foreach { case (s, d) => s := d } 124 debug_fuType.foreach(_ := fuType) 125 this 126 } 127 128 def isSoftPrefetch: Bool = { 129 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 130 } 131 132 def connectStaticInst(source: StaticInst): Unit = { 133 for ((name, data) <- this.elements) { 134 if (source.elements.contains(name)) { 135 data := source.elements(name) 136 } 137 } 138 } 139 } 140 141 // DecodedInst --[Rename]--> DynInst 142 class DynInst(implicit p: Parameters) extends XSBundle { 143 def numSrc = backendParams.numSrc 144 // passed from StaticInst 145 val instr = UInt(32.W) 146 val pc = UInt(VAddrBits.W) 147 val foldpc = UInt(MemPredPCWidth.W) 148 val exceptionVec = ExceptionVec() 149 val hasException = Bool() 150 val trigger = new TriggerCf 151 val preDecodeInfo = new PreDecodeInfo 152 val pred_taken = Bool() 153 val crossPageIPFFix = Bool() 154 val ftqPtr = new FtqPtr 155 val ftqOffset = UInt(log2Up(PredictWidth).W) 156 // passed from DecodedInst 157 val srcType = Vec(numSrc, SrcType()) 158 val ldest = UInt(LogicRegsWidth.W) 159 val fuType = FuType() 160 val fuOpType = FuOpType() 161 val rfWen = Bool() 162 val fpWen = Bool() 163 val vecWen = Bool() 164 val v0Wen = Bool() 165 val vlWen = Bool() 166 val isXSTrap = Bool() 167 val waitForward = Bool() // no speculate execution 168 val blockBackward = Bool() 169 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 170 val canRobCompress = Bool() 171 val selImm = SelImm() 172 val imm = UInt(32.W) 173 val fpu = new FPUCtrlSignals 174 val vpu = new VPUCtrlSignals 175 val vlsInstr = Bool() 176 val wfflags = Bool() 177 val isMove = Bool() 178 val uopIdx = UopIdx() 179 val isVset = Bool() 180 val firstUop = Bool() 181 val lastUop = Bool() 182 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 183 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 184 val commitType = CommitType() 185 // rename 186 val srcState = Vec(numSrc, SrcState()) 187 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 188 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 189 val pdest = UInt(PhyRegIdxWidth.W) 190 val robIdx = new RobPtr 191 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 192 val dirtyFs = Bool() 193 val dirtyVs = Bool() 194 195 val eliminatedMove = Bool() 196 // Take snapshot at this CFI inst 197 val snapshot = Bool() 198 val debugInfo = new PerfDebugInfo 199 val storeSetHit = Bool() // inst has been allocated an store set 200 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 201 // Load wait is needed 202 // load inst will not be executed until former store (predicted by mdp) addr calcuated 203 val loadWaitBit = Bool() 204 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 205 // load inst will not be executed until ALL former store addr calcuated 206 val loadWaitStrict = Bool() 207 val ssid = UInt(SSIDWidth.W) 208 // Todo 209 val lqIdx = new LqPtr 210 val sqIdx = new SqPtr 211 // debug module 212 val singleStep = Bool() 213 // schedule 214 val replayInst = Bool() 215 216 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 217 218 val numLsElem = NumLsElem() 219 220 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 221 222 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 223 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 224 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 225 226 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 227 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 228 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 229 def isNotSvinval = !FuType.isFence(fuType) 230 231 def isHls: Bool = { 232 fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType) 233 } 234 235 def isVecOPF: Bool = { 236 FuType.isVecOPF(fuType) 237 } 238 239 def srcIsReady: Vec[Bool] = { 240 VecInit(this.srcType.zip(this.srcState).map { 241 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 242 }) 243 } 244 245 def clearExceptions( 246 exceptionBits: Seq[Int] = Seq(), 247 flushPipe : Boolean = false, 248 replayInst : Boolean = false 249 ): DynInst = { 250 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 251 if (!flushPipe) { this.flushPipe := false.B } 252 if (!replayInst) { this.replayInst := false.B } 253 this 254 } 255 256 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen || v0Wen || vlWen 257 } 258 259 trait BundleSource { 260 var wakeupSource = "undefined" 261 var idx = 0 262 } 263 264 /** 265 * 266 * @param pregIdxWidth index width of preg 267 * @param exuIndices exu indices of wakeup bundle 268 */ 269 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int])(implicit p: Parameters) extends XSBundle { 270 val rfWen = Bool() 271 val fpWen = Bool() 272 val vecWen = Bool() 273 val v0Wen = Bool() 274 val vlWen = Bool() 275 val pdest = UInt(pregIdxWidth.W) 276 277 /** 278 * @param successor Seq[(psrc, srcType)] 279 * @return Seq[if wakeup psrc] 280 */ 281 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 282 successor.map { case (thatPsrc, srcType) => 283 val pdestMatch = pdest === thatPsrc 284 pdestMatch && ( 285 SrcType.isFp(srcType) && this.fpWen || 286 SrcType.isXp(srcType) && this.rfWen || 287 SrcType.isVp(srcType) && this.vecWen 288 ) && valid 289 } 290 } 291 def wakeUpV0(successor: (UInt, UInt), valid: Bool): Bool = { 292 val (thatPsrc, srcType) = successor 293 val pdestMatch = pdest === thatPsrc 294 pdestMatch && ( 295 SrcType.isV0(srcType) && this.v0Wen 296 ) && valid 297 } 298 def wakeUpVl(successor: (UInt, UInt), valid: Bool): Bool = { 299 val (thatPsrc, srcType) = successor 300 val pdestMatch = pdest === thatPsrc 301 pdestMatch && ( 302 SrcType.isVp(srcType) && this.vlWen 303 ) && valid 304 } 305 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 306 successor.map { case (thatPsrc, srcType) => 307 val pdestMatch = pdest === thatPsrc 308 pdestMatch && ( 309 SrcType.isFp(srcType) && this.fpWen || 310 SrcType.isXp(srcType) && this.rfWen || 311 SrcType.isVp(srcType) && this.vecWen 312 ) 313 } 314 } 315 def wakeUpV0FromIQ(successor: (UInt, UInt)): Bool = { 316 val (thatPsrc, srcType) = successor 317 val pdestMatch = pdest === thatPsrc 318 pdestMatch && ( 319 SrcType.isV0(srcType) && this.v0Wen 320 ) 321 } 322 def wakeUpVlFromIQ(successor: (UInt, UInt)): Bool = { 323 val (thatPsrc, srcType) = successor 324 val pdestMatch = pdest === thatPsrc 325 pdestMatch && ( 326 SrcType.isVp(srcType) && this.vlWen 327 ) 328 } 329 330 def hasOnlyOneSource: Boolean = exuIndices.size == 1 331 332 def hasMultiSources: Boolean = exuIndices.size > 1 333 334 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 335 336 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 337 338 def exuIdx: Int = { 339 require(hasOnlyOneSource) 340 this.exuIndices.head 341 } 342 } 343 344 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams)(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 345 346 } 347 348 class IssueQueueIQWakeUpBundle( 349 exuIdx: Int, 350 backendParams: BackendParams, 351 copyWakeupOut: Boolean = false, 352 copyNum: Int = 0 353 )(implicit p: Parameters) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 354 val loadDependency = Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)) 355 val is0Lat = Bool() 356 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 357 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 358 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 359 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 360 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 361 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 362 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 363 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 364 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[Vec[Bool]]): Unit = { 365 this.rfWen := exuInput.rfWen.getOrElse(false.B) 366 this.fpWen := exuInput.fpWen.getOrElse(false.B) 367 this.vecWen := exuInput.vecWen.getOrElse(false.B) 368 this.v0Wen := exuInput.v0Wen.getOrElse(false.B) 369 this.vlWen := exuInput.vlWen.getOrElse(false.B) 370 this.pdest := exuInput.pdest 371 } 372 373 def fromExuInput(exuInput: ExuInput): Unit = { 374 this.rfWen := exuInput.rfWen.getOrElse(false.B) 375 this.fpWen := exuInput.fpWen.getOrElse(false.B) 376 this.vecWen := exuInput.vecWen.getOrElse(false.B) 377 this.v0Wen := exuInput.v0Wen.getOrElse(false.B) 378 this.vlWen := exuInput.vlWen.getOrElse(false.B) 379 this.pdest := exuInput.pdest 380 } 381 } 382 383 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 384 // vtype 385 val vill = Bool() 386 val vma = Bool() // 1: agnostic, 0: undisturbed 387 val vta = Bool() // 1: agnostic, 0: undisturbed 388 val vsew = VSew() 389 val vlmul = VLmul() // 1/8~8 --> -3~3 390 391 val vm = Bool() // 0: need v0.t 392 val vstart = Vl() 393 394 // float rounding mode 395 val frm = Frm() 396 // scalar float instr and vector float reduction 397 val fpu = Fpu() 398 // vector fix int rounding mode 399 val vxrm = Vxrm() 400 // vector uop index, exclude other non-vector uop 401 val vuopIdx = UopIdx() 402 val lastUop = Bool() 403 // maybe used if data dependancy 404 val vmask = UInt(V0Data().dataWidth.W) 405 val vl = Vl() 406 407 // vector load/store 408 val nf = Nf() 409 val veew = VEew() 410 411 val isReverse = Bool() // vrsub, vrdiv 412 val isExt = Bool() 413 val isNarrow = Bool() 414 val isDstMask = Bool() // vvm, vvvm, mmm 415 val isOpMask = Bool() // vmand, vmnand 416 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 417 418 val isDependOldvd = Bool() // some instruction's computation depends on oldvd 419 val isWritePartVd = Bool() // some instruction's computation writes part of vd, such as vredsum 420 421 def vtype: VType = { 422 val res = Wire(VType()) 423 res.illegal := this.vill 424 res.vma := this.vma 425 res.vta := this.vta 426 res.vsew := this.vsew 427 res.vlmul := this.vlmul 428 res 429 } 430 431 def vconfig: VConfig = { 432 val res = Wire(VConfig()) 433 res.vtype := this.vtype 434 res.vl := this.vl 435 res 436 } 437 438 def connectVType(source: VType): Unit = { 439 this.vill := source.illegal 440 this.vma := source.vma 441 this.vta := source.vta 442 this.vsew := source.vsew 443 this.vlmul := source.vlmul 444 } 445 } 446 447 // DynInst --[IssueQueue]--> DataPath 448 class IssueQueueIssueBundle( 449 iqParams: IssueBlockParams, 450 val exuParams: ExeUnitParams, 451 )(implicit 452 p: Parameters 453 ) extends Bundle { 454 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 455 456 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 457 rfReadDataCfgSet.map((set: Set[DataConfig]) => 458 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 459 ) 460 )) 461 462 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 463 val immType = SelImm() // used to select imm extractor 464 val common = new ExuInput(exuParams) 465 val addrOH = UInt(iqParams.numEntries.W) 466 467 def exuIdx = exuParams.exuIdx 468 def getSource: SchedulerType = exuParams.getWBSource 469 470 def getRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 471 rf.zip(srcType).map { 472 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 473 makeValid(issueValid, rfRd.head) 474 }.toSeq 475 } 476 } 477 478 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 479 val issueQueueParams = this.params 480 val og0resp = Valid(new EntryDeqRespBundle) 481 val og1resp = Valid(new EntryDeqRespBundle) 482 } 483 484 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 485 private val intCertainLat = params.intLatencyCertain 486 private val fpCertainLat = params.fpLatencyCertain 487 private val vfCertainLat = params.vfLatencyCertain 488 private val v0CertainLat = params.v0LatencyCertain 489 private val vlCertainLat = params.vlLatencyCertain 490 private val intLat = params.intLatencyValMax 491 private val fpLat = params.fpLatencyValMax 492 private val vfLat = params.vfLatencyValMax 493 private val v0Lat = params.v0LatencyValMax 494 private val vlLat = params.vlLatencyValMax 495 496 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 497 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 498 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 499 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 500 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 501 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 502 val fpDeqRespSet = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 503 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 504 val v0DeqRespSet = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 505 val vlDeqRespSet = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 506 } 507 508 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 509 private val intCertainLat = params.intLatencyCertain 510 private val fpCertainLat = params.fpLatencyCertain 511 private val vfCertainLat = params.vfLatencyCertain 512 private val v0CertainLat = params.v0LatencyCertain 513 private val vlCertainLat = params.vlLatencyCertain 514 private val intLat = params.intLatencyValMax 515 private val fpLat = params.fpLatencyValMax 516 private val vfLat = params.vfLatencyValMax 517 private val v0Lat = params.v0LatencyValMax 518 private val vlLat = params.vlLatencyValMax 519 520 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 521 val fpWbBusyTable = OptionWrapper(fpCertainLat, UInt((fpLat + 1).W)) 522 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 523 val v0WbBusyTable = OptionWrapper(v0CertainLat, UInt((v0Lat + 1).W)) 524 val vlWbBusyTable = OptionWrapper(vlCertainLat, UInt((vlLat + 1).W)) 525 } 526 527 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 528 private val intCertainLat = params.intLatencyCertain 529 private val fpCertainLat = params.fpLatencyCertain 530 private val vfCertainLat = params.vfLatencyCertain 531 private val v0CertainLat = params.v0LatencyCertain 532 private val vlCertainLat = params.vlLatencyCertain 533 534 val intConflict = OptionWrapper(intCertainLat, Bool()) 535 val fpConflict = OptionWrapper(fpCertainLat, Bool()) 536 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 537 val v0Conflict = OptionWrapper(v0CertainLat, Bool()) 538 val vlConflict = OptionWrapper(vlCertainLat, Bool()) 539 } 540 541 class ImmInfo extends Bundle { 542 val imm = UInt(32.W) 543 val immType = SelImm() 544 } 545 546 // DataPath --[ExuInput]--> Exu 547 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 548 val fuType = FuType() 549 val fuOpType = FuOpType() 550 val src = Vec(params.numRegSrc, UInt(params.srcDataBitsMax.W)) 551 val imm = UInt(32.W) 552 val robIdx = new RobPtr 553 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 554 val isFirstIssue = Bool() // Only used by store yet 555 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 556 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 557 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 558 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 559 val v0WenCopy = OptionWrapper(copyWakeupOut && params.needV0Wen, Vec(copyNum, Bool())) 560 val vlWenCopy = OptionWrapper(copyWakeupOut && params.needVlWen, Vec(copyNum, Bool())) 561 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) 562 val pdest = UInt(params.wbPregIdxWidth.W) 563 val rfWen = if (params.needIntWen) Some(Bool()) else None 564 val fpWen = if (params.needFpWen) Some(Bool()) else None 565 val vecWen = if (params.needVecWen) Some(Bool()) else None 566 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 567 val vlWen = if (params.needVlWen) Some(Bool()) else None 568 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 569 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 570 val flushPipe = if (params.flushPipe) Some(Bool()) else None 571 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 572 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 573 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 574 Some(new FtqPtr) else None 575 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu || params.hasCSR) 576 Some(UInt(log2Up(PredictWidth).W)) else None 577 val predictInfo = if (params.needPdInfo) Some(new Bundle { 578 val target = UInt(VAddrData().dataWidth.W) 579 val taken = Bool() 580 }) else None 581 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 582 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 583 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 584 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 585 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 586 // only vector load store need 587 val numLsElem = OptionWrapper(params.hasVecLsFu, NumLsElem()) 588 589 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 590 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 591 val dataSources = Vec(params.numRegSrc, DataSource()) 592 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 593 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 594 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))) 595 596 val perfDebugInfo = new PerfDebugInfo() 597 598 def exuIdx = this.params.exuIdx 599 600 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 601 if (params.isIQWakeUpSink) { 602 require( 603 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 604 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 605 ) 606 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 607 case(exuOH: Vec[Bool], srcTimer: UInt) => 608 (exuOH.asUInt & og0CancelOH).orR && srcTimer === 1.U 609 }.reduce(_ | _) 610 l1Cancel 611 } else { 612 false.B 613 } 614 } 615 616 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 617 // src is assigned to rfReadData 618 this.fuType := source.common.fuType 619 this.fuOpType := source.common.fuOpType 620 this.imm := source.common.imm 621 this.robIdx := source.common.robIdx 622 this.pdest := source.common.pdest 623 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 624 this.iqIdx := source.common.iqIdx // Only used by mem feedback 625 this.dataSources := source.common.dataSources 626 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 627 this.rfWen .foreach(_ := source.common.rfWen.get) 628 this.fpWen .foreach(_ := source.common.fpWen.get) 629 this.vecWen .foreach(_ := source.common.vecWen.get) 630 this.v0Wen .foreach(_ := source.common.v0Wen.get) 631 this.vlWen .foreach(_ := source.common.vlWen.get) 632 this.fpu .foreach(_ := source.common.fpu.get) 633 this.vpu .foreach(_ := source.common.vpu.get) 634 this.flushPipe .foreach(_ := source.common.flushPipe.get) 635 this.pc .foreach(_ := source.common.pc.get) 636 this.preDecode .foreach(_ := source.common.preDecode.get) 637 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 638 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 639 this.predictInfo .foreach(_ := source.common.predictInfo.get) 640 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 641 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 642 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 643 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 644 this.ssid .foreach(_ := source.common.ssid.get) 645 this.lqIdx .foreach(_ := source.common.lqIdx.get) 646 this.sqIdx .foreach(_ := source.common.sqIdx.get) 647 this.numLsElem .foreach(_ := source.common.numLsElem.get) 648 this.srcTimer .foreach(_ := source.common.srcTimer.get) 649 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 650 } 651 } 652 653 // ExuInput --[FuncUnit]--> ExuOutput 654 class ExuOutput( 655 val params: ExeUnitParams, 656 )(implicit 657 val p: Parameters 658 ) extends Bundle with BundleSource with HasXSParameter { 659 val data = Vec(params.wbPathNum, UInt(params.destDataBitsMax.W)) 660 val pdest = UInt(params.wbPregIdxWidth.W) 661 val robIdx = new RobPtr 662 val intWen = if (params.needIntWen) Some(Bool()) else None 663 val fpWen = if (params.needFpWen) Some(Bool()) else None 664 val vecWen = if (params.needVecWen) Some(Bool()) else None 665 val v0Wen = if (params.needV0Wen) Some(Bool()) else None 666 val vlWen = if (params.needVlWen) Some(Bool()) else None 667 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 668 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 669 val wflags = if (params.writeFflags) Some(Bool()) else None 670 val vxsat = if (params.writeVxsat) Some(Bool()) else None 671 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 672 val flushPipe = if (params.flushPipe) Some(Bool()) else None 673 val replay = if (params.replayInst) Some(Bool()) else None 674 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 675 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 676 Some(new SqPtr()) else None 677 val trigger = if (params.trigger) Some(new TriggerCf) else None 678 // uop info 679 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 680 // vldu used only 681 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 682 val vpu = new VPUCtrlSignals 683 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 684 val vdIdx = UInt(3.W) 685 val vdIdxInField = UInt(3.W) 686 val isIndexed = Bool() 687 val isMasked = Bool() 688 }) 689 val debug = new DebugBundle 690 val debugInfo = new PerfDebugInfo 691 } 692 693 // ExuOutput + DynInst --> WriteBackBundle 694 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 695 val rfWen = Bool() 696 val fpWen = Bool() 697 val vecWen = Bool() 698 val v0Wen = Bool() 699 val vlWen = Bool() 700 val pdest = UInt(params.pregIdxWidth(backendParams).W) 701 val data = UInt(params.dataWidth.W) 702 val robIdx = new RobPtr()(p) 703 val flushPipe = Bool() 704 val replayInst = Bool() 705 val redirect = ValidIO(new Redirect) 706 val fflags = UInt(5.W) 707 val vxsat = Bool() 708 val exceptionVec = ExceptionVec() 709 val debug = new DebugBundle 710 val debugInfo = new PerfDebugInfo 711 712 this.wakeupSource = s"WB(${params.toString})" 713 714 def fromExuOutput(source: ExuOutput, wbType: String) = { 715 val typeMap = Map("int" -> 0, "fp" -> 1, "vf" -> 2, "v0" -> 3, "vl" -> 4) 716 this.rfWen := source.intWen.getOrElse(false.B) 717 this.fpWen := source.fpWen.getOrElse(false.B) 718 this.vecWen := source.vecWen.getOrElse(false.B) 719 this.v0Wen := source.v0Wen.getOrElse(false.B) 720 this.vlWen := source.vlWen.getOrElse(false.B) 721 this.pdest := source.pdest 722 this.data := source.data(source.params.wbIndex(typeMap(wbType))) 723 this.robIdx := source.robIdx 724 this.flushPipe := source.flushPipe.getOrElse(false.B) 725 this.replayInst := source.replay.getOrElse(false.B) 726 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 727 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 728 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 729 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 730 this.debug := source.debug 731 this.debugInfo := source.debugInfo 732 } 733 734 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 735 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 736 rfWrite.wen := this.rfWen && fire 737 rfWrite.addr := this.pdest 738 rfWrite.data := this.data 739 rfWrite.intWen := this.rfWen 740 rfWrite.fpWen := false.B 741 rfWrite.vecWen := false.B 742 rfWrite.v0Wen := false.B 743 rfWrite.vlWen := false.B 744 rfWrite 745 } 746 747 def asFpRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 748 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(FpData()).addrWidth))) 749 rfWrite.wen := this.fpWen && fire 750 rfWrite.addr := this.pdest 751 rfWrite.data := this.data 752 rfWrite.intWen := false.B 753 rfWrite.fpWen := this.fpWen 754 rfWrite.vecWen := false.B 755 rfWrite.v0Wen := false.B 756 rfWrite.vlWen := false.B 757 rfWrite 758 } 759 760 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 761 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 762 rfWrite.wen := this.vecWen && fire 763 rfWrite.addr := this.pdest 764 rfWrite.data := this.data 765 rfWrite.intWen := false.B 766 rfWrite.fpWen := false.B 767 rfWrite.vecWen := this.vecWen 768 rfWrite.v0Wen := false.B 769 rfWrite.vlWen := false.B 770 rfWrite 771 } 772 773 def asV0RfWriteBundle(fire: Bool): RfWritePortWithConfig = { 774 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(V0Data()).addrWidth))) 775 rfWrite.wen := this.v0Wen && fire 776 rfWrite.addr := this.pdest 777 rfWrite.data := this.data 778 rfWrite.intWen := false.B 779 rfWrite.fpWen := false.B 780 rfWrite.vecWen := false.B 781 rfWrite.v0Wen := this.v0Wen 782 rfWrite.vlWen := false.B 783 rfWrite 784 } 785 786 def asVlRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 787 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VlData()).addrWidth))) 788 rfWrite.wen := this.vlWen && fire 789 rfWrite.addr := this.pdest 790 rfWrite.data := this.data 791 rfWrite.intWen := false.B 792 rfWrite.fpWen := false.B 793 rfWrite.vecWen := false.B 794 rfWrite.v0Wen := false.B 795 rfWrite.vlWen := this.vlWen 796 rfWrite 797 } 798 } 799 800 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 801 // / 802 // [IssueQueue]--> ExuInput -- 803 class ExuBypassBundle( 804 val params: ExeUnitParams, 805 )(implicit 806 val p: Parameters 807 ) extends Bundle { 808 val data = UInt(params.destDataBitsMax.W) 809 val pdest = UInt(params.wbPregIdxWidth.W) 810 } 811 812 class ExceptionInfo(implicit p: Parameters) extends XSBundle { 813 val pc = UInt(VAddrData().dataWidth.W) 814 val instr = UInt(32.W) 815 val commitType = CommitType() 816 val exceptionVec = ExceptionVec() 817 val gpaddr = UInt(GPAddrBits.W) 818 val singleStep = Bool() 819 val crossPageIPFFix = Bool() 820 val isInterrupt = Bool() 821 val isHls = Bool() 822 val vls = Bool() 823 val trigger = new TriggerCf 824 } 825 826 object UopIdx { 827 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 828 } 829 830 object FuLatency { 831 def apply(): UInt = UInt(width.W) 832 833 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 834 } 835 836 object ExuOH { 837 def apply(exuNum: Int): UInt = UInt(exuNum.W) 838 839 def apply()(implicit p: Parameters): UInt = UInt(width.W) 840 841 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 842 } 843 844 object ExuVec { 845 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 846 847 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 848 849 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 850 } 851 852 class CancelSignal(implicit p: Parameters) extends XSBundle { 853 val rfWen = Bool() 854 val fpWen = Bool() 855 val vecWen = Bool() 856 val v0Wen = Bool() 857 val vlWen = Bool() 858 val pdest = UInt(PhyRegIdxWidth.W) 859 } 860 861 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 862 val uop = new DynInst 863 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 864 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 865 val isFirstIssue = Bool() 866 val flowNum = OptionWrapper(isVector, NumLsElem()) 867 868 def src_rs1 = src(0) 869 def src_stride = src(1) 870 def src_vs3 = src(2) 871 def src_mask = if (isVector) src(3) else 0.U 872 def src_vl = if (isVector) src(4) else 0.U 873 } 874 875 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 876 val uop = new DynInst 877 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 878 val mask = if (isVector) Some(UInt(VLEN.W)) else None 879 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 880 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 881 val debug = new DebugBundle 882 883 def isVls = FuType.isVls(uop.fuType) 884 } 885 886 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 887 val uop = new DynInst 888 val flag = UInt(1.W) 889 } 890 891 object LoadShouldCancel { 892 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 893 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(0)}.reduce(_ || _)) 894 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 895 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 896 } 897 } 898} 899